WWDG_Example

  ******************** (C) COPYRIGHT 2010 STMicroelectronics *******************
  * @file    WWDG/readme.txt 
  * @author  MCD Application Team
  * @version V3.4.0
  * @date    10/15/2010
  * @brief   Description of the WWDG Example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
   
Example Description

This example shows how to update at regulate period the WWDG counter using the Early Wakeup interrupt (EWI).

The WWDG timeout is set to 87.42ms on Value line devices and to 58.25 ms on other devices, the refresh window is set to 65 and the EWI is enabled. When the WWDG counter reaches 64, the EWI is generated. In the WWDG ISR, the counter is refreshed to prevent a WWDG reset and LED2 is toggled.

An EXTI Line is connected to a GPIO pin, and configured to generate an interrupt on the falling edge of the signal. In the NVIC (nested vectored interrupt controller), the EXTI Line interrupt vector is enabled with a priority equal to 0 and the WWDG interrupt vector is enabled with a priority equal to 1 (EXTI IT > WWDG IT).

The EXTI Line is used to simulate a software failure: once the EXTI Line event occurs, by pressing the Key push-button, the corresponding interrupt is served. In the ISR, the LED2 turns off and the EXTI Line pending bit is not cleared. So the CPU executes the EXTI Line ISR indefinitely and the WWDG ISR is never executed (the WWDG counter is not updated). As a result, when the WWDG counter falls to 63, the WWDG reset occurs. If the WWDG reset is generated, after the system resumes from reset, LED1 turns on.

If the EXTI Line event does not occur, the WWDG counter is indefinitely refreshed in the WWDG ISR, and there is no WWDG reset.

In this example the system clock is set to 24 MHz on Value line devices and to 72 MHz on other devices.

Directory contents
Hardware and Software environment
How to use it ?

In order to make the program work, you must do the following:

Tip: You can tailor the provided project template to run this example, for more details please refer to "stm32f10x_stdperiph_lib_um.chm" user manual; select "Peripheral Examples" then follow the instructions provided in "How to proceed" section.

Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2010 STMicroelectronics

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