IWDG_Example

  ******************** (C) COPYRIGHT 2010 STMicroelectronics *******************
  * @file    IWDG/readme.txt 
  * @author  MCD Application Team
  * @version V3.4.0
  * @date    10/15/2010
  * @brief   Description of the IWDG Example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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  ******************************************************************************
   
Example Description

This example shows how to reload at regulate period the IWDG counter using the SysTick interrupt. The IWDG timeout is set to 280 ms (the timeout may vary due to LSI frequency dispersion).

SysTick is configured to generate an interrupt every 250 ms. In the SysTick interrupt service routine (ISR), the IWDG counter is reloaded to prevent an IWDG reset and LED2 is toggled. An EXTI is connected to a specific GPIO pin and configured to generate an interrupt on its falling edge. In the NVIC, this EXTI line corresspondant interrupt vector is enabled with a priority equal to 0, and the SysTick interrupt vector priority is set to 1 (EXTI IT > SysTick IT).

The EXTI Line is used to simulate a software failure: when the EXTI Line event is triggered (by pressing the Key push-button on the board), the corresponding interrupt is served. In the ISR, the LED2turns off and the EXTI line pending bit is not cleared. So the CPU executes the EXTI line ISR indefinitely and the SysTick ISR is never entered (IWDG counter not reloaded). As a result, when the IWDG counter reaches 00h, the IWDG generates a reset. If the IWDG reset is generated, LED1 is turned on after the system resumes operation.

If the EXTI Line event does not occur, the IWDG counter is indefinitely reloaded in the SysTick ISR, which prevents any IWDG reset.

In this example the system clock is set to 24 MHz on Value line devices and to 72MHz on other devices.

Note:
The IWDG Counter can be only written when the RVU flag is reset. In this example, as the SysTick period is too higher than the IWDG Counter Update timing (5 Cycles 40KHz RC), the Reload Value Update "RVU" flag is not checked before reloading the counter.
Directory contents
Hardware and Software environment
How to use it ?

In order to make the program work, you must do the following:

Tip: You can tailor the provided project template to run this example, for more details please refer to "stm32f10x_stdperiph_lib_um.chm" user manual; select "Peripheral Examples" then follow the instructions provided in "How to proceed" section.

Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2010 STMicroelectronics

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