I2S_SPI_I2S_Switch

  ******************** (C) COPYRIGHT 2010 STMicroelectronics *******************
  * @file    I2S/SPI_I2S_Switch/readme.txt 
  * @author  MCD Application Team
  * @version V3.4.0
  * @date    10/15/2010
  * @brief   Description of the SPI_I2S_Switch Example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
   
Example Description

This example provides a description of how to set a communication between two SPIs in I2S mode, and how to switch between SPI and I2S modes, performing a transfer from Master to Slave in I2S modes then a transfer from master to slave in SPI mode and finally a transfer from Slave to Master in I2S mode.

I2S2 is configured as master transmitter and I2S3 as slave reciever and both are in Phillips standard configuration with 16bit data size in 32bit packet length and 48KHz audio frequnecy.

In the first phase, the master I2S2 starts the I2S2_Buffer_Tx transfer while the slave I2S3 receieves and loads the values in I2S3_Buffer_Rx. Once the transfer is completed a comparison is done and TransferStatus1 gives the data transfer status where it is PASSED if transmitted and received data are the same otherwise it is FAILED.

In the second step, both preripherals are configured in SPI modes (simplex communication) and SPI2_Buffer_Tx transfer is performed in simplex mode from SPI2 to SPI3.Once the transfer is completed a comparison is done and TransferStatus2 gives the data transfer status where it is PASSED if transmitted and received data are the same otherwise it is FAILED. As the master/slave mode is managed by software (the master is the clock (CK and WS) generator), this allows to I2S2 to become slave transmitter and I2S3 to become master receiver whithout hardware modification.

In the third step, the slave I2S2 prepares the first data to be sent before the master is enabled. Once the master is enabled, the clocks are released from the master and the data are released on the slave. Once the transfer is completed a comparison is done and TransferStatus3 gives the data transfer status where it is PASSED if transmitted and received data are the same otherwise it is FAILED.

Directory contents
Hardware and Software environment

Since some SPI3/I2S3 pins are shared with JTAG pins (SPI3_NSS/I2S3_WS with JTDI and SPI3_SCK/I2S3_CK with JTDO), they are not controlled by the I/O controller and are reserved for JTAG usage (after each Reset). For this purpose prior to configure the SPI3/I2S3 pins:

How to use it ?

In order to make the program work, you must do the following:

Tip: You can tailor the provided project template to run this example, for more details please refer to "stm32f10x_stdperiph_lib_um.chm" user manual; select "Peripheral Examples" then follow the instructions provided in "How to proceed" section.

Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2010 STMicroelectronics

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