stm32f10x_tim.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_tim.h
00004   * @author  MCD Application Team
00005   * @version V3.4.0
00006   * @date    10/15/2010
00007   * @brief   This file contains all the functions prototypes for the TIM firmware 
00008   *          library.
00009   ******************************************************************************
00010   * @copy
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
00020   */ 
00021 
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_TIM_H
00024 #define __STM32F10x_TIM_H
00025 
00026 #ifdef __cplusplus
00027  extern "C" {
00028 #endif
00029 
00030 /* Includes ------------------------------------------------------------------*/
00031 #include "stm32f10x.h"
00032 
00033 /** @addtogroup STM32F10x_StdPeriph_Driver
00034   * @{
00035   */
00036 
00037 /** @addtogroup TIM
00038   * @{
00039   */ 
00040 
00041 /** @defgroup TIM_Exported_Types
00042   * @{
00043   */ 
00044 
00045 /** 
00046   * @brief  TIM Time Base Init structure definition
00047   * @note   This sturcture is used with all TIMx except for TIM6 and TIM7.    
00048   */
00049 
00050 typedef struct
00051 {
00052   uint16_t TIM_Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
00053                                        This parameter can be a number between 0x0000 and 0xFFFF */
00054 
00055   uint16_t TIM_CounterMode;       /*!< Specifies the counter mode.
00056                                        This parameter can be a value of @ref TIM_Counter_Mode */
00057 
00058   uint16_t TIM_Period;            /*!< Specifies the period value to be loaded into the active
00059                                        Auto-Reload Register at the next update event.
00060                                        This parameter must be a number between 0x0000 and 0xFFFF.  */ 
00061 
00062   uint16_t TIM_ClockDivision;     /*!< Specifies the clock division.
00063                                       This parameter can be a value of @ref TIM_Clock_Division_CKD */
00064 
00065   uint8_t TIM_RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
00066                                        reaches zero, an update event is generated and counting restarts
00067                                        from the RCR value (N).
00068                                        This means in PWM mode that (N+1) corresponds to:
00069                                           - the number of PWM periods in edge-aligned mode
00070                                           - the number of half PWM period in center-aligned mode
00071                                        This parameter must be a number between 0x00 and 0xFF. 
00072                                        @note This parameter is valid only for TIM1 and TIM8. */
00073 } TIM_TimeBaseInitTypeDef;       
00074 
00075 /** 
00076   * @brief  TIM Output Compare Init structure definition  
00077   */
00078 
00079 typedef struct
00080 {
00081   uint16_t TIM_OCMode;        /*!< Specifies the TIM mode.
00082                                    This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
00083 
00084   uint16_t TIM_OutputState;   /*!< Specifies the TIM Output Compare state.
00085                                    This parameter can be a value of @ref TIM_Output_Compare_state */
00086 
00087   uint16_t TIM_OutputNState;  /*!< Specifies the TIM complementary Output Compare state.
00088                                    This parameter can be a value of @ref TIM_Output_Compare_N_state
00089                                    @note This parameter is valid only for TIM1 and TIM8. */
00090 
00091   uint16_t TIM_Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
00092                                    This parameter can be a number between 0x0000 and 0xFFFF */
00093 
00094   uint16_t TIM_OCPolarity;    /*!< Specifies the output polarity.
00095                                    This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00096 
00097   uint16_t TIM_OCNPolarity;   /*!< Specifies the complementary output polarity.
00098                                    This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
00099                                    @note This parameter is valid only for TIM1 and TIM8. */
00100 
00101   uint16_t TIM_OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00102                                    This parameter can be a value of @ref TIM_Output_Compare_Idle_State
00103                                    @note This parameter is valid only for TIM1 and TIM8. */
00104 
00105   uint16_t TIM_OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00106                                    This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
00107                                    @note This parameter is valid only for TIM1 and TIM8. */
00108 } TIM_OCInitTypeDef;
00109 
00110 /** 
00111   * @brief  TIM Input Capture Init structure definition  
00112   */
00113 
00114 typedef struct
00115 {
00116 
00117   uint16_t TIM_Channel;      /*!< Specifies the TIM channel.
00118                                   This parameter can be a value of @ref TIM_Channel */
00119 
00120   uint16_t TIM_ICPolarity;   /*!< Specifies the active edge of the input signal.
00121                                   This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00122 
00123   uint16_t TIM_ICSelection;  /*!< Specifies the input.
00124                                   This parameter can be a value of @ref TIM_Input_Capture_Selection */
00125 
00126   uint16_t TIM_ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
00127                                   This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00128 
00129   uint16_t TIM_ICFilter;     /*!< Specifies the input capture filter.
00130                                   This parameter can be a number between 0x0 and 0xF */
00131 } TIM_ICInitTypeDef;
00132 
00133 /** 
00134   * @brief  BDTR structure definition 
00135   * @note   This sturcture is used only with TIM1 and TIM8.    
00136   */
00137 
00138 typedef struct
00139 {
00140 
00141   uint16_t TIM_OSSRState;        /*!< Specifies the Off-State selection used in Run mode.
00142                                       This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
00143 
00144   uint16_t TIM_OSSIState;        /*!< Specifies the Off-State used in Idle state.
00145                                       This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
00146 
00147   uint16_t TIM_LOCKLevel;        /*!< Specifies the LOCK level parameters.
00148                                       This parameter can be a value of @ref Lock_level */ 
00149 
00150   uint16_t TIM_DeadTime;         /*!< Specifies the delay time between the switching-off and the
00151                                       switching-on of the outputs.
00152                                       This parameter can be a number between 0x00 and 0xFF  */
00153 
00154   uint16_t TIM_Break;            /*!< Specifies whether the TIM Break input is enabled or not. 
00155                                       This parameter can be a value of @ref Break_Input_enable_disable */
00156 
00157   uint16_t TIM_BreakPolarity;    /*!< Specifies the TIM Break Input pin polarity.
00158                                       This parameter can be a value of @ref Break_Polarity */
00159 
00160   uint16_t TIM_AutomaticOutput;  /*!< Specifies whether the TIM Automatic Output feature is enabled or not. 
00161                                       This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
00162 } TIM_BDTRInitTypeDef;
00163 
00164 /** @defgroup TIM_Exported_constants 
00165   * @{
00166   */
00167 
00168 #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
00169                                    ((PERIPH) == TIM2) || \
00170                                    ((PERIPH) == TIM3) || \
00171                                    ((PERIPH) == TIM4) || \
00172                                    ((PERIPH) == TIM5) || \
00173                                    ((PERIPH) == TIM6) || \
00174                                    ((PERIPH) == TIM7) || \
00175                                    ((PERIPH) == TIM8) || \
00176                                    ((PERIPH) == TIM9) || \
00177                                    ((PERIPH) == TIM10)|| \
00178                                    ((PERIPH) == TIM11)|| \
00179                                    ((PERIPH) == TIM12)|| \
00180                                    ((PERIPH) == TIM13)|| \
00181                                    ((PERIPH) == TIM14)|| \
00182                                    ((PERIPH) == TIM15)|| \
00183                                    ((PERIPH) == TIM16)|| \
00184                                    ((PERIPH) == TIM17))
00185 
00186 /* LIST1: TIM 1 and 8 */
00187 #define IS_TIM_LIST1_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
00188                                       ((PERIPH) == TIM8))
00189 
00190 /* LIST2: TIM 1, 8, 15 16 and 17 */
00191 #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
00192                                      ((PERIPH) == TIM8) || \
00193                                      ((PERIPH) == TIM15)|| \
00194                                      ((PERIPH) == TIM16)|| \
00195                                      ((PERIPH) == TIM17)) 
00196 
00197 /* LIST3: TIM 1, 2, 3, 4, 5 and 8 */
00198 #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
00199                                      ((PERIPH) == TIM2) || \
00200                                      ((PERIPH) == TIM3) || \
00201                                      ((PERIPH) == TIM4) || \
00202                                      ((PERIPH) == TIM5) || \
00203                                      ((PERIPH) == TIM8)) 
00204                                                                                                          
00205 /* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */
00206 #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
00207                                      ((PERIPH) == TIM2) || \
00208                                      ((PERIPH) == TIM3) || \
00209                                      ((PERIPH) == TIM4) || \
00210                                      ((PERIPH) == TIM5) || \
00211                                      ((PERIPH) == TIM8) || \
00212                                      ((PERIPH) == TIM15)|| \
00213                                      ((PERIPH) == TIM16)|| \
00214                                      ((PERIPH) == TIM17))
00215 
00216 /* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */                                            
00217 #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
00218                                      ((PERIPH) == TIM2) || \
00219                                      ((PERIPH) == TIM3) || \
00220                                      ((PERIPH) == TIM4) || \
00221                                      ((PERIPH) == TIM5) || \
00222                                      ((PERIPH) == TIM8) || \
00223                                      ((PERIPH) == TIM15)) 
00224 
00225 /* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */
00226 #define IS_TIM_LIST6_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
00227                                       ((PERIPH) == TIM2) || \
00228                                       ((PERIPH) == TIM3) || \
00229                                       ((PERIPH) == TIM4) || \
00230                                       ((PERIPH) == TIM5) || \
00231                                       ((PERIPH) == TIM8) || \
00232                                       ((PERIPH) == TIM9) || \
00233                                                                           ((PERIPH) == TIM12)|| \
00234                                       ((PERIPH) == TIM15))
00235 
00236 /* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */
00237 #define IS_TIM_LIST7_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
00238                                       ((PERIPH) == TIM2) || \
00239                                       ((PERIPH) == TIM3) || \
00240                                       ((PERIPH) == TIM4) || \
00241                                       ((PERIPH) == TIM5) || \
00242                                       ((PERIPH) == TIM6) || \
00243                                       ((PERIPH) == TIM7) || \
00244                                       ((PERIPH) == TIM8) || \
00245                                       ((PERIPH) == TIM9) || \
00246                                       ((PERIPH) == TIM12)|| \
00247                                       ((PERIPH) == TIM15))                                    
00248 
00249 /* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */                                        
00250 #define IS_TIM_LIST8_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
00251                                       ((PERIPH) == TIM2) || \
00252                                       ((PERIPH) == TIM3) || \
00253                                       ((PERIPH) == TIM4) || \
00254                                       ((PERIPH) == TIM5) || \
00255                                       ((PERIPH) == TIM8) || \
00256                                       ((PERIPH) == TIM9) || \
00257                                       ((PERIPH) == TIM10)|| \
00258                                       ((PERIPH) == TIM11)|| \
00259                                       ((PERIPH) == TIM12)|| \
00260                                       ((PERIPH) == TIM13)|| \
00261                                       ((PERIPH) == TIM14)|| \
00262                                       ((PERIPH) == TIM15)|| \
00263                                       ((PERIPH) == TIM16)|| \
00264                                       ((PERIPH) == TIM17))
00265 
00266 /* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */
00267 #define IS_TIM_LIST9_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
00268                                       ((PERIPH) == TIM2) || \
00269                                       ((PERIPH) == TIM3) || \
00270                                       ((PERIPH) == TIM4) || \
00271                                       ((PERIPH) == TIM5) || \
00272                                       ((PERIPH) == TIM6) || \
00273                                       ((PERIPH) == TIM7) || \
00274                                       ((PERIPH) == TIM8) || \
00275                                       ((PERIPH) == TIM15)|| \
00276                                       ((PERIPH) == TIM16)|| \
00277                                       ((PERIPH) == TIM17))  
00278                                                                                                                                                                                                                           
00279 /**
00280   * @}
00281   */ 
00282 
00283 /** @defgroup TIM_Output_Compare_and_PWM_modes 
00284   * @{
00285   */
00286 
00287 #define TIM_OCMode_Timing                  ((uint16_t)0x0000)
00288 #define TIM_OCMode_Active                  ((uint16_t)0x0010)
00289 #define TIM_OCMode_Inactive                ((uint16_t)0x0020)
00290 #define TIM_OCMode_Toggle                  ((uint16_t)0x0030)
00291 #define TIM_OCMode_PWM1                    ((uint16_t)0x0060)
00292 #define TIM_OCMode_PWM2                    ((uint16_t)0x0070)
00293 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
00294                               ((MODE) == TIM_OCMode_Active) || \
00295                               ((MODE) == TIM_OCMode_Inactive) || \
00296                               ((MODE) == TIM_OCMode_Toggle)|| \
00297                               ((MODE) == TIM_OCMode_PWM1) || \
00298                               ((MODE) == TIM_OCMode_PWM2))
00299 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
00300                           ((MODE) == TIM_OCMode_Active) || \
00301                           ((MODE) == TIM_OCMode_Inactive) || \
00302                           ((MODE) == TIM_OCMode_Toggle)|| \
00303                           ((MODE) == TIM_OCMode_PWM1) || \
00304                           ((MODE) == TIM_OCMode_PWM2) ||        \
00305                           ((MODE) == TIM_ForcedAction_Active) || \
00306                           ((MODE) == TIM_ForcedAction_InActive))
00307 /**
00308   * @}
00309   */
00310 
00311 /** @defgroup TIM_One_Pulse_Mode 
00312   * @{
00313   */
00314 
00315 #define TIM_OPMode_Single                  ((uint16_t)0x0008)
00316 #define TIM_OPMode_Repetitive              ((uint16_t)0x0000)
00317 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
00318                                ((MODE) == TIM_OPMode_Repetitive))
00319 /**
00320   * @}
00321   */ 
00322 
00323 /** @defgroup TIM_Channel 
00324   * @{
00325   */
00326 
00327 #define TIM_Channel_1                      ((uint16_t)0x0000)
00328 #define TIM_Channel_2                      ((uint16_t)0x0004)
00329 #define TIM_Channel_3                      ((uint16_t)0x0008)
00330 #define TIM_Channel_4                      ((uint16_t)0x000C)
00331 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
00332                                  ((CHANNEL) == TIM_Channel_2) || \
00333                                  ((CHANNEL) == TIM_Channel_3) || \
00334                                  ((CHANNEL) == TIM_Channel_4))
00335 #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
00336                                       ((CHANNEL) == TIM_Channel_2))
00337 #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
00338                                                ((CHANNEL) == TIM_Channel_2) || \
00339                                                ((CHANNEL) == TIM_Channel_3))
00340 /**
00341   * @}
00342   */ 
00343 
00344 /** @defgroup TIM_Clock_Division_CKD 
00345   * @{
00346   */
00347 
00348 #define TIM_CKD_DIV1                       ((uint16_t)0x0000)
00349 #define TIM_CKD_DIV2                       ((uint16_t)0x0100)
00350 #define TIM_CKD_DIV4                       ((uint16_t)0x0200)
00351 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
00352                              ((DIV) == TIM_CKD_DIV2) || \
00353                              ((DIV) == TIM_CKD_DIV4))
00354 /**
00355   * @}
00356   */
00357 
00358 /** @defgroup TIM_Counter_Mode 
00359   * @{
00360   */
00361 
00362 #define TIM_CounterMode_Up                 ((uint16_t)0x0000)
00363 #define TIM_CounterMode_Down               ((uint16_t)0x0010)
00364 #define TIM_CounterMode_CenterAligned1     ((uint16_t)0x0020)
00365 #define TIM_CounterMode_CenterAligned2     ((uint16_t)0x0040)
00366 #define TIM_CounterMode_CenterAligned3     ((uint16_t)0x0060)
00367 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) ||  \
00368                                    ((MODE) == TIM_CounterMode_Down) || \
00369                                    ((MODE) == TIM_CounterMode_CenterAligned1) || \
00370                                    ((MODE) == TIM_CounterMode_CenterAligned2) || \
00371                                    ((MODE) == TIM_CounterMode_CenterAligned3))
00372 /**
00373   * @}
00374   */ 
00375 
00376 /** @defgroup TIM_Output_Compare_Polarity 
00377   * @{
00378   */
00379 
00380 #define TIM_OCPolarity_High                ((uint16_t)0x0000)
00381 #define TIM_OCPolarity_Low                 ((uint16_t)0x0002)
00382 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
00383                                       ((POLARITY) == TIM_OCPolarity_Low))
00384 /**
00385   * @}
00386   */
00387 
00388 /** @defgroup TIM_Output_Compare_N_Polarity 
00389   * @{
00390   */
00391   
00392 #define TIM_OCNPolarity_High               ((uint16_t)0x0000)
00393 #define TIM_OCNPolarity_Low                ((uint16_t)0x0008)
00394 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
00395                                        ((POLARITY) == TIM_OCNPolarity_Low))
00396 /**
00397   * @}
00398   */
00399 
00400 /** @defgroup TIM_Output_Compare_state 
00401   * @{
00402   */
00403 
00404 #define TIM_OutputState_Disable            ((uint16_t)0x0000)
00405 #define TIM_OutputState_Enable             ((uint16_t)0x0001)
00406 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
00407                                     ((STATE) == TIM_OutputState_Enable))
00408 /**
00409   * @}
00410   */ 
00411 
00412 /** @defgroup TIM_Output_Compare_N_state 
00413   * @{
00414   */
00415 
00416 #define TIM_OutputNState_Disable           ((uint16_t)0x0000)
00417 #define TIM_OutputNState_Enable            ((uint16_t)0x0004)
00418 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
00419                                      ((STATE) == TIM_OutputNState_Enable))
00420 /**
00421   * @}
00422   */ 
00423 
00424 /** @defgroup TIM_Capture_Compare_state 
00425   * @{
00426   */
00427 
00428 #define TIM_CCx_Enable                      ((uint16_t)0x0001)
00429 #define TIM_CCx_Disable                     ((uint16_t)0x0000)
00430 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
00431                          ((CCX) == TIM_CCx_Disable))
00432 /**
00433   * @}
00434   */ 
00435 
00436 /** @defgroup TIM_Capture_Compare_N_state 
00437   * @{
00438   */
00439 
00440 #define TIM_CCxN_Enable                     ((uint16_t)0x0004)
00441 #define TIM_CCxN_Disable                    ((uint16_t)0x0000)
00442 #define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
00443                            ((CCXN) == TIM_CCxN_Disable))
00444 /**
00445   * @}
00446   */ 
00447 
00448 /** @defgroup Break_Input_enable_disable 
00449   * @{
00450   */
00451 
00452 #define TIM_Break_Enable                   ((uint16_t)0x1000)
00453 #define TIM_Break_Disable                  ((uint16_t)0x0000)
00454 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
00455                                    ((STATE) == TIM_Break_Disable))
00456 /**
00457   * @}
00458   */ 
00459 
00460 /** @defgroup Break_Polarity 
00461   * @{
00462   */
00463 
00464 #define TIM_BreakPolarity_Low              ((uint16_t)0x0000)
00465 #define TIM_BreakPolarity_High             ((uint16_t)0x2000)
00466 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
00467                                          ((POLARITY) == TIM_BreakPolarity_High))
00468 /**
00469   * @}
00470   */ 
00471 
00472 /** @defgroup TIM_AOE_Bit_Set_Reset 
00473   * @{
00474   */
00475 
00476 #define TIM_AutomaticOutput_Enable         ((uint16_t)0x4000)
00477 #define TIM_AutomaticOutput_Disable        ((uint16_t)0x0000)
00478 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
00479                                               ((STATE) == TIM_AutomaticOutput_Disable))
00480 /**
00481   * @}
00482   */ 
00483 
00484 /** @defgroup Lock_level 
00485   * @{
00486   */
00487 
00488 #define TIM_LOCKLevel_OFF                  ((uint16_t)0x0000)
00489 #define TIM_LOCKLevel_1                    ((uint16_t)0x0100)
00490 #define TIM_LOCKLevel_2                    ((uint16_t)0x0200)
00491 #define TIM_LOCKLevel_3                    ((uint16_t)0x0300)
00492 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
00493                                   ((LEVEL) == TIM_LOCKLevel_1) || \
00494                                   ((LEVEL) == TIM_LOCKLevel_2) || \
00495                                   ((LEVEL) == TIM_LOCKLevel_3))
00496 /**
00497   * @}
00498   */ 
00499 
00500 /** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state 
00501   * @{
00502   */
00503 
00504 #define TIM_OSSIState_Enable               ((uint16_t)0x0400)
00505 #define TIM_OSSIState_Disable              ((uint16_t)0x0000)
00506 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
00507                                   ((STATE) == TIM_OSSIState_Disable))
00508 /**
00509   * @}
00510   */
00511 
00512 /** @defgroup OSSR_Off_State_Selection_for_Run_mode_state 
00513   * @{
00514   */
00515 
00516 #define TIM_OSSRState_Enable               ((uint16_t)0x0800)
00517 #define TIM_OSSRState_Disable              ((uint16_t)0x0000)
00518 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
00519                                   ((STATE) == TIM_OSSRState_Disable))
00520 /**
00521   * @}
00522   */ 
00523 
00524 /** @defgroup TIM_Output_Compare_Idle_State 
00525   * @{
00526   */
00527 
00528 #define TIM_OCIdleState_Set                ((uint16_t)0x0100)
00529 #define TIM_OCIdleState_Reset              ((uint16_t)0x0000)
00530 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
00531                                     ((STATE) == TIM_OCIdleState_Reset))
00532 /**
00533   * @}
00534   */ 
00535 
00536 /** @defgroup TIM_Output_Compare_N_Idle_State 
00537   * @{
00538   */
00539 
00540 #define TIM_OCNIdleState_Set               ((uint16_t)0x0200)
00541 #define TIM_OCNIdleState_Reset             ((uint16_t)0x0000)
00542 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
00543                                      ((STATE) == TIM_OCNIdleState_Reset))
00544 /**
00545   * @}
00546   */ 
00547 
00548 /** @defgroup TIM_Input_Capture_Polarity 
00549   * @{
00550   */
00551 
00552 #define  TIM_ICPolarity_Rising             ((uint16_t)0x0000)
00553 #define  TIM_ICPolarity_Falling            ((uint16_t)0x0002)
00554 #define  TIM_ICPolarity_BothEdge           ((uint16_t)0x000A)
00555 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
00556                                       ((POLARITY) == TIM_ICPolarity_Falling))
00557 #define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
00558                                            ((POLARITY) == TIM_ICPolarity_Falling)|| \
00559                                            ((POLARITY) == TIM_ICPolarity_BothEdge))                                      
00560 /**
00561   * @}
00562   */ 
00563 
00564 /** @defgroup TIM_Input_Capture_Selection 
00565   * @{
00566   */
00567 
00568 #define TIM_ICSelection_DirectTI           ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be 
00569                                                                    connected to IC1, IC2, IC3 or IC4, respectively */
00570 #define TIM_ICSelection_IndirectTI         ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
00571                                                                    connected to IC2, IC1, IC4 or IC3, respectively. */
00572 #define TIM_ICSelection_TRC                ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
00573 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
00574                                         ((SELECTION) == TIM_ICSelection_IndirectTI) || \
00575                                         ((SELECTION) == TIM_ICSelection_TRC))
00576 /**
00577   * @}
00578   */ 
00579 
00580 /** @defgroup TIM_Input_Capture_Prescaler 
00581   * @{
00582   */
00583 
00584 #define TIM_ICPSC_DIV1                     ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
00585 #define TIM_ICPSC_DIV2                     ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
00586 #define TIM_ICPSC_DIV4                     ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
00587 #define TIM_ICPSC_DIV8                     ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
00588 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
00589                                         ((PRESCALER) == TIM_ICPSC_DIV2) || \
00590                                         ((PRESCALER) == TIM_ICPSC_DIV4) || \
00591                                         ((PRESCALER) == TIM_ICPSC_DIV8))
00592 /**
00593   * @}
00594   */ 
00595 
00596 /** @defgroup TIM_interrupt_sources 
00597   * @{
00598   */
00599 
00600 #define TIM_IT_Update                      ((uint16_t)0x0001)
00601 #define TIM_IT_CC1                         ((uint16_t)0x0002)
00602 #define TIM_IT_CC2                         ((uint16_t)0x0004)
00603 #define TIM_IT_CC3                         ((uint16_t)0x0008)
00604 #define TIM_IT_CC4                         ((uint16_t)0x0010)
00605 #define TIM_IT_COM                         ((uint16_t)0x0020)
00606 #define TIM_IT_Trigger                     ((uint16_t)0x0040)
00607 #define TIM_IT_Break                       ((uint16_t)0x0080)
00608 #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
00609 
00610 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
00611                            ((IT) == TIM_IT_CC1) || \
00612                            ((IT) == TIM_IT_CC2) || \
00613                            ((IT) == TIM_IT_CC3) || \
00614                            ((IT) == TIM_IT_CC4) || \
00615                            ((IT) == TIM_IT_COM) || \
00616                            ((IT) == TIM_IT_Trigger) || \
00617                            ((IT) == TIM_IT_Break))
00618 /**
00619   * @}
00620   */ 
00621 
00622 /** @defgroup TIM_DMA_Base_address 
00623   * @{
00624   */
00625 
00626 #define TIM_DMABase_CR1                    ((uint16_t)0x0000)
00627 #define TIM_DMABase_CR2                    ((uint16_t)0x0001)
00628 #define TIM_DMABase_SMCR                   ((uint16_t)0x0002)
00629 #define TIM_DMABase_DIER                   ((uint16_t)0x0003)
00630 #define TIM_DMABase_SR                     ((uint16_t)0x0004)
00631 #define TIM_DMABase_EGR                    ((uint16_t)0x0005)
00632 #define TIM_DMABase_CCMR1                  ((uint16_t)0x0006)
00633 #define TIM_DMABase_CCMR2                  ((uint16_t)0x0007)
00634 #define TIM_DMABase_CCER                   ((uint16_t)0x0008)
00635 #define TIM_DMABase_CNT                    ((uint16_t)0x0009)
00636 #define TIM_DMABase_PSC                    ((uint16_t)0x000A)
00637 #define TIM_DMABase_ARR                    ((uint16_t)0x000B)
00638 #define TIM_DMABase_RCR                    ((uint16_t)0x000C)
00639 #define TIM_DMABase_CCR1                   ((uint16_t)0x000D)
00640 #define TIM_DMABase_CCR2                   ((uint16_t)0x000E)
00641 #define TIM_DMABase_CCR3                   ((uint16_t)0x000F)
00642 #define TIM_DMABase_CCR4                   ((uint16_t)0x0010)
00643 #define TIM_DMABase_BDTR                   ((uint16_t)0x0011)
00644 #define TIM_DMABase_DCR                    ((uint16_t)0x0012)
00645 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
00646                                ((BASE) == TIM_DMABase_CR2) || \
00647                                ((BASE) == TIM_DMABase_SMCR) || \
00648                                ((BASE) == TIM_DMABase_DIER) || \
00649                                ((BASE) == TIM_DMABase_SR) || \
00650                                ((BASE) == TIM_DMABase_EGR) || \
00651                                ((BASE) == TIM_DMABase_CCMR1) || \
00652                                ((BASE) == TIM_DMABase_CCMR2) || \
00653                                ((BASE) == TIM_DMABase_CCER) || \
00654                                ((BASE) == TIM_DMABase_CNT) || \
00655                                ((BASE) == TIM_DMABase_PSC) || \
00656                                ((BASE) == TIM_DMABase_ARR) || \
00657                                ((BASE) == TIM_DMABase_RCR) || \
00658                                ((BASE) == TIM_DMABase_CCR1) || \
00659                                ((BASE) == TIM_DMABase_CCR2) || \
00660                                ((BASE) == TIM_DMABase_CCR3) || \
00661                                ((BASE) == TIM_DMABase_CCR4) || \
00662                                ((BASE) == TIM_DMABase_BDTR) || \
00663                                ((BASE) == TIM_DMABase_DCR))
00664 /**
00665   * @}
00666   */ 
00667 
00668 /** @defgroup TIM_DMA_Burst_Length 
00669   * @{
00670   */
00671 
00672 #define TIM_DMABurstLength_1Byte           ((uint16_t)0x0000)
00673 #define TIM_DMABurstLength_2Bytes          ((uint16_t)0x0100)
00674 #define TIM_DMABurstLength_3Bytes          ((uint16_t)0x0200)
00675 #define TIM_DMABurstLength_4Bytes          ((uint16_t)0x0300)
00676 #define TIM_DMABurstLength_5Bytes          ((uint16_t)0x0400)
00677 #define TIM_DMABurstLength_6Bytes          ((uint16_t)0x0500)
00678 #define TIM_DMABurstLength_7Bytes          ((uint16_t)0x0600)
00679 #define TIM_DMABurstLength_8Bytes          ((uint16_t)0x0700)
00680 #define TIM_DMABurstLength_9Bytes          ((uint16_t)0x0800)
00681 #define TIM_DMABurstLength_10Bytes         ((uint16_t)0x0900)
00682 #define TIM_DMABurstLength_11Bytes         ((uint16_t)0x0A00)
00683 #define TIM_DMABurstLength_12Bytes         ((uint16_t)0x0B00)
00684 #define TIM_DMABurstLength_13Bytes         ((uint16_t)0x0C00)
00685 #define TIM_DMABurstLength_14Bytes         ((uint16_t)0x0D00)
00686 #define TIM_DMABurstLength_15Bytes         ((uint16_t)0x0E00)
00687 #define TIM_DMABurstLength_16Bytes         ((uint16_t)0x0F00)
00688 #define TIM_DMABurstLength_17Bytes         ((uint16_t)0x1000)
00689 #define TIM_DMABurstLength_18Bytes         ((uint16_t)0x1100)
00690 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \
00691                                    ((LENGTH) == TIM_DMABurstLength_2Bytes) || \
00692                                    ((LENGTH) == TIM_DMABurstLength_3Bytes) || \
00693                                    ((LENGTH) == TIM_DMABurstLength_4Bytes) || \
00694                                    ((LENGTH) == TIM_DMABurstLength_5Bytes) || \
00695                                    ((LENGTH) == TIM_DMABurstLength_6Bytes) || \
00696                                    ((LENGTH) == TIM_DMABurstLength_7Bytes) || \
00697                                    ((LENGTH) == TIM_DMABurstLength_8Bytes) || \
00698                                    ((LENGTH) == TIM_DMABurstLength_9Bytes) || \
00699                                    ((LENGTH) == TIM_DMABurstLength_10Bytes) || \
00700                                    ((LENGTH) == TIM_DMABurstLength_11Bytes) || \
00701                                    ((LENGTH) == TIM_DMABurstLength_12Bytes) || \
00702                                    ((LENGTH) == TIM_DMABurstLength_13Bytes) || \
00703                                    ((LENGTH) == TIM_DMABurstLength_14Bytes) || \
00704                                    ((LENGTH) == TIM_DMABurstLength_15Bytes) || \
00705                                    ((LENGTH) == TIM_DMABurstLength_16Bytes) || \
00706                                    ((LENGTH) == TIM_DMABurstLength_17Bytes) || \
00707                                    ((LENGTH) == TIM_DMABurstLength_18Bytes))
00708 /**
00709   * @}
00710   */ 
00711 
00712 /** @defgroup TIM_DMA_sources 
00713   * @{
00714   */
00715 
00716 #define TIM_DMA_Update                     ((uint16_t)0x0100)
00717 #define TIM_DMA_CC1                        ((uint16_t)0x0200)
00718 #define TIM_DMA_CC2                        ((uint16_t)0x0400)
00719 #define TIM_DMA_CC3                        ((uint16_t)0x0800)
00720 #define TIM_DMA_CC4                        ((uint16_t)0x1000)
00721 #define TIM_DMA_COM                        ((uint16_t)0x2000)
00722 #define TIM_DMA_Trigger                    ((uint16_t)0x4000)
00723 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
00724 
00725 /**
00726   * @}
00727   */ 
00728 
00729 /** @defgroup TIM_External_Trigger_Prescaler 
00730   * @{
00731   */
00732 
00733 #define TIM_ExtTRGPSC_OFF                  ((uint16_t)0x0000)
00734 #define TIM_ExtTRGPSC_DIV2                 ((uint16_t)0x1000)
00735 #define TIM_ExtTRGPSC_DIV4                 ((uint16_t)0x2000)
00736 #define TIM_ExtTRGPSC_DIV8                 ((uint16_t)0x3000)
00737 #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
00738                                          ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
00739                                          ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
00740                                          ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
00741 /**
00742   * @}
00743   */ 
00744 
00745 /** @defgroup TIM_Internal_Trigger_Selection 
00746   * @{
00747   */
00748 
00749 #define TIM_TS_ITR0                        ((uint16_t)0x0000)
00750 #define TIM_TS_ITR1                        ((uint16_t)0x0010)
00751 #define TIM_TS_ITR2                        ((uint16_t)0x0020)
00752 #define TIM_TS_ITR3                        ((uint16_t)0x0030)
00753 #define TIM_TS_TI1F_ED                     ((uint16_t)0x0040)
00754 #define TIM_TS_TI1FP1                      ((uint16_t)0x0050)
00755 #define TIM_TS_TI2FP2                      ((uint16_t)0x0060)
00756 #define TIM_TS_ETRF                        ((uint16_t)0x0070)
00757 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
00758                                              ((SELECTION) == TIM_TS_ITR1) || \
00759                                              ((SELECTION) == TIM_TS_ITR2) || \
00760                                              ((SELECTION) == TIM_TS_ITR3) || \
00761                                              ((SELECTION) == TIM_TS_TI1F_ED) || \
00762                                              ((SELECTION) == TIM_TS_TI1FP1) || \
00763                                              ((SELECTION) == TIM_TS_TI2FP2) || \
00764                                              ((SELECTION) == TIM_TS_ETRF))
00765 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
00766                                                       ((SELECTION) == TIM_TS_ITR1) || \
00767                                                       ((SELECTION) == TIM_TS_ITR2) || \
00768                                                       ((SELECTION) == TIM_TS_ITR3))
00769 /**
00770   * @}
00771   */ 
00772 
00773 /** @defgroup TIM_TIx_External_Clock_Source 
00774   * @{
00775   */
00776 
00777 #define TIM_TIxExternalCLK1Source_TI1      ((uint16_t)0x0050)
00778 #define TIM_TIxExternalCLK1Source_TI2      ((uint16_t)0x0060)
00779 #define TIM_TIxExternalCLK1Source_TI1ED    ((uint16_t)0x0040)
00780 #define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \
00781                                       ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \
00782                                       ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))
00783 /**
00784   * @}
00785   */ 
00786 
00787 /** @defgroup TIM_External_Trigger_Polarity 
00788   * @{
00789   */ 
00790 #define TIM_ExtTRGPolarity_Inverted        ((uint16_t)0x8000)
00791 #define TIM_ExtTRGPolarity_NonInverted     ((uint16_t)0x0000)
00792 #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
00793                                        ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
00794 /**
00795   * @}
00796   */
00797 
00798 /** @defgroup TIM_Prescaler_Reload_Mode 
00799   * @{
00800   */
00801 
00802 #define TIM_PSCReloadMode_Update           ((uint16_t)0x0000)
00803 #define TIM_PSCReloadMode_Immediate        ((uint16_t)0x0001)
00804 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
00805                                          ((RELOAD) == TIM_PSCReloadMode_Immediate))
00806 /**
00807   * @}
00808   */ 
00809 
00810 /** @defgroup TIM_Forced_Action 
00811   * @{
00812   */
00813 
00814 #define TIM_ForcedAction_Active            ((uint16_t)0x0050)
00815 #define TIM_ForcedAction_InActive          ((uint16_t)0x0040)
00816 #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
00817                                       ((ACTION) == TIM_ForcedAction_InActive))
00818 /**
00819   * @}
00820   */ 
00821 
00822 /** @defgroup TIM_Encoder_Mode 
00823   * @{
00824   */
00825 
00826 #define TIM_EncoderMode_TI1                ((uint16_t)0x0001)
00827 #define TIM_EncoderMode_TI2                ((uint16_t)0x0002)
00828 #define TIM_EncoderMode_TI12               ((uint16_t)0x0003)
00829 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
00830                                    ((MODE) == TIM_EncoderMode_TI2) || \
00831                                    ((MODE) == TIM_EncoderMode_TI12))
00832 /**
00833   * @}
00834   */ 
00835 
00836 
00837 /** @defgroup TIM_Event_Source 
00838   * @{
00839   */
00840 
00841 #define TIM_EventSource_Update             ((uint16_t)0x0001)
00842 #define TIM_EventSource_CC1                ((uint16_t)0x0002)
00843 #define TIM_EventSource_CC2                ((uint16_t)0x0004)
00844 #define TIM_EventSource_CC3                ((uint16_t)0x0008)
00845 #define TIM_EventSource_CC4                ((uint16_t)0x0010)
00846 #define TIM_EventSource_COM                ((uint16_t)0x0020)
00847 #define TIM_EventSource_Trigger            ((uint16_t)0x0040)
00848 #define TIM_EventSource_Break              ((uint16_t)0x0080)
00849 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
00850 
00851 /**
00852   * @}
00853   */ 
00854 
00855 /** @defgroup TIM_Update_Source 
00856   * @{
00857   */
00858 
00859 #define TIM_UpdateSource_Global            ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
00860                                                                    or the setting of UG bit, or an update generation
00861                                                                    through the slave mode controller. */
00862 #define TIM_UpdateSource_Regular           ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
00863 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
00864                                       ((SOURCE) == TIM_UpdateSource_Regular))
00865 /**
00866   * @}
00867   */ 
00868 
00869 /** @defgroup TIM_Ouput_Compare_Preload_State 
00870   * @{
00871   */
00872 
00873 #define TIM_OCPreload_Enable               ((uint16_t)0x0008)
00874 #define TIM_OCPreload_Disable              ((uint16_t)0x0000)
00875 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
00876                                        ((STATE) == TIM_OCPreload_Disable))
00877 /**
00878   * @}
00879   */ 
00880 
00881 /** @defgroup TIM_Ouput_Compare_Fast_State 
00882   * @{
00883   */
00884 
00885 #define TIM_OCFast_Enable                  ((uint16_t)0x0004)
00886 #define TIM_OCFast_Disable                 ((uint16_t)0x0000)
00887 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
00888                                     ((STATE) == TIM_OCFast_Disable))
00889                                      
00890 /**
00891   * @}
00892   */ 
00893 
00894 /** @defgroup TIM_Ouput_Compare_Clear_State 
00895   * @{
00896   */
00897 
00898 #define TIM_OCClear_Enable                 ((uint16_t)0x0080)
00899 #define TIM_OCClear_Disable                ((uint16_t)0x0000)
00900 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
00901                                      ((STATE) == TIM_OCClear_Disable))
00902 /**
00903   * @}
00904   */ 
00905 
00906 /** @defgroup TIM_Trigger_Output_Source 
00907   * @{
00908   */
00909 
00910 #define TIM_TRGOSource_Reset               ((uint16_t)0x0000)
00911 #define TIM_TRGOSource_Enable              ((uint16_t)0x0010)
00912 #define TIM_TRGOSource_Update              ((uint16_t)0x0020)
00913 #define TIM_TRGOSource_OC1                 ((uint16_t)0x0030)
00914 #define TIM_TRGOSource_OC1Ref              ((uint16_t)0x0040)
00915 #define TIM_TRGOSource_OC2Ref              ((uint16_t)0x0050)
00916 #define TIM_TRGOSource_OC3Ref              ((uint16_t)0x0060)
00917 #define TIM_TRGOSource_OC4Ref              ((uint16_t)0x0070)
00918 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
00919                                     ((SOURCE) == TIM_TRGOSource_Enable) || \
00920                                     ((SOURCE) == TIM_TRGOSource_Update) || \
00921                                     ((SOURCE) == TIM_TRGOSource_OC1) || \
00922                                     ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
00923                                     ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
00924                                     ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
00925                                     ((SOURCE) == TIM_TRGOSource_OC4Ref))
00926 /**
00927   * @}
00928   */ 
00929 
00930 /** @defgroup TIM_Slave_Mode 
00931   * @{
00932   */
00933 
00934 #define TIM_SlaveMode_Reset                ((uint16_t)0x0004)
00935 #define TIM_SlaveMode_Gated                ((uint16_t)0x0005)
00936 #define TIM_SlaveMode_Trigger              ((uint16_t)0x0006)
00937 #define TIM_SlaveMode_External1            ((uint16_t)0x0007)
00938 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
00939                                  ((MODE) == TIM_SlaveMode_Gated) || \
00940                                  ((MODE) == TIM_SlaveMode_Trigger) || \
00941                                  ((MODE) == TIM_SlaveMode_External1))
00942 /**
00943   * @}
00944   */ 
00945 
00946 /** @defgroup TIM_Master_Slave_Mode 
00947   * @{
00948   */
00949 
00950 #define TIM_MasterSlaveMode_Enable         ((uint16_t)0x0080)
00951 #define TIM_MasterSlaveMode_Disable        ((uint16_t)0x0000)
00952 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
00953                                  ((STATE) == TIM_MasterSlaveMode_Disable))
00954 /**
00955   * @}
00956   */ 
00957 
00958 /** @defgroup TIM_Flags 
00959   * @{
00960   */
00961 
00962 #define TIM_FLAG_Update                    ((uint16_t)0x0001)
00963 #define TIM_FLAG_CC1                       ((uint16_t)0x0002)
00964 #define TIM_FLAG_CC2                       ((uint16_t)0x0004)
00965 #define TIM_FLAG_CC3                       ((uint16_t)0x0008)
00966 #define TIM_FLAG_CC4                       ((uint16_t)0x0010)
00967 #define TIM_FLAG_COM                       ((uint16_t)0x0020)
00968 #define TIM_FLAG_Trigger                   ((uint16_t)0x0040)
00969 #define TIM_FLAG_Break                     ((uint16_t)0x0080)
00970 #define TIM_FLAG_CC1OF                     ((uint16_t)0x0200)
00971 #define TIM_FLAG_CC2OF                     ((uint16_t)0x0400)
00972 #define TIM_FLAG_CC3OF                     ((uint16_t)0x0800)
00973 #define TIM_FLAG_CC4OF                     ((uint16_t)0x1000)
00974 #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
00975                                ((FLAG) == TIM_FLAG_CC1) || \
00976                                ((FLAG) == TIM_FLAG_CC2) || \
00977                                ((FLAG) == TIM_FLAG_CC3) || \
00978                                ((FLAG) == TIM_FLAG_CC4) || \
00979                                ((FLAG) == TIM_FLAG_COM) || \
00980                                ((FLAG) == TIM_FLAG_Trigger) || \
00981                                ((FLAG) == TIM_FLAG_Break) || \
00982                                ((FLAG) == TIM_FLAG_CC1OF) || \
00983                                ((FLAG) == TIM_FLAG_CC2OF) || \
00984                                ((FLAG) == TIM_FLAG_CC3OF) || \
00985                                ((FLAG) == TIM_FLAG_CC4OF))
00986                                
00987                                
00988 #define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
00989 /**
00990   * @}
00991   */ 
00992 
00993 /** @defgroup TIM_Input_Capture_Filer_Value 
00994   * @{
00995   */
00996 
00997 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 
00998 /**
00999   * @}
01000   */ 
01001 
01002 /** @defgroup TIM_External_Trigger_Filter 
01003   * @{
01004   */
01005 
01006 #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
01007 /**
01008   * @}
01009   */ 
01010 
01011 /**
01012   * @}
01013   */
01014 
01015 /** @defgroup TIM_Exported_Macros
01016   * @{
01017   */
01018 
01019 /**
01020   * @}
01021   */ 
01022 
01023 /** @defgroup TIM_Exported_Functions
01024   * @{
01025   */
01026 
01027 void TIM_DeInit(TIM_TypeDef* TIMx);
01028 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
01029 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
01030 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
01031 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
01032 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
01033 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
01034 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
01035 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
01036 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
01037 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
01038 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
01039 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
01040 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
01041 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
01042 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
01043 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
01044 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
01045 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
01046 void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
01047 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
01048 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
01049                                 uint16_t TIM_ICPolarity, uint16_t ICFilter);
01050 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
01051                              uint16_t ExtTRGFilter);
01052 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
01053                              uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
01054 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
01055                    uint16_t ExtTRGFilter);
01056 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
01057 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
01058 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
01059 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
01060                                 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
01061 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
01062 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
01063 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
01064 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
01065 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
01066 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
01067 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
01068 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
01069 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
01070 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
01071 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
01072 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
01073 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
01074 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
01075 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
01076 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
01077 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
01078 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
01079 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
01080 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
01081 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
01082 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
01083 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
01084 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
01085 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
01086 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
01087 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
01088 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
01089 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
01090 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
01091 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
01092 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
01093 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
01094 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
01095 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
01096 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
01097 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
01098 void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);
01099 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);
01100 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);
01101 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);
01102 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);
01103 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);
01104 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
01105 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
01106 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
01107 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
01108 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
01109 uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);
01110 uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);
01111 uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);
01112 uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);
01113 uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);
01114 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
01115 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
01116 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
01117 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
01118 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
01119 
01120 #ifdef __cplusplus
01121 }
01122 #endif
01123 
01124 #endif /*__STM32F10x_TIM_H */
01125 /**
01126   * @}
01127   */ 
01128 
01129 /**
01130   * @}
01131   */ 
01132 
01133 /**
01134   * @}
01135   */
01136 
01137 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
STM32F10x Standard Peripherals Library: Footer

 

 

 

      For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit  www.st.com/STM32