stm32f10x_tim.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_tim.c
00004   * @author  MCD Application Team
00005   * @version V3.4.0
00006   * @date    10/15/2010
00007   * @brief   This file provides all the TIM firmware functions.
00008   ******************************************************************************
00009   * @copy
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
00019   */ 
00020 
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32f10x_tim.h"
00023 #include "stm32f10x_rcc.h"
00024 
00025 /** @addtogroup STM32F10x_StdPeriph_Driver
00026   * @{
00027   */
00028 
00029 /** @defgroup TIM 
00030   * @brief TIM driver modules
00031   * @{
00032   */
00033 
00034 /** @defgroup TIM_Private_TypesDefinitions
00035   * @{
00036   */
00037 
00038 /**
00039   * @}
00040   */
00041 
00042 /** @defgroup TIM_Private_Defines
00043   * @{
00044   */
00045 
00046 /* ---------------------- TIM registers bit mask ------------------------ */
00047 #define SMCR_ETR_Mask               ((uint16_t)0x00FF) 
00048 #define CCMR_Offset                 ((uint16_t)0x0018)
00049 #define CCER_CCE_Set                ((uint16_t)0x0001)  
00050 #define CCER_CCNE_Set               ((uint16_t)0x0004) 
00051 
00052 /**
00053   * @}
00054   */
00055 
00056 /** @defgroup TIM_Private_Macros
00057   * @{
00058   */
00059 
00060 /**
00061   * @}
00062   */
00063 
00064 /** @defgroup TIM_Private_Variables
00065   * @{
00066   */
00067 
00068 /**
00069   * @}
00070   */
00071 
00072 /** @defgroup TIM_Private_FunctionPrototypes
00073   * @{
00074   */
00075 
00076 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
00077                        uint16_t TIM_ICFilter);
00078 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
00079                        uint16_t TIM_ICFilter);
00080 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
00081                        uint16_t TIM_ICFilter);
00082 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
00083                        uint16_t TIM_ICFilter);
00084 /**
00085   * @}
00086   */
00087 
00088 /** @defgroup TIM_Private_Macros
00089   * @{
00090   */
00091 
00092 /**
00093   * @}
00094   */
00095 
00096 /** @defgroup TIM_Private_Variables
00097   * @{
00098   */
00099 
00100 /**
00101   * @}
00102   */
00103 
00104 /** @defgroup TIM_Private_FunctionPrototypes
00105   * @{
00106   */
00107 
00108 /**
00109   * @}
00110   */
00111 
00112 /** @defgroup TIM_Private_Functions
00113   * @{
00114   */
00115 
00116 /**
00117   * @brief  Deinitializes the TIMx peripheral registers to their default reset values.
00118   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
00119   * @retval None
00120   */
00121 void TIM_DeInit(TIM_TypeDef* TIMx)
00122 {
00123   /* Check the parameters */
00124   assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
00125  
00126   if (TIMx == TIM1)
00127   {
00128     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
00129     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);  
00130   }     
00131   else if (TIMx == TIM2)
00132   {
00133     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
00134     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
00135   }
00136   else if (TIMx == TIM3)
00137   {
00138     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
00139     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
00140   }
00141   else if (TIMx == TIM4)
00142   {
00143     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
00144     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
00145   } 
00146   else if (TIMx == TIM5)
00147   {
00148     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
00149     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
00150   } 
00151   else if (TIMx == TIM6)
00152   {
00153     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
00154     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
00155   } 
00156   else if (TIMx == TIM7)
00157   {
00158     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
00159     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
00160   } 
00161   else if (TIMx == TIM8)
00162   {
00163     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
00164     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
00165   }
00166   else if (TIMx == TIM9)
00167   {      
00168     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
00169     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);  
00170    }  
00171   else if (TIMx == TIM10)
00172   {      
00173     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
00174     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);  
00175   }  
00176   else if (TIMx == TIM11) 
00177   {     
00178     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
00179     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);  
00180   }  
00181   else if (TIMx == TIM12)
00182   {      
00183     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
00184     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);  
00185   }  
00186   else if (TIMx == TIM13) 
00187   {       
00188     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
00189     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);  
00190   }
00191   else if (TIMx == TIM14) 
00192   {       
00193     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
00194     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);  
00195   }        
00196   else if (TIMx == TIM15)
00197   {
00198     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
00199     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
00200   } 
00201   else if (TIMx == TIM16)
00202   {
00203     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
00204     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
00205   } 
00206   else
00207   {
00208     if (TIMx == TIM17)
00209     {
00210       RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
00211       RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
00212     }  
00213   }
00214 }
00215 
00216 /**
00217   * @brief  Initializes the TIMx Time Base Unit peripheral according to 
00218   *   the specified parameters in the TIM_TimeBaseInitStruct.
00219   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
00220   * @param  TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
00221   *   structure that contains the configuration information for the specified TIM peripheral.
00222   * @retval None
00223   */
00224 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
00225 {
00226   uint16_t tmpcr1 = 0;
00227 
00228   /* Check the parameters */
00229   assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
00230   assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
00231   assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
00232 
00233   tmpcr1 = TIMx->CR1;  
00234 
00235   if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)||
00236      (TIMx == TIM4) || (TIMx == TIM5)) 
00237   {
00238     /* Select the Counter Mode */
00239     tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
00240     tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
00241   }
00242  
00243   if((TIMx != TIM6) && (TIMx != TIM7))
00244   {
00245     /* Set the clock division */
00246     tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
00247     tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
00248   }
00249 
00250   TIMx->CR1 = tmpcr1;
00251 
00252   /* Set the Autoreload value */
00253   TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
00254  
00255   /* Set the Prescaler value */
00256   TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
00257     
00258   if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17))  
00259   {
00260     /* Set the Repetition Counter value */
00261     TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
00262   }
00263 
00264   /* Generate an update event to reload the Prescaler and the Repetition counter
00265      values immediately */
00266   TIMx->EGR = TIM_PSCReloadMode_Immediate;           
00267 }
00268 
00269 /**
00270   * @brief  Initializes the TIMx Channel1 according to the specified
00271   *   parameters in the TIM_OCInitStruct.
00272   * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
00273   * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
00274   *   that contains the configuration information for the specified TIM peripheral.
00275   * @retval None
00276   */
00277 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
00278 {
00279   uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
00280    
00281   /* Check the parameters */
00282   assert_param(IS_TIM_LIST8_PERIPH(TIMx));
00283   assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
00284   assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
00285   assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
00286  /* Disable the Channel 1: Reset the CC1E Bit */
00287   TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
00288   /* Get the TIMx CCER register value */
00289   tmpccer = TIMx->CCER;
00290   /* Get the TIMx CR2 register value */
00291   tmpcr2 =  TIMx->CR2;
00292   
00293   /* Get the TIMx CCMR1 register value */
00294   tmpccmrx = TIMx->CCMR1;
00295     
00296   /* Reset the Output Compare Mode Bits */
00297   tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
00298   tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
00299 
00300   /* Select the Output Compare Mode */
00301   tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
00302   
00303   /* Reset the Output Polarity level */
00304   tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
00305   /* Set the Output Compare Polarity */
00306   tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
00307   
00308   /* Set the Output State */
00309   tmpccer |= TIM_OCInitStruct->TIM_OutputState;
00310     
00311   if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)||
00312      (TIMx == TIM16)|| (TIMx == TIM17))
00313   {
00314     assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
00315     assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
00316     assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
00317     assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
00318     
00319     /* Reset the Output N Polarity level */
00320     tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
00321     /* Set the Output N Polarity */
00322     tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
00323     
00324     /* Reset the Output N State */
00325     tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));    
00326     /* Set the Output N State */
00327     tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
00328     
00329     /* Reset the Ouput Compare and Output Compare N IDLE State */
00330     tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
00331     tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
00332     
00333     /* Set the Output Idle state */
00334     tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
00335     /* Set the Output N Idle state */
00336     tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
00337   }
00338   /* Write to TIMx CR2 */
00339   TIMx->CR2 = tmpcr2;
00340   
00341   /* Write to TIMx CCMR1 */
00342   TIMx->CCMR1 = tmpccmrx;
00343 
00344   /* Set the Capture Compare Register value */
00345   TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; 
00346  
00347   /* Write to TIMx CCER */
00348   TIMx->CCER = tmpccer;
00349 }
00350 
00351 /**
00352   * @brief  Initializes the TIMx Channel2 according to the specified
00353   *   parameters in the TIM_OCInitStruct.
00354   * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select 
00355   *   the TIM peripheral.
00356   * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
00357   *   that contains the configuration information for the specified TIM peripheral.
00358   * @retval None
00359   */
00360 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
00361 {
00362   uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
00363    
00364   /* Check the parameters */
00365   assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 
00366   assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
00367   assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
00368   assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
00369    /* Disable the Channel 2: Reset the CC2E Bit */
00370   TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
00371   
00372   /* Get the TIMx CCER register value */  
00373   tmpccer = TIMx->CCER;
00374   /* Get the TIMx CR2 register value */
00375   tmpcr2 =  TIMx->CR2;
00376   
00377   /* Get the TIMx CCMR1 register value */
00378   tmpccmrx = TIMx->CCMR1;
00379     
00380   /* Reset the Output Compare mode and Capture/Compare selection Bits */
00381   tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
00382   tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));
00383   
00384   /* Select the Output Compare Mode */
00385   tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
00386   
00387   /* Reset the Output Polarity level */
00388   tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
00389   /* Set the Output Compare Polarity */
00390   tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
00391   
00392   /* Set the Output State */
00393   tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
00394     
00395   if((TIMx == TIM1) || (TIMx == TIM8))
00396   {
00397     assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
00398     assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
00399     assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
00400     assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
00401     
00402     /* Reset the Output N Polarity level */
00403     tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));
00404     /* Set the Output N Polarity */
00405     tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
00406     
00407     /* Reset the Output N State */
00408     tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE));    
00409     /* Set the Output N State */
00410     tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
00411     
00412     /* Reset the Ouput Compare and Output Compare N IDLE State */
00413     tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
00414     tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));
00415     
00416     /* Set the Output Idle state */
00417     tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
00418     /* Set the Output N Idle state */
00419     tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
00420   }
00421   /* Write to TIMx CR2 */
00422   TIMx->CR2 = tmpcr2;
00423   
00424   /* Write to TIMx CCMR1 */
00425   TIMx->CCMR1 = tmpccmrx;
00426 
00427   /* Set the Capture Compare Register value */
00428   TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
00429   
00430   /* Write to TIMx CCER */
00431   TIMx->CCER = tmpccer;
00432 }
00433 
00434 /**
00435   * @brief  Initializes the TIMx Channel3 according to the specified
00436   *   parameters in the TIM_OCInitStruct.
00437   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
00438   * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
00439   *   that contains the configuration information for the specified TIM peripheral.
00440   * @retval None
00441   */
00442 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
00443 {
00444   uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
00445    
00446   /* Check the parameters */
00447   assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
00448   assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
00449   assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
00450   assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
00451   /* Disable the Channel 2: Reset the CC2E Bit */
00452   TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
00453   
00454   /* Get the TIMx CCER register value */
00455   tmpccer = TIMx->CCER;
00456   /* Get the TIMx CR2 register value */
00457   tmpcr2 =  TIMx->CR2;
00458   
00459   /* Get the TIMx CCMR2 register value */
00460   tmpccmrx = TIMx->CCMR2;
00461     
00462   /* Reset the Output Compare mode and Capture/Compare selection Bits */
00463   tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
00464   tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));  
00465   /* Select the Output Compare Mode */
00466   tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
00467   
00468   /* Reset the Output Polarity level */
00469   tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
00470   /* Set the Output Compare Polarity */
00471   tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
00472   
00473   /* Set the Output State */
00474   tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
00475     
00476   if((TIMx == TIM1) || (TIMx == TIM8))
00477   {
00478     assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
00479     assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
00480     assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
00481     assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
00482     
00483     /* Reset the Output N Polarity level */
00484     tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
00485     /* Set the Output N Polarity */
00486     tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
00487     /* Reset the Output N State */
00488     tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));
00489     
00490     /* Set the Output N State */
00491     tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
00492     /* Reset the Ouput Compare and Output Compare N IDLE State */
00493     tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
00494     tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
00495     /* Set the Output Idle state */
00496     tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
00497     /* Set the Output N Idle state */
00498     tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
00499   }
00500   /* Write to TIMx CR2 */
00501   TIMx->CR2 = tmpcr2;
00502   
00503   /* Write to TIMx CCMR2 */
00504   TIMx->CCMR2 = tmpccmrx;
00505 
00506   /* Set the Capture Compare Register value */
00507   TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
00508   
00509   /* Write to TIMx CCER */
00510   TIMx->CCER = tmpccer;
00511 }
00512 
00513 /**
00514   * @brief  Initializes the TIMx Channel4 according to the specified
00515   *   parameters in the TIM_OCInitStruct.
00516   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
00517   * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
00518   *   that contains the configuration information for the specified TIM peripheral.
00519   * @retval None
00520   */
00521 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
00522 {
00523   uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
00524    
00525   /* Check the parameters */
00526   assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
00527   assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
00528   assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
00529   assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
00530   /* Disable the Channel 2: Reset the CC4E Bit */
00531   TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
00532   
00533   /* Get the TIMx CCER register value */
00534   tmpccer = TIMx->CCER;
00535   /* Get the TIMx CR2 register value */
00536   tmpcr2 =  TIMx->CR2;
00537   
00538   /* Get the TIMx CCMR2 register value */
00539   tmpccmrx = TIMx->CCMR2;
00540     
00541   /* Reset the Output Compare mode and Capture/Compare selection Bits */
00542   tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
00543   tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));
00544   
00545   /* Select the Output Compare Mode */
00546   tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
00547   
00548   /* Reset the Output Polarity level */
00549   tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
00550   /* Set the Output Compare Polarity */
00551   tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
00552   
00553   /* Set the Output State */
00554   tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
00555     
00556   if((TIMx == TIM1) || (TIMx == TIM8))
00557   {
00558     assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
00559     /* Reset the Ouput Compare IDLE State */
00560     tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
00561     /* Set the Output Idle state */
00562     tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
00563   }
00564   /* Write to TIMx CR2 */
00565   TIMx->CR2 = tmpcr2;
00566   
00567   /* Write to TIMx CCMR2 */  
00568   TIMx->CCMR2 = tmpccmrx;
00569 
00570   /* Set the Capture Compare Register value */
00571   TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
00572   
00573   /* Write to TIMx CCER */
00574   TIMx->CCER = tmpccer;
00575 }
00576 
00577 /**
00578   * @brief  Initializes the TIM peripheral according to the specified
00579   *   parameters in the TIM_ICInitStruct.
00580   * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
00581   * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
00582   *   that contains the configuration information for the specified TIM peripheral.
00583   * @retval None
00584   */
00585 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
00586 {
00587   /* Check the parameters */
00588   assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));  
00589   assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
00590   assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
00591   assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
00592   
00593   if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
00594      (TIMx == TIM4) ||(TIMx == TIM5))
00595   {
00596     assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
00597   }
00598   else
00599   {
00600     assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity));
00601   }
00602   if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
00603   {
00604     assert_param(IS_TIM_LIST8_PERIPH(TIMx));
00605     /* TI1 Configuration */
00606     TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
00607                TIM_ICInitStruct->TIM_ICSelection,
00608                TIM_ICInitStruct->TIM_ICFilter);
00609     /* Set the Input Capture Prescaler value */
00610     TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
00611   }
00612   else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
00613   {
00614     assert_param(IS_TIM_LIST6_PERIPH(TIMx));
00615     /* TI2 Configuration */
00616     TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
00617                TIM_ICInitStruct->TIM_ICSelection,
00618                TIM_ICInitStruct->TIM_ICFilter);
00619     /* Set the Input Capture Prescaler value */
00620     TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
00621   }
00622   else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
00623   {
00624     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
00625     /* TI3 Configuration */
00626     TI3_Config(TIMx,  TIM_ICInitStruct->TIM_ICPolarity,
00627                TIM_ICInitStruct->TIM_ICSelection,
00628                TIM_ICInitStruct->TIM_ICFilter);
00629     /* Set the Input Capture Prescaler value */
00630     TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
00631   }
00632   else
00633   {
00634     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
00635     /* TI4 Configuration */
00636     TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
00637                TIM_ICInitStruct->TIM_ICSelection,
00638                TIM_ICInitStruct->TIM_ICFilter);
00639     /* Set the Input Capture Prescaler value */
00640     TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
00641   }
00642 }
00643 
00644 /**
00645   * @brief  Configures the TIM peripheral according to the specified
00646   *   parameters in the TIM_ICInitStruct to measure an external PWM signal.
00647   * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
00648   * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
00649   *   that contains the configuration information for the specified TIM peripheral.
00650   * @retval None
00651   */
00652 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
00653 {
00654   uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
00655   uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
00656   /* Check the parameters */
00657   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
00658   /* Select the Opposite Input Polarity */
00659   if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
00660   {
00661     icoppositepolarity = TIM_ICPolarity_Falling;
00662   }
00663   else
00664   {
00665     icoppositepolarity = TIM_ICPolarity_Rising;
00666   }
00667   /* Select the Opposite Input */
00668   if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
00669   {
00670     icoppositeselection = TIM_ICSelection_IndirectTI;
00671   }
00672   else
00673   {
00674     icoppositeselection = TIM_ICSelection_DirectTI;
00675   }
00676   if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
00677   {
00678     /* TI1 Configuration */
00679     TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
00680                TIM_ICInitStruct->TIM_ICFilter);
00681     /* Set the Input Capture Prescaler value */
00682     TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
00683     /* TI2 Configuration */
00684     TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
00685     /* Set the Input Capture Prescaler value */
00686     TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
00687   }
00688   else
00689   { 
00690     /* TI2 Configuration */
00691     TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
00692                TIM_ICInitStruct->TIM_ICFilter);
00693     /* Set the Input Capture Prescaler value */
00694     TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
00695     /* TI1 Configuration */
00696     TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
00697     /* Set the Input Capture Prescaler value */
00698     TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
00699   }
00700 }
00701 
00702 /**
00703   * @brief  Configures the: Break feature, dead time, Lock level, the OSSI,
00704   *   the OSSR State and the AOE(automatic output enable).
00705   * @param  TIMx: where x can be  1 or 8 to select the TIM 
00706   * @param  TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
00707   *   contains the BDTR Register configuration  information for the TIM peripheral.
00708   * @retval None
00709   */
00710 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
00711 {
00712   /* Check the parameters */
00713   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
00714   assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
00715   assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
00716   assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
00717   assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
00718   assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
00719   assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
00720   /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
00721      the OSSI State, the dead time value and the Automatic Output Enable Bit */
00722   TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
00723              TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
00724              TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
00725              TIM_BDTRInitStruct->TIM_AutomaticOutput;
00726 }
00727 
00728 /**
00729   * @brief  Fills each TIM_TimeBaseInitStruct member with its default value.
00730   * @param  TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
00731   *   structure which will be initialized.
00732   * @retval None
00733   */
00734 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
00735 {
00736   /* Set the default configuration */
00737   TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
00738   TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
00739   TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
00740   TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
00741   TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
00742 }
00743 
00744 /**
00745   * @brief  Fills each TIM_OCInitStruct member with its default value.
00746   * @param  TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
00747   *   be initialized.
00748   * @retval None
00749   */
00750 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
00751 {
00752   /* Set the default configuration */
00753   TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
00754   TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
00755   TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
00756   TIM_OCInitStruct->TIM_Pulse = 0x0000;
00757   TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
00758   TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
00759   TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
00760   TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
00761 }
00762 
00763 /**
00764   * @brief  Fills each TIM_ICInitStruct member with its default value.
00765   * @param  TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will
00766   *   be initialized.
00767   * @retval None
00768   */
00769 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
00770 {
00771   /* Set the default configuration */
00772   TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
00773   TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
00774   TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
00775   TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
00776   TIM_ICInitStruct->TIM_ICFilter = 0x00;
00777 }
00778 
00779 /**
00780   * @brief  Fills each TIM_BDTRInitStruct member with its default value.
00781   * @param  TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
00782   *   will be initialized.
00783   * @retval None
00784   */
00785 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
00786 {
00787   /* Set the default configuration */
00788   TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
00789   TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
00790   TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
00791   TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
00792   TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
00793   TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
00794   TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
00795 }
00796 
00797 /**
00798   * @brief  Enables or disables the specified TIM peripheral.
00799   * @param  TIMx: where x can be 1 to 17 to select the TIMx peripheral.
00800   * @param  NewState: new state of the TIMx peripheral.
00801   *   This parameter can be: ENABLE or DISABLE.
00802   * @retval None
00803   */
00804 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
00805 {
00806   /* Check the parameters */
00807   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00808   assert_param(IS_FUNCTIONAL_STATE(NewState));
00809   
00810   if (NewState != DISABLE)
00811   {
00812     /* Enable the TIM Counter */
00813     TIMx->CR1 |= TIM_CR1_CEN;
00814   }
00815   else
00816   {
00817     /* Disable the TIM Counter */
00818     TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
00819   }
00820 }
00821 
00822 /**
00823   * @brief  Enables or disables the TIM peripheral Main Outputs.
00824   * @param  TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.
00825   * @param  NewState: new state of the TIM peripheral Main Outputs.
00826   *   This parameter can be: ENABLE or DISABLE.
00827   * @retval None
00828   */
00829 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
00830 {
00831   /* Check the parameters */
00832   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
00833   assert_param(IS_FUNCTIONAL_STATE(NewState));
00834   if (NewState != DISABLE)
00835   {
00836     /* Enable the TIM Main Output */
00837     TIMx->BDTR |= TIM_BDTR_MOE;
00838   }
00839   else
00840   {
00841     /* Disable the TIM Main Output */
00842     TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));
00843   }  
00844 }
00845 
00846 /**
00847   * @brief  Enables or disables the specified TIM interrupts.
00848   * @param  TIMx: where x can be 1 to 17 to select the TIMx peripheral.
00849   * @param  TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
00850   *   This parameter can be any combination of the following values:
00851   *     @arg TIM_IT_Update: TIM update Interrupt source
00852   *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
00853   *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
00854   *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
00855   *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
00856   *     @arg TIM_IT_COM: TIM Commutation Interrupt source
00857   *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
00858   *     @arg TIM_IT_Break: TIM Break Interrupt source
00859   * @note 
00860   *   - TIM6 and TIM7 can only generate an update interrupt.
00861   *   - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
00862   *      TIM_IT_CC2 or TIM_IT_Trigger. 
00863   *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.   
00864   *   - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. 
00865   *   - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.    
00866   * @param  NewState: new state of the TIM interrupts.
00867   *   This parameter can be: ENABLE or DISABLE.
00868   * @retval None
00869   */
00870 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
00871 {  
00872   /* Check the parameters */
00873   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00874   assert_param(IS_TIM_IT(TIM_IT));
00875   assert_param(IS_FUNCTIONAL_STATE(NewState));
00876   
00877   if (NewState != DISABLE)
00878   {
00879     /* Enable the Interrupt sources */
00880     TIMx->DIER |= TIM_IT;
00881   }
00882   else
00883   {
00884     /* Disable the Interrupt sources */
00885     TIMx->DIER &= (uint16_t)~TIM_IT;
00886   }
00887 }
00888 
00889 /**
00890   * @brief  Configures the TIMx event to be generate by software.
00891   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
00892   * @param  TIM_EventSource: specifies the event source.
00893   *   This parameter can be one or more of the following values:           
00894   *     @arg TIM_EventSource_Update: Timer update Event source
00895   *     @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
00896   *     @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
00897   *     @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
00898   *     @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
00899   *     @arg TIM_EventSource_COM: Timer COM event source  
00900   *     @arg TIM_EventSource_Trigger: Timer Trigger Event source
00901   *     @arg TIM_EventSource_Break: Timer Break event source
00902   * @note 
00903   *   - TIM6 and TIM7 can only generate an update event. 
00904   *   - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.      
00905   * @retval None
00906   */
00907 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
00908 { 
00909   /* Check the parameters */
00910   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00911   assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
00912   
00913   /* Set the event sources */
00914   TIMx->EGR = TIM_EventSource;
00915 }
00916 
00917 /**
00918   * @brief  Configures the TIMx’s DMA interface.
00919   * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 15, 16 or 17 to select 
00920   *   the TIM peripheral.
00921   * @param  TIM_DMABase: DMA Base address.
00922   *   This parameter can be one of the following values:
00923   *     @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
00924   *   TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
00925   *   TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
00926   *   TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
00927   *   TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
00928   *   TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
00929   *   TIM_DMABase_DCR.
00930   * @param  TIM_DMABurstLength: DMA Burst length.
00931   *   This parameter can be one value between:
00932   *   TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.
00933   * @retval None
00934   */
00935 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
00936 {
00937   /* Check the parameters */
00938   assert_param(IS_TIM_LIST4_PERIPH(TIMx));
00939   assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
00940   assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
00941   /* Set the DMA Base and the DMA Burst Length */
00942   TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
00943 }
00944 
00945 /**
00946   * @brief  Enables or disables the TIMx’s DMA Requests.
00947   * @param  TIMx: where x can be  1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17 
00948   *   to select the TIM peripheral. 
00949   * @param  TIM_DMASource: specifies the DMA Request sources.
00950   *   This parameter can be any combination of the following values:
00951   *     @arg TIM_DMA_Update: TIM update Interrupt source
00952   *     @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
00953   *     @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
00954   *     @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
00955   *     @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
00956   *     @arg TIM_DMA_COM: TIM Commutation DMA source
00957   *     @arg TIM_DMA_Trigger: TIM Trigger DMA source
00958   * @param  NewState: new state of the DMA Request sources.
00959   *   This parameter can be: ENABLE or DISABLE.
00960   * @retval None
00961   */
00962 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
00963 { 
00964   /* Check the parameters */
00965   assert_param(IS_TIM_LIST9_PERIPH(TIMx));
00966   assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
00967   assert_param(IS_FUNCTIONAL_STATE(NewState));
00968   
00969   if (NewState != DISABLE)
00970   {
00971     /* Enable the DMA sources */
00972     TIMx->DIER |= TIM_DMASource; 
00973   }
00974   else
00975   {
00976     /* Disable the DMA sources */
00977     TIMx->DIER &= (uint16_t)~TIM_DMASource;
00978   }
00979 }
00980 
00981 /**
00982   * @brief  Configures the TIMx interrnal Clock
00983   * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15
00984   *   to select the TIM peripheral.
00985   * @retval None
00986   */
00987 void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
00988 {
00989   /* Check the parameters */
00990   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
00991   /* Disable slave mode to clock the prescaler directly with the internal clock */
00992   TIMx->SMCR &=  (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
00993 }
00994 
00995 /**
00996   * @brief  Configures the TIMx Internal Trigger as External Clock
00997   * @param  TIMx: where x can be  1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
00998   * @param  TIM_ITRSource: Trigger source.
00999   *   This parameter can be one of the following values:
01000   * @param  TIM_TS_ITR0: Internal Trigger 0
01001   * @param  TIM_TS_ITR1: Internal Trigger 1
01002   * @param  TIM_TS_ITR2: Internal Trigger 2
01003   * @param  TIM_TS_ITR3: Internal Trigger 3
01004   * @retval None
01005   */
01006 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
01007 {
01008   /* Check the parameters */
01009   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
01010   assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
01011   /* Select the Internal Trigger */
01012   TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
01013   /* Select the External clock mode1 */
01014   TIMx->SMCR |= TIM_SlaveMode_External1;
01015 }
01016 
01017 /**
01018   * @brief  Configures the TIMx Trigger as External Clock
01019   * @param  TIMx: where x can be  1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
01020   * @param  TIM_TIxExternalCLKSource: Trigger source.
01021   *   This parameter can be one of the following values:
01022   *     @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
01023   *     @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
01024   *     @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
01025   * @param  TIM_ICPolarity: specifies the TIx Polarity.
01026   *   This parameter can be one of the following values:
01027   *     @arg TIM_ICPolarity_Rising
01028   *     @arg TIM_ICPolarity_Falling
01029   * @param  ICFilter : specifies the filter value.
01030   *   This parameter must be a value between 0x0 and 0xF.
01031   * @retval None
01032   */
01033 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
01034                                 uint16_t TIM_ICPolarity, uint16_t ICFilter)
01035 {
01036   /* Check the parameters */
01037   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
01038   assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
01039   assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
01040   assert_param(IS_TIM_IC_FILTER(ICFilter));
01041   /* Configure the Timer Input Clock Source */
01042   if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
01043   {
01044     TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
01045   }
01046   else
01047   {
01048     TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
01049   }
01050   /* Select the Trigger source */
01051   TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
01052   /* Select the External clock mode1 */
01053   TIMx->SMCR |= TIM_SlaveMode_External1;
01054 }
01055 
01056 /**
01057   * @brief  Configures the External clock Mode1
01058   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01059   * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
01060   *   This parameter can be one of the following values:
01061   *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
01062   *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
01063   *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
01064   *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
01065   * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
01066   *   This parameter can be one of the following values:
01067   *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
01068   *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
01069   * @param  ExtTRGFilter: External Trigger Filter.
01070   *   This parameter must be a value between 0x00 and 0x0F
01071   * @retval None
01072   */
01073 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
01074                              uint16_t ExtTRGFilter)
01075 {
01076   uint16_t tmpsmcr = 0;
01077   /* Check the parameters */
01078   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01079   assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
01080   assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
01081   assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
01082   /* Configure the ETR Clock source */
01083   TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
01084   
01085   /* Get the TIMx SMCR register value */
01086   tmpsmcr = TIMx->SMCR;
01087   /* Reset the SMS Bits */
01088   tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
01089   /* Select the External clock mode1 */
01090   tmpsmcr |= TIM_SlaveMode_External1;
01091   /* Select the Trigger selection : ETRF */
01092   tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
01093   tmpsmcr |= TIM_TS_ETRF;
01094   /* Write to TIMx SMCR */
01095   TIMx->SMCR = tmpsmcr;
01096 }
01097 
01098 /**
01099   * @brief  Configures the External clock Mode2
01100   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01101   * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
01102   *   This parameter can be one of the following values:
01103   *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
01104   *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
01105   *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
01106   *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
01107   * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
01108   *   This parameter can be one of the following values:
01109   *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
01110   *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
01111   * @param  ExtTRGFilter: External Trigger Filter.
01112   *   This parameter must be a value between 0x00 and 0x0F
01113   * @retval None
01114   */
01115 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
01116                              uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
01117 {
01118   /* Check the parameters */
01119   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01120   assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
01121   assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
01122   assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
01123   /* Configure the ETR Clock source */
01124   TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
01125   /* Enable the External clock mode2 */
01126   TIMx->SMCR |= TIM_SMCR_ECE;
01127 }
01128 
01129 /**
01130   * @brief  Configures the TIMx External Trigger (ETR).
01131   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01132   * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
01133   *   This parameter can be one of the following values:
01134   *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
01135   *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
01136   *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
01137   *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
01138   * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
01139   *   This parameter can be one of the following values:
01140   *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
01141   *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
01142   * @param  ExtTRGFilter: External Trigger Filter.
01143   *   This parameter must be a value between 0x00 and 0x0F
01144   * @retval None
01145   */
01146 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
01147                    uint16_t ExtTRGFilter)
01148 {
01149   uint16_t tmpsmcr = 0;
01150   /* Check the parameters */
01151   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01152   assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
01153   assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
01154   assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
01155   tmpsmcr = TIMx->SMCR;
01156   /* Reset the ETR Bits */
01157   tmpsmcr &= SMCR_ETR_Mask;
01158   /* Set the Prescaler, the Filter value and the Polarity */
01159   tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
01160   /* Write to TIMx SMCR */
01161   TIMx->SMCR = tmpsmcr;
01162 }
01163 
01164 /**
01165   * @brief  Configures the TIMx Prescaler.
01166   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
01167   * @param  Prescaler: specifies the Prescaler Register value
01168   * @param  TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
01169   *   This parameter can be one of the following values:
01170   *     @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
01171   *     @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
01172   * @retval None
01173   */
01174 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
01175 {
01176   /* Check the parameters */
01177   assert_param(IS_TIM_ALL_PERIPH(TIMx));
01178   assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
01179   /* Set the Prescaler value */
01180   TIMx->PSC = Prescaler;
01181   /* Set or reset the UG Bit */
01182   TIMx->EGR = TIM_PSCReloadMode;
01183 }
01184 
01185 /**
01186   * @brief  Specifies the TIMx Counter Mode to be used.
01187   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01188   * @param  TIM_CounterMode: specifies the Counter Mode to be used
01189   *   This parameter can be one of the following values:
01190   *     @arg TIM_CounterMode_Up: TIM Up Counting Mode
01191   *     @arg TIM_CounterMode_Down: TIM Down Counting Mode
01192   *     @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
01193   *     @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
01194   *     @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
01195   * @retval None
01196   */
01197 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
01198 {
01199   uint16_t tmpcr1 = 0;
01200   /* Check the parameters */
01201   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01202   assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
01203   tmpcr1 = TIMx->CR1;
01204   /* Reset the CMS and DIR Bits */
01205   tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
01206   /* Set the Counter Mode */
01207   tmpcr1 |= TIM_CounterMode;
01208   /* Write to TIMx CR1 register */
01209   TIMx->CR1 = tmpcr1;
01210 }
01211 
01212 /**
01213   * @brief  Selects the Input Trigger source
01214   * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
01215   * @param  TIM_InputTriggerSource: The Input Trigger source.
01216   *   This parameter can be one of the following values:
01217   *     @arg TIM_TS_ITR0: Internal Trigger 0
01218   *     @arg TIM_TS_ITR1: Internal Trigger 1
01219   *     @arg TIM_TS_ITR2: Internal Trigger 2
01220   *     @arg TIM_TS_ITR3: Internal Trigger 3
01221   *     @arg TIM_TS_TI1F_ED: TI1 Edge Detector
01222   *     @arg TIM_TS_TI1FP1: Filtered Timer Input 1
01223   *     @arg TIM_TS_TI2FP2: Filtered Timer Input 2
01224   *     @arg TIM_TS_ETRF: External Trigger input
01225   * @retval None
01226   */
01227 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
01228 {
01229   uint16_t tmpsmcr = 0;
01230   /* Check the parameters */
01231   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
01232   assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
01233   /* Get the TIMx SMCR register value */
01234   tmpsmcr = TIMx->SMCR;
01235   /* Reset the TS Bits */
01236   tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
01237   /* Set the Input Trigger source */
01238   tmpsmcr |= TIM_InputTriggerSource;
01239   /* Write to TIMx SMCR */
01240   TIMx->SMCR = tmpsmcr;
01241 }
01242 
01243 /**
01244   * @brief  Configures the TIMx Encoder Interface.
01245   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01246   * @param  TIM_EncoderMode: specifies the TIMx Encoder Mode.
01247   *   This parameter can be one of the following values:
01248   *     @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
01249   *     @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
01250   *     @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
01251   *                                on the level of the other input.
01252   * @param  TIM_IC1Polarity: specifies the IC1 Polarity
01253   *   This parmeter can be one of the following values:
01254   *     @arg TIM_ICPolarity_Falling: IC Falling edge.
01255   *     @arg TIM_ICPolarity_Rising: IC Rising edge.
01256   * @param  TIM_IC2Polarity: specifies the IC2 Polarity
01257   *   This parmeter can be one of the following values:
01258   *     @arg TIM_ICPolarity_Falling: IC Falling edge.
01259   *     @arg TIM_ICPolarity_Rising: IC Rising edge.
01260   * @retval None
01261   */
01262 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
01263                                 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
01264 {
01265   uint16_t tmpsmcr = 0;
01266   uint16_t tmpccmr1 = 0;
01267   uint16_t tmpccer = 0;
01268     
01269   /* Check the parameters */
01270   assert_param(IS_TIM_LIST5_PERIPH(TIMx));
01271   assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
01272   assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
01273   assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
01274 
01275   /* Get the TIMx SMCR register value */
01276   tmpsmcr = TIMx->SMCR;
01277   
01278   /* Get the TIMx CCMR1 register value */
01279   tmpccmr1 = TIMx->CCMR1;
01280   
01281   /* Get the TIMx CCER register value */
01282   tmpccer = TIMx->CCER;
01283   
01284   /* Set the encoder Mode */
01285   tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
01286   tmpsmcr |= TIM_EncoderMode;
01287   
01288   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
01289   tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
01290   tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
01291   
01292   /* Set the TI1 and the TI2 Polarities */
01293   tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
01294   tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
01295   
01296   /* Write to TIMx SMCR */
01297   TIMx->SMCR = tmpsmcr;
01298   /* Write to TIMx CCMR1 */
01299   TIMx->CCMR1 = tmpccmr1;
01300   /* Write to TIMx CCER */
01301   TIMx->CCER = tmpccer;
01302 }
01303 
01304 /**
01305   * @brief  Forces the TIMx output 1 waveform to active or inactive level.
01306   * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
01307   * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
01308   *   This parameter can be one of the following values:
01309   *     @arg TIM_ForcedAction_Active: Force active level on OC1REF
01310   *     @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
01311   * @retval None
01312   */
01313 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
01314 {
01315   uint16_t tmpccmr1 = 0;
01316   /* Check the parameters */
01317   assert_param(IS_TIM_LIST8_PERIPH(TIMx));
01318   assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
01319   tmpccmr1 = TIMx->CCMR1;
01320   /* Reset the OC1M Bits */
01321   tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
01322   /* Configure The Forced output Mode */
01323   tmpccmr1 |= TIM_ForcedAction;
01324   /* Write to TIMx CCMR1 register */
01325   TIMx->CCMR1 = tmpccmr1;
01326 }
01327 
01328 /**
01329   * @brief  Forces the TIMx output 2 waveform to active or inactive level.
01330   * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
01331   * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
01332   *   This parameter can be one of the following values:
01333   *     @arg TIM_ForcedAction_Active: Force active level on OC2REF
01334   *     @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
01335   * @retval None
01336   */
01337 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
01338 {
01339   uint16_t tmpccmr1 = 0;
01340   /* Check the parameters */
01341   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
01342   assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
01343   tmpccmr1 = TIMx->CCMR1;
01344   /* Reset the OC2M Bits */
01345   tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
01346   /* Configure The Forced output Mode */
01347   tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
01348   /* Write to TIMx CCMR1 register */
01349   TIMx->CCMR1 = tmpccmr1;
01350 }
01351 
01352 /**
01353   * @brief  Forces the TIMx output 3 waveform to active or inactive level.
01354   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01355   * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
01356   *   This parameter can be one of the following values:
01357   *     @arg TIM_ForcedAction_Active: Force active level on OC3REF
01358   *     @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
01359   * @retval None
01360   */
01361 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
01362 {
01363   uint16_t tmpccmr2 = 0;
01364   /* Check the parameters */
01365   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01366   assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
01367   tmpccmr2 = TIMx->CCMR2;
01368   /* Reset the OC1M Bits */
01369   tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
01370   /* Configure The Forced output Mode */
01371   tmpccmr2 |= TIM_ForcedAction;
01372   /* Write to TIMx CCMR2 register */
01373   TIMx->CCMR2 = tmpccmr2;
01374 }
01375 
01376 /**
01377   * @brief  Forces the TIMx output 4 waveform to active or inactive level.
01378   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01379   * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
01380   *   This parameter can be one of the following values:
01381   *     @arg TIM_ForcedAction_Active: Force active level on OC4REF
01382   *     @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
01383   * @retval None
01384   */
01385 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
01386 {
01387   uint16_t tmpccmr2 = 0;
01388   /* Check the parameters */
01389   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01390   assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
01391   tmpccmr2 = TIMx->CCMR2;
01392   /* Reset the OC2M Bits */
01393   tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
01394   /* Configure The Forced output Mode */
01395   tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
01396   /* Write to TIMx CCMR2 register */
01397   TIMx->CCMR2 = tmpccmr2;
01398 }
01399 
01400 /**
01401   * @brief  Enables or disables TIMx peripheral Preload register on ARR.
01402   * @param  TIMx: where x can be  1 to 17 to select the TIM peripheral.
01403   * @param  NewState: new state of the TIMx peripheral Preload register
01404   *   This parameter can be: ENABLE or DISABLE.
01405   * @retval None
01406   */
01407 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
01408 {
01409   /* Check the parameters */
01410   assert_param(IS_TIM_ALL_PERIPH(TIMx));
01411   assert_param(IS_FUNCTIONAL_STATE(NewState));
01412   if (NewState != DISABLE)
01413   {
01414     /* Set the ARR Preload Bit */
01415     TIMx->CR1 |= TIM_CR1_ARPE;
01416   }
01417   else
01418   {
01419     /* Reset the ARR Preload Bit */
01420     TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
01421   }
01422 }
01423 
01424 /**
01425   * @brief  Selects the TIM peripheral Commutation event.
01426   * @param  TIMx: where x can be  1, 8, 15, 16 or 17 to select the TIMx peripheral
01427   * @param  NewState: new state of the Commutation event.
01428   *   This parameter can be: ENABLE or DISABLE.
01429   * @retval None
01430   */
01431 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
01432 {
01433   /* Check the parameters */
01434   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
01435   assert_param(IS_FUNCTIONAL_STATE(NewState));
01436   if (NewState != DISABLE)
01437   {
01438     /* Set the COM Bit */
01439     TIMx->CR2 |= TIM_CR2_CCUS;
01440   }
01441   else
01442   {
01443     /* Reset the COM Bit */
01444     TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);
01445   }
01446 }
01447 
01448 /**
01449   * @brief  Selects the TIMx peripheral Capture Compare DMA source.
01450   * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 15, 16 or 17 to select 
01451   *   the TIM peripheral.
01452   * @param  NewState: new state of the Capture Compare DMA source
01453   *   This parameter can be: ENABLE or DISABLE.
01454   * @retval None
01455   */
01456 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
01457 {
01458   /* Check the parameters */
01459   assert_param(IS_TIM_LIST4_PERIPH(TIMx));
01460   assert_param(IS_FUNCTIONAL_STATE(NewState));
01461   if (NewState != DISABLE)
01462   {
01463     /* Set the CCDS Bit */
01464     TIMx->CR2 |= TIM_CR2_CCDS;
01465   }
01466   else
01467   {
01468     /* Reset the CCDS Bit */
01469     TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
01470   }
01471 }
01472 
01473 /**
01474   * @brief  Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
01475   * @param  TIMx: where x can be   1, 2, 3, 4, 5, 8 or 15 
01476   *   to select the TIMx peripheral
01477   * @param  NewState: new state of the Capture Compare Preload Control bit
01478   *   This parameter can be: ENABLE or DISABLE.
01479   * @retval None
01480   */
01481 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
01482 { 
01483   /* Check the parameters */
01484   assert_param(IS_TIM_LIST5_PERIPH(TIMx));
01485   assert_param(IS_FUNCTIONAL_STATE(NewState));
01486   if (NewState != DISABLE)
01487   {
01488     /* Set the CCPC Bit */
01489     TIMx->CR2 |= TIM_CR2_CCPC;
01490   }
01491   else
01492   {
01493     /* Reset the CCPC Bit */
01494     TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);
01495   }
01496 }
01497 
01498 /**
01499   * @brief  Enables or disables the TIMx peripheral Preload register on CCR1.
01500   * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
01501   * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
01502   *   This parameter can be one of the following values:
01503   *     @arg TIM_OCPreload_Enable
01504   *     @arg TIM_OCPreload_Disable
01505   * @retval None
01506   */
01507 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
01508 {
01509   uint16_t tmpccmr1 = 0;
01510   /* Check the parameters */
01511   assert_param(IS_TIM_LIST8_PERIPH(TIMx));
01512   assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
01513   tmpccmr1 = TIMx->CCMR1;
01514   /* Reset the OC1PE Bit */
01515   tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
01516   /* Enable or Disable the Output Compare Preload feature */
01517   tmpccmr1 |= TIM_OCPreload;
01518   /* Write to TIMx CCMR1 register */
01519   TIMx->CCMR1 = tmpccmr1;
01520 }
01521 
01522 /**
01523   * @brief  Enables or disables the TIMx peripheral Preload register on CCR2.
01524   * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select 
01525   *   the TIM peripheral.
01526   * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
01527   *   This parameter can be one of the following values:
01528   *     @arg TIM_OCPreload_Enable
01529   *     @arg TIM_OCPreload_Disable
01530   * @retval None
01531   */
01532 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
01533 {
01534   uint16_t tmpccmr1 = 0;
01535   /* Check the parameters */
01536   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
01537   assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
01538   tmpccmr1 = TIMx->CCMR1;
01539   /* Reset the OC2PE Bit */
01540   tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
01541   /* Enable or Disable the Output Compare Preload feature */
01542   tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
01543   /* Write to TIMx CCMR1 register */
01544   TIMx->CCMR1 = tmpccmr1;
01545 }
01546 
01547 /**
01548   * @brief  Enables or disables the TIMx peripheral Preload register on CCR3.
01549   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01550   * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
01551   *   This parameter can be one of the following values:
01552   *     @arg TIM_OCPreload_Enable
01553   *     @arg TIM_OCPreload_Disable
01554   * @retval None
01555   */
01556 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
01557 {
01558   uint16_t tmpccmr2 = 0;
01559   /* Check the parameters */
01560   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01561   assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
01562   tmpccmr2 = TIMx->CCMR2;
01563   /* Reset the OC3PE Bit */
01564   tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
01565   /* Enable or Disable the Output Compare Preload feature */
01566   tmpccmr2 |= TIM_OCPreload;
01567   /* Write to TIMx CCMR2 register */
01568   TIMx->CCMR2 = tmpccmr2;
01569 }
01570 
01571 /**
01572   * @brief  Enables or disables the TIMx peripheral Preload register on CCR4.
01573   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01574   * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
01575   *   This parameter can be one of the following values:
01576   *     @arg TIM_OCPreload_Enable
01577   *     @arg TIM_OCPreload_Disable
01578   * @retval None
01579   */
01580 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
01581 {
01582   uint16_t tmpccmr2 = 0;
01583   /* Check the parameters */
01584   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01585   assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
01586   tmpccmr2 = TIMx->CCMR2;
01587   /* Reset the OC4PE Bit */
01588   tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
01589   /* Enable or Disable the Output Compare Preload feature */
01590   tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
01591   /* Write to TIMx CCMR2 register */
01592   TIMx->CCMR2 = tmpccmr2;
01593 }
01594 
01595 /**
01596   * @brief  Configures the TIMx Output Compare 1 Fast feature.
01597   * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
01598   * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
01599   *   This parameter can be one of the following values:
01600   *     @arg TIM_OCFast_Enable: TIM output compare fast enable
01601   *     @arg TIM_OCFast_Disable: TIM output compare fast disable
01602   * @retval None
01603   */
01604 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
01605 {
01606   uint16_t tmpccmr1 = 0;
01607   /* Check the parameters */
01608   assert_param(IS_TIM_LIST8_PERIPH(TIMx));
01609   assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
01610   /* Get the TIMx CCMR1 register value */
01611   tmpccmr1 = TIMx->CCMR1;
01612   /* Reset the OC1FE Bit */
01613   tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
01614   /* Enable or Disable the Output Compare Fast Bit */
01615   tmpccmr1 |= TIM_OCFast;
01616   /* Write to TIMx CCMR1 */
01617   TIMx->CCMR1 = tmpccmr1;
01618 }
01619 
01620 /**
01621   * @brief  Configures the TIMx Output Compare 2 Fast feature.
01622   * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select 
01623   *   the TIM peripheral.
01624   * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
01625   *   This parameter can be one of the following values:
01626   *     @arg TIM_OCFast_Enable: TIM output compare fast enable
01627   *     @arg TIM_OCFast_Disable: TIM output compare fast disable
01628   * @retval None
01629   */
01630 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
01631 {
01632   uint16_t tmpccmr1 = 0;
01633   /* Check the parameters */
01634   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
01635   assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
01636   /* Get the TIMx CCMR1 register value */
01637   tmpccmr1 = TIMx->CCMR1;
01638   /* Reset the OC2FE Bit */
01639   tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
01640   /* Enable or Disable the Output Compare Fast Bit */
01641   tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
01642   /* Write to TIMx CCMR1 */
01643   TIMx->CCMR1 = tmpccmr1;
01644 }
01645 
01646 /**
01647   * @brief  Configures the TIMx Output Compare 3 Fast feature.
01648   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01649   * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
01650   *   This parameter can be one of the following values:
01651   *     @arg TIM_OCFast_Enable: TIM output compare fast enable
01652   *     @arg TIM_OCFast_Disable: TIM output compare fast disable
01653   * @retval None
01654   */
01655 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
01656 {
01657   uint16_t tmpccmr2 = 0;
01658   /* Check the parameters */
01659   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01660   assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
01661   /* Get the TIMx CCMR2 register value */
01662   tmpccmr2 = TIMx->CCMR2;
01663   /* Reset the OC3FE Bit */
01664   tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
01665   /* Enable or Disable the Output Compare Fast Bit */
01666   tmpccmr2 |= TIM_OCFast;
01667   /* Write to TIMx CCMR2 */
01668   TIMx->CCMR2 = tmpccmr2;
01669 }
01670 
01671 /**
01672   * @brief  Configures the TIMx Output Compare 4 Fast feature.
01673   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01674   * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
01675   *   This parameter can be one of the following values:
01676   *     @arg TIM_OCFast_Enable: TIM output compare fast enable
01677   *     @arg TIM_OCFast_Disable: TIM output compare fast disable
01678   * @retval None
01679   */
01680 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
01681 {
01682   uint16_t tmpccmr2 = 0;
01683   /* Check the parameters */
01684   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01685   assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
01686   /* Get the TIMx CCMR2 register value */
01687   tmpccmr2 = TIMx->CCMR2;
01688   /* Reset the OC4FE Bit */
01689   tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
01690   /* Enable or Disable the Output Compare Fast Bit */
01691   tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
01692   /* Write to TIMx CCMR2 */
01693   TIMx->CCMR2 = tmpccmr2;
01694 }
01695 
01696 /**
01697   * @brief  Clears or safeguards the OCREF1 signal on an external event
01698   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01699   * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
01700   *   This parameter can be one of the following values:
01701   *     @arg TIM_OCClear_Enable: TIM Output clear enable
01702   *     @arg TIM_OCClear_Disable: TIM Output clear disable
01703   * @retval None
01704   */
01705 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
01706 {
01707   uint16_t tmpccmr1 = 0;
01708   /* Check the parameters */
01709   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01710   assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
01711 
01712   tmpccmr1 = TIMx->CCMR1;
01713 
01714   /* Reset the OC1CE Bit */
01715   tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
01716   /* Enable or Disable the Output Compare Clear Bit */
01717   tmpccmr1 |= TIM_OCClear;
01718   /* Write to TIMx CCMR1 register */
01719   TIMx->CCMR1 = tmpccmr1;
01720 }
01721 
01722 /**
01723   * @brief  Clears or safeguards the OCREF2 signal on an external event
01724   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01725   * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
01726   *   This parameter can be one of the following values:
01727   *     @arg TIM_OCClear_Enable: TIM Output clear enable
01728   *     @arg TIM_OCClear_Disable: TIM Output clear disable
01729   * @retval None
01730   */
01731 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
01732 {
01733   uint16_t tmpccmr1 = 0;
01734   /* Check the parameters */
01735   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01736   assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
01737   tmpccmr1 = TIMx->CCMR1;
01738   /* Reset the OC2CE Bit */
01739   tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
01740   /* Enable or Disable the Output Compare Clear Bit */
01741   tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
01742   /* Write to TIMx CCMR1 register */
01743   TIMx->CCMR1 = tmpccmr1;
01744 }
01745 
01746 /**
01747   * @brief  Clears or safeguards the OCREF3 signal on an external event
01748   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01749   * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
01750   *   This parameter can be one of the following values:
01751   *     @arg TIM_OCClear_Enable: TIM Output clear enable
01752   *     @arg TIM_OCClear_Disable: TIM Output clear disable
01753   * @retval None
01754   */
01755 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
01756 {
01757   uint16_t tmpccmr2 = 0;
01758   /* Check the parameters */
01759   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01760   assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
01761   tmpccmr2 = TIMx->CCMR2;
01762   /* Reset the OC3CE Bit */
01763   tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
01764   /* Enable or Disable the Output Compare Clear Bit */
01765   tmpccmr2 |= TIM_OCClear;
01766   /* Write to TIMx CCMR2 register */
01767   TIMx->CCMR2 = tmpccmr2;
01768 }
01769 
01770 /**
01771   * @brief  Clears or safeguards the OCREF4 signal on an external event
01772   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01773   * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
01774   *   This parameter can be one of the following values:
01775   *     @arg TIM_OCClear_Enable: TIM Output clear enable
01776   *     @arg TIM_OCClear_Disable: TIM Output clear disable
01777   * @retval None
01778   */
01779 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
01780 {
01781   uint16_t tmpccmr2 = 0;
01782   /* Check the parameters */
01783   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01784   assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
01785   tmpccmr2 = TIMx->CCMR2;
01786   /* Reset the OC4CE Bit */
01787   tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
01788   /* Enable or Disable the Output Compare Clear Bit */
01789   tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
01790   /* Write to TIMx CCMR2 register */
01791   TIMx->CCMR2 = tmpccmr2;
01792 }
01793 
01794 /**
01795   * @brief  Configures the TIMx channel 1 polarity.
01796   * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
01797   * @param  TIM_OCPolarity: specifies the OC1 Polarity
01798   *   This parmeter can be one of the following values:
01799   *     @arg TIM_OCPolarity_High: Output Compare active high
01800   *     @arg TIM_OCPolarity_Low: Output Compare active low
01801   * @retval None
01802   */
01803 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
01804 {
01805   uint16_t tmpccer = 0;
01806   /* Check the parameters */
01807   assert_param(IS_TIM_LIST8_PERIPH(TIMx));
01808   assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
01809   tmpccer = TIMx->CCER;
01810   /* Set or Reset the CC1P Bit */
01811   tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
01812   tmpccer |= TIM_OCPolarity;
01813   /* Write to TIMx CCER register */
01814   TIMx->CCER = tmpccer;
01815 }
01816 
01817 /**
01818   * @brief  Configures the TIMx Channel 1N polarity.
01819   * @param  TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
01820   * @param  TIM_OCNPolarity: specifies the OC1N Polarity
01821   *   This parmeter can be one of the following values:
01822   *     @arg TIM_OCNPolarity_High: Output Compare active high
01823   *     @arg TIM_OCNPolarity_Low: Output Compare active low
01824   * @retval None
01825   */
01826 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
01827 {
01828   uint16_t tmpccer = 0;
01829   /* Check the parameters */
01830   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
01831   assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
01832    
01833   tmpccer = TIMx->CCER;
01834   /* Set or Reset the CC1NP Bit */
01835   tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);
01836   tmpccer |= TIM_OCNPolarity;
01837   /* Write to TIMx CCER register */
01838   TIMx->CCER = tmpccer;
01839 }
01840 
01841 /**
01842   * @brief  Configures the TIMx channel 2 polarity.
01843   * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
01844   * @param  TIM_OCPolarity: specifies the OC2 Polarity
01845   *   This parmeter can be one of the following values:
01846   *     @arg TIM_OCPolarity_High: Output Compare active high
01847   *     @arg TIM_OCPolarity_Low: Output Compare active low
01848   * @retval None
01849   */
01850 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
01851 {
01852   uint16_t tmpccer = 0;
01853   /* Check the parameters */
01854   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
01855   assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
01856   tmpccer = TIMx->CCER;
01857   /* Set or Reset the CC2P Bit */
01858   tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
01859   tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
01860   /* Write to TIMx CCER register */
01861   TIMx->CCER = tmpccer;
01862 }
01863 
01864 /**
01865   * @brief  Configures the TIMx Channel 2N polarity.
01866   * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
01867   * @param  TIM_OCNPolarity: specifies the OC2N Polarity
01868   *   This parmeter can be one of the following values:
01869   *     @arg TIM_OCNPolarity_High: Output Compare active high
01870   *     @arg TIM_OCNPolarity_Low: Output Compare active low
01871   * @retval None
01872   */
01873 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
01874 {
01875   uint16_t tmpccer = 0;
01876   /* Check the parameters */
01877   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
01878   assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
01879   
01880   tmpccer = TIMx->CCER;
01881   /* Set or Reset the CC2NP Bit */
01882   tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);
01883   tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
01884   /* Write to TIMx CCER register */
01885   TIMx->CCER = tmpccer;
01886 }
01887 
01888 /**
01889   * @brief  Configures the TIMx channel 3 polarity.
01890   * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01891   * @param  TIM_OCPolarity: specifies the OC3 Polarity
01892   *   This parmeter can be one of the following values:
01893   *     @arg TIM_OCPolarity_High: Output Compare active high
01894   *     @arg TIM_OCPolarity_Low: Output Compare active low
01895   * @retval None
01896   */
01897 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
01898 {
01899   uint16_t tmpccer = 0;
01900   /* Check the parameters */
01901   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01902   assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
01903   tmpccer = TIMx->CCER;
01904   /* Set or Reset the CC3P Bit */
01905   tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
01906   tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
01907   /* Write to TIMx CCER register */
01908   TIMx->CCER = tmpccer;
01909 }
01910 
01911 /**
01912   * @brief  Configures the TIMx Channel 3N polarity.
01913   * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
01914   * @param  TIM_OCNPolarity: specifies the OC3N Polarity
01915   *   This parmeter can be one of the following values:
01916   *     @arg TIM_OCNPolarity_High: Output Compare active high
01917   *     @arg TIM_OCNPolarity_Low: Output Compare active low
01918   * @retval None
01919   */
01920 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
01921 {
01922   uint16_t tmpccer = 0;
01923  
01924   /* Check the parameters */
01925   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
01926   assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
01927     
01928   tmpccer = TIMx->CCER;
01929   /* Set or Reset the CC3NP Bit */
01930   tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);
01931   tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
01932   /* Write to TIMx CCER register */
01933   TIMx->CCER = tmpccer;
01934 }
01935 
01936 /**
01937   * @brief  Configures the TIMx channel 4 polarity.
01938   * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01939   * @param  TIM_OCPolarity: specifies the OC4 Polarity
01940   *   This parmeter can be one of the following values:
01941   *     @arg TIM_OCPolarity_High: Output Compare active high
01942   *     @arg TIM_OCPolarity_Low: Output Compare active low
01943   * @retval None
01944   */
01945 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
01946 {
01947   uint16_t tmpccer = 0;
01948   /* Check the parameters */
01949   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01950   assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
01951   tmpccer = TIMx->CCER;
01952   /* Set or Reset the CC4P Bit */
01953   tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
01954   tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
01955   /* Write to TIMx CCER register */
01956   TIMx->CCER = tmpccer;
01957 }
01958 
01959 /**
01960   * @brief  Enables or disables the TIM Capture Compare Channel x.
01961   * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
01962   * @param  TIM_Channel: specifies the TIM Channel
01963   *   This parmeter can be one of the following values:
01964   *     @arg TIM_Channel_1: TIM Channel 1
01965   *     @arg TIM_Channel_2: TIM Channel 2
01966   *     @arg TIM_Channel_3: TIM Channel 3
01967   *     @arg TIM_Channel_4: TIM Channel 4
01968   * @param  TIM_CCx: specifies the TIM Channel CCxE bit new state.
01969   *   This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. 
01970   * @retval None
01971   */
01972 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
01973 {
01974   uint16_t tmp = 0;
01975 
01976   /* Check the parameters */
01977   assert_param(IS_TIM_LIST8_PERIPH(TIMx));
01978   assert_param(IS_TIM_CHANNEL(TIM_Channel));
01979   assert_param(IS_TIM_CCX(TIM_CCx));
01980 
01981   tmp = CCER_CCE_Set << TIM_Channel;
01982 
01983   /* Reset the CCxE Bit */
01984   TIMx->CCER &= (uint16_t)~ tmp;
01985 
01986   /* Set or reset the CCxE Bit */ 
01987   TIMx->CCER |=  (uint16_t)(TIM_CCx << TIM_Channel);
01988 }
01989 
01990 /**
01991   * @brief  Enables or disables the TIM Capture Compare Channel xN.
01992   * @param  TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
01993   * @param  TIM_Channel: specifies the TIM Channel
01994   *   This parmeter can be one of the following values:
01995   *     @arg TIM_Channel_1: TIM Channel 1
01996   *     @arg TIM_Channel_2: TIM Channel 2
01997   *     @arg TIM_Channel_3: TIM Channel 3
01998   * @param  TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
01999   *   This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. 
02000   * @retval None
02001   */
02002 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
02003 {
02004   uint16_t tmp = 0;
02005 
02006   /* Check the parameters */
02007   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
02008   assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
02009   assert_param(IS_TIM_CCXN(TIM_CCxN));
02010 
02011   tmp = CCER_CCNE_Set << TIM_Channel;
02012 
02013   /* Reset the CCxNE Bit */
02014   TIMx->CCER &= (uint16_t) ~tmp;
02015 
02016   /* Set or reset the CCxNE Bit */ 
02017   TIMx->CCER |=  (uint16_t)(TIM_CCxN << TIM_Channel);
02018 }
02019 
02020 /**
02021   * @brief  Selects the TIM Ouput Compare Mode.
02022   * @note   This function disables the selected channel before changing the Ouput
02023   *         Compare Mode.
02024   *         User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
02025   * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
02026   * @param  TIM_Channel: specifies the TIM Channel
02027   *   This parmeter can be one of the following values:
02028   *     @arg TIM_Channel_1: TIM Channel 1
02029   *     @arg TIM_Channel_2: TIM Channel 2
02030   *     @arg TIM_Channel_3: TIM Channel 3
02031   *     @arg TIM_Channel_4: TIM Channel 4
02032   * @param  TIM_OCMode: specifies the TIM Output Compare Mode.
02033   *   This paramter can be one of the following values:
02034   *     @arg TIM_OCMode_Timing
02035   *     @arg TIM_OCMode_Active
02036   *     @arg TIM_OCMode_Toggle
02037   *     @arg TIM_OCMode_PWM1
02038   *     @arg TIM_OCMode_PWM2
02039   *     @arg TIM_ForcedAction_Active
02040   *     @arg TIM_ForcedAction_InActive
02041   * @retval None
02042   */
02043 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
02044 {
02045   uint32_t tmp = 0;
02046   uint16_t tmp1 = 0;
02047 
02048   /* Check the parameters */
02049   assert_param(IS_TIM_LIST8_PERIPH(TIMx));
02050   assert_param(IS_TIM_CHANNEL(TIM_Channel));
02051   assert_param(IS_TIM_OCM(TIM_OCMode));
02052 
02053   tmp = (uint32_t) TIMx;
02054   tmp += CCMR_Offset;
02055 
02056   tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;
02057 
02058   /* Disable the Channel: Reset the CCxE Bit */
02059   TIMx->CCER &= (uint16_t) ~tmp1;
02060 
02061   if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
02062   {
02063     tmp += (TIM_Channel>>1);
02064 
02065     /* Reset the OCxM bits in the CCMRx register */
02066     *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
02067    
02068     /* Configure the OCxM bits in the CCMRx register */
02069     *(__IO uint32_t *) tmp |= TIM_OCMode;
02070   }
02071   else
02072   {
02073     tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
02074 
02075     /* Reset the OCxM bits in the CCMRx register */
02076     *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
02077     
02078     /* Configure the OCxM bits in the CCMRx register */
02079     *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
02080   }
02081 }
02082 
02083 /**
02084   * @brief  Enables or Disables the TIMx Update event.
02085   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
02086   * @param  NewState: new state of the TIMx UDIS bit
02087   *   This parameter can be: ENABLE or DISABLE.
02088   * @retval None
02089   */
02090 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
02091 {
02092   /* Check the parameters */
02093   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02094   assert_param(IS_FUNCTIONAL_STATE(NewState));
02095   if (NewState != DISABLE)
02096   {
02097     /* Set the Update Disable Bit */
02098     TIMx->CR1 |= TIM_CR1_UDIS;
02099   }
02100   else
02101   {
02102     /* Reset the Update Disable Bit */
02103     TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
02104   }
02105 }
02106 
02107 /**
02108   * @brief  Configures the TIMx Update Request Interrupt source.
02109   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
02110   * @param  TIM_UpdateSource: specifies the Update source.
02111   *   This parameter can be one of the following values:
02112   *     @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
02113                                        or the setting of UG bit, or an update generation
02114                                        through the slave mode controller.
02115   *     @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
02116   * @retval None
02117   */
02118 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
02119 {
02120   /* Check the parameters */
02121   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02122   assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
02123   if (TIM_UpdateSource != TIM_UpdateSource_Global)
02124   {
02125     /* Set the URS Bit */
02126     TIMx->CR1 |= TIM_CR1_URS;
02127   }
02128   else
02129   {
02130     /* Reset the URS Bit */
02131     TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
02132   }
02133 }
02134 
02135 /**
02136   * @brief  Enables or disables the TIMx’s Hall sensor interface.
02137   * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
02138   * @param  NewState: new state of the TIMx Hall sensor interface.
02139   *   This parameter can be: ENABLE or DISABLE.
02140   * @retval None
02141   */
02142 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
02143 {
02144   /* Check the parameters */
02145   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
02146   assert_param(IS_FUNCTIONAL_STATE(NewState));
02147   if (NewState != DISABLE)
02148   {
02149     /* Set the TI1S Bit */
02150     TIMx->CR2 |= TIM_CR2_TI1S;
02151   }
02152   else
02153   {
02154     /* Reset the TI1S Bit */
02155     TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
02156   }
02157 }
02158 
02159 /**
02160   * @brief  Selects the TIMx’s One Pulse Mode.
02161   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
02162   * @param  TIM_OPMode: specifies the OPM Mode to be used.
02163   *   This parameter can be one of the following values:
02164   *     @arg TIM_OPMode_Single
02165   *     @arg TIM_OPMode_Repetitive
02166   * @retval None
02167   */
02168 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
02169 {
02170   /* Check the parameters */
02171   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02172   assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
02173   /* Reset the OPM Bit */
02174   TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
02175   /* Configure the OPM Mode */
02176   TIMx->CR1 |= TIM_OPMode;
02177 }
02178 
02179 /**
02180   * @brief  Selects the TIMx Trigger Output Mode.
02181   * @param  TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral.
02182   * @param  TIM_TRGOSource: specifies the Trigger Output source.
02183   *   This paramter can be one of the following values:
02184   *
02185   *  - For all TIMx
02186   *     @arg TIM_TRGOSource_Reset:  The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
02187   *     @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
02188   *     @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
02189   *
02190   *  - For all TIMx except TIM6 and TIM7
02191   *     @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
02192   *                              is to be set, as soon as a capture or compare match occurs (TRGO).
02193   *     @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
02194   *     @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
02195   *     @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
02196   *     @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
02197   *
02198   * @retval None
02199   */
02200 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
02201 {
02202   /* Check the parameters */
02203   assert_param(IS_TIM_LIST7_PERIPH(TIMx));
02204   assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
02205   /* Reset the MMS Bits */
02206   TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
02207   /* Select the TRGO source */
02208   TIMx->CR2 |=  TIM_TRGOSource;
02209 }
02210 
02211 /**
02212   * @brief  Selects the TIMx Slave Mode.
02213   * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
02214   * @param  TIM_SlaveMode: specifies the Timer Slave Mode.
02215   *   This paramter can be one of the following values:
02216   *     @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
02217   *                               the counter and triggers an update of the registers.
02218   *     @arg TIM_SlaveMode_Gated:     The counter clock is enabled when the trigger signal (TRGI) is high.
02219   *     @arg TIM_SlaveMode_Trigger:   The counter starts at a rising edge of the trigger TRGI.
02220   *     @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
02221   * @retval None
02222   */
02223 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
02224 {
02225   /* Check the parameters */
02226   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
02227   assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
02228  /* Reset the SMS Bits */
02229   TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
02230   /* Select the Slave Mode */
02231   TIMx->SMCR |= TIM_SlaveMode;
02232 }
02233 
02234 /**
02235   * @brief  Sets or Resets the TIMx Master/Slave Mode.
02236   * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
02237   * @param  TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
02238   *   This paramter can be one of the following values:
02239   *     @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
02240   *                                      and its slaves (through TRGO).
02241   *     @arg TIM_MasterSlaveMode_Disable: No action
02242   * @retval None
02243   */
02244 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
02245 {
02246   /* Check the parameters */
02247   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
02248   assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
02249   /* Reset the MSM Bit */
02250   TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
02251   
02252   /* Set or Reset the MSM Bit */
02253   TIMx->SMCR |= TIM_MasterSlaveMode;
02254 }
02255 
02256 /**
02257   * @brief  Sets the TIMx Counter Register value
02258   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
02259   * @param  Counter: specifies the Counter register new value.
02260   * @retval None
02261   */
02262 void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)
02263 {
02264   /* Check the parameters */
02265   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02266   /* Set the Counter Register value */
02267   TIMx->CNT = Counter;
02268 }
02269 
02270 /**
02271   * @brief  Sets the TIMx Autoreload Register value
02272   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
02273   * @param  Autoreload: specifies the Autoreload register new value.
02274   * @retval None
02275   */
02276 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)
02277 {
02278   /* Check the parameters */
02279   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02280   /* Set the Autoreload Register value */
02281   TIMx->ARR = Autoreload;
02282 }
02283 
02284 /**
02285   * @brief  Sets the TIMx Capture Compare1 Register value
02286   * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
02287   * @param  Compare1: specifies the Capture Compare1 register new value.
02288   * @retval None
02289   */
02290 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)
02291 {
02292   /* Check the parameters */
02293   assert_param(IS_TIM_LIST8_PERIPH(TIMx));
02294   /* Set the Capture Compare1 Register value */
02295   TIMx->CCR1 = Compare1;
02296 }
02297 
02298 /**
02299   * @brief  Sets the TIMx Capture Compare2 Register value
02300   * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
02301   * @param  Compare2: specifies the Capture Compare2 register new value.
02302   * @retval None
02303   */
02304 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)
02305 {
02306   /* Check the parameters */
02307   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
02308   /* Set the Capture Compare2 Register value */
02309   TIMx->CCR2 = Compare2;
02310 }
02311 
02312 /**
02313   * @brief  Sets the TIMx Capture Compare3 Register value
02314   * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
02315   * @param  Compare3: specifies the Capture Compare3 register new value.
02316   * @retval None
02317   */
02318 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)
02319 {
02320   /* Check the parameters */
02321   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
02322   /* Set the Capture Compare3 Register value */
02323   TIMx->CCR3 = Compare3;
02324 }
02325 
02326 /**
02327   * @brief  Sets the TIMx Capture Compare4 Register value
02328   * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
02329   * @param  Compare4: specifies the Capture Compare4 register new value.
02330   * @retval None
02331   */
02332 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)
02333 {
02334   /* Check the parameters */
02335   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
02336   /* Set the Capture Compare4 Register value */
02337   TIMx->CCR4 = Compare4;
02338 }
02339 
02340 /**
02341   * @brief  Sets the TIMx Input Capture 1 prescaler.
02342   * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
02343   * @param  TIM_ICPSC: specifies the Input Capture1 prescaler new value.
02344   *   This parameter can be one of the following values:
02345   *     @arg TIM_ICPSC_DIV1: no prescaler
02346   *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
02347   *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
02348   *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
02349   * @retval None
02350   */
02351 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
02352 {
02353   /* Check the parameters */
02354   assert_param(IS_TIM_LIST8_PERIPH(TIMx));
02355   assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
02356   /* Reset the IC1PSC Bits */
02357   TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
02358   /* Set the IC1PSC value */
02359   TIMx->CCMR1 |= TIM_ICPSC;
02360 }
02361 
02362 /**
02363   * @brief  Sets the TIMx Input Capture 2 prescaler.
02364   * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
02365   * @param  TIM_ICPSC: specifies the Input Capture2 prescaler new value.
02366   *   This parameter can be one of the following values:
02367   *     @arg TIM_ICPSC_DIV1: no prescaler
02368   *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
02369   *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
02370   *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
02371   * @retval None
02372   */
02373 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
02374 {
02375   /* Check the parameters */
02376   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
02377   assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
02378   /* Reset the IC2PSC Bits */
02379   TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
02380   /* Set the IC2PSC value */
02381   TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
02382 }
02383 
02384 /**
02385   * @brief  Sets the TIMx Input Capture 3 prescaler.
02386   * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
02387   * @param  TIM_ICPSC: specifies the Input Capture3 prescaler new value.
02388   *   This parameter can be one of the following values:
02389   *     @arg TIM_ICPSC_DIV1: no prescaler
02390   *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
02391   *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
02392   *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
02393   * @retval None
02394   */
02395 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
02396 {
02397   /* Check the parameters */
02398   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
02399   assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
02400   /* Reset the IC3PSC Bits */
02401   TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
02402   /* Set the IC3PSC value */
02403   TIMx->CCMR2 |= TIM_ICPSC;
02404 }
02405 
02406 /**
02407   * @brief  Sets the TIMx Input Capture 4 prescaler.
02408   * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
02409   * @param  TIM_ICPSC: specifies the Input Capture4 prescaler new value.
02410   *   This parameter can be one of the following values:
02411   *     @arg TIM_ICPSC_DIV1: no prescaler
02412   *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
02413   *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
02414   *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
02415   * @retval None
02416   */
02417 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
02418 {  
02419   /* Check the parameters */
02420   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
02421   assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
02422   /* Reset the IC4PSC Bits */
02423   TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
02424   /* Set the IC4PSC value */
02425   TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
02426 }
02427 
02428 /**
02429   * @brief  Sets the TIMx Clock Division value.
02430   * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select 
02431   *   the TIM peripheral.
02432   * @param  TIM_CKD: specifies the clock division value.
02433   *   This parameter can be one of the following value:
02434   *     @arg TIM_CKD_DIV1: TDTS = Tck_tim
02435   *     @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
02436   *     @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
02437   * @retval None
02438   */
02439 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
02440 {
02441   /* Check the parameters */
02442   assert_param(IS_TIM_LIST8_PERIPH(TIMx));
02443   assert_param(IS_TIM_CKD_DIV(TIM_CKD));
02444   /* Reset the CKD Bits */
02445   TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
02446   /* Set the CKD value */
02447   TIMx->CR1 |= TIM_CKD;
02448 }
02449 
02450 /**
02451   * @brief  Gets the TIMx Input Capture 1 value.
02452   * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
02453   * @retval Capture Compare 1 Register value.
02454   */
02455 uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)
02456 {
02457   /* Check the parameters */
02458   assert_param(IS_TIM_LIST8_PERIPH(TIMx));
02459   /* Get the Capture 1 Register value */
02460   return TIMx->CCR1;
02461 }
02462 
02463 /**
02464   * @brief  Gets the TIMx Input Capture 2 value.
02465   * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
02466   * @retval Capture Compare 2 Register value.
02467   */
02468 uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)
02469 {
02470   /* Check the parameters */
02471   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
02472   /* Get the Capture 2 Register value */
02473   return TIMx->CCR2;
02474 }
02475 
02476 /**
02477   * @brief  Gets the TIMx Input Capture 3 value.
02478   * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
02479   * @retval Capture Compare 3 Register value.
02480   */
02481 uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)
02482 {
02483   /* Check the parameters */
02484   assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
02485   /* Get the Capture 3 Register value */
02486   return TIMx->CCR3;
02487 }
02488 
02489 /**
02490   * @brief  Gets the TIMx Input Capture 4 value.
02491   * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
02492   * @retval Capture Compare 4 Register value.
02493   */
02494 uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)
02495 {
02496   /* Check the parameters */
02497   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
02498   /* Get the Capture 4 Register value */
02499   return TIMx->CCR4;
02500 }
02501 
02502 /**
02503   * @brief  Gets the TIMx Counter value.
02504   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
02505   * @retval Counter Register value.
02506   */
02507 uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)
02508 {
02509   /* Check the parameters */
02510   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02511   /* Get the Counter Register value */
02512   return TIMx->CNT;
02513 }
02514 
02515 /**
02516   * @brief  Gets the TIMx Prescaler value.
02517   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
02518   * @retval Prescaler Register value.
02519   */
02520 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
02521 {
02522   /* Check the parameters */
02523   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02524   /* Get the Prescaler Register value */
02525   return TIMx->PSC;
02526 }
02527 
02528 /**
02529   * @brief  Checks whether the specified TIM flag is set or not.
02530   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
02531   * @param  TIM_FLAG: specifies the flag to check.
02532   *   This parameter can be one of the following values:
02533   *     @arg TIM_FLAG_Update: TIM update Flag
02534   *     @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
02535   *     @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
02536   *     @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
02537   *     @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
02538   *     @arg TIM_FLAG_COM: TIM Commutation Flag
02539   *     @arg TIM_FLAG_Trigger: TIM Trigger Flag
02540   *     @arg TIM_FLAG_Break: TIM Break Flag
02541   *     @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
02542   *     @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
02543   *     @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
02544   *     @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
02545   * @note
02546   *   - TIM6 and TIM7 can have only one update flag. 
02547   *   - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
02548   *      TIM_FLAG_CC2 or TIM_FLAG_Trigger. 
02549   *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.   
02550   *   - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. 
02551   *   - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.    
02552   * @retval The new state of TIM_FLAG (SET or RESET).
02553   */
02554 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
02555 { 
02556   ITStatus bitstatus = RESET;  
02557   /* Check the parameters */
02558   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02559   assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
02560   
02561   if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
02562   {
02563     bitstatus = SET;
02564   }
02565   else
02566   {
02567     bitstatus = RESET;
02568   }
02569   return bitstatus;
02570 }
02571 
02572 /**
02573   * @brief  Clears the TIMx's pending flags.
02574   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
02575   * @param  TIM_FLAG: specifies the flag bit to clear.
02576   *   This parameter can be any combination of the following values:
02577   *     @arg TIM_FLAG_Update: TIM update Flag
02578   *     @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
02579   *     @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
02580   *     @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
02581   *     @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
02582   *     @arg TIM_FLAG_COM: TIM Commutation Flag
02583   *     @arg TIM_FLAG_Trigger: TIM Trigger Flag
02584   *     @arg TIM_FLAG_Break: TIM Break Flag
02585   *     @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
02586   *     @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
02587   *     @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
02588   *     @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
02589   * @note
02590   *   - TIM6 and TIM7 can have only one update flag. 
02591   *   - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
02592   *      TIM_FLAG_CC2 or TIM_FLAG_Trigger. 
02593   *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.   
02594   *   - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. 
02595   *   - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.   
02596   * @retval None
02597   */
02598 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
02599 {  
02600   /* Check the parameters */
02601   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02602   assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
02603    
02604   /* Clear the flags */
02605   TIMx->SR = (uint16_t)~TIM_FLAG;
02606 }
02607 
02608 /**
02609   * @brief  Checks whether the TIM interrupt has occurred or not.
02610   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
02611   * @param  TIM_IT: specifies the TIM interrupt source to check.
02612   *   This parameter can be one of the following values:
02613   *     @arg TIM_IT_Update: TIM update Interrupt source
02614   *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
02615   *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
02616   *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
02617   *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
02618   *     @arg TIM_IT_COM: TIM Commutation Interrupt source
02619   *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
02620   *     @arg TIM_IT_Break: TIM Break Interrupt source
02621   * @note
02622   *   - TIM6 and TIM7 can generate only an update interrupt.
02623   *   - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
02624   *      TIM_IT_CC2 or TIM_IT_Trigger. 
02625   *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.   
02626   *   - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. 
02627   *   - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.  
02628   * @retval The new state of the TIM_IT(SET or RESET).
02629   */
02630 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
02631 {
02632   ITStatus bitstatus = RESET;  
02633   uint16_t itstatus = 0x0, itenable = 0x0;
02634   /* Check the parameters */
02635   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02636   assert_param(IS_TIM_GET_IT(TIM_IT));
02637    
02638   itstatus = TIMx->SR & TIM_IT;
02639   
02640   itenable = TIMx->DIER & TIM_IT;
02641   if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
02642   {
02643     bitstatus = SET;
02644   }
02645   else
02646   {
02647     bitstatus = RESET;
02648   }
02649   return bitstatus;
02650 }
02651 
02652 /**
02653   * @brief  Clears the TIMx's interrupt pending bits.
02654   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
02655   * @param  TIM_IT: specifies the pending bit to clear.
02656   *   This parameter can be any combination of the following values:
02657   *     @arg TIM_IT_Update: TIM1 update Interrupt source
02658   *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
02659   *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
02660   *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
02661   *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
02662   *     @arg TIM_IT_COM: TIM Commutation Interrupt source
02663   *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
02664   *     @arg TIM_IT_Break: TIM Break Interrupt source
02665   * @note
02666   *   - TIM6 and TIM7 can generate only an update interrupt.
02667   *   - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
02668   *      TIM_IT_CC2 or TIM_IT_Trigger. 
02669   *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.   
02670   *   - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. 
02671   *   - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.    
02672   * @retval None
02673   */
02674 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
02675 {
02676   /* Check the parameters */
02677   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02678   assert_param(IS_TIM_IT(TIM_IT));
02679   /* Clear the IT pending Bit */
02680   TIMx->SR = (uint16_t)~TIM_IT;
02681 }
02682 
02683 /**
02684   * @brief  Configure the TI1 as Input.
02685   * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
02686   * @param  TIM_ICPolarity : The Input Polarity.
02687   *   This parameter can be one of the following values:
02688   *     @arg TIM_ICPolarity_Rising
02689   *     @arg TIM_ICPolarity_Falling
02690   * @param  TIM_ICSelection: specifies the input to be used.
02691   *   This parameter can be one of the following values:
02692   *     @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
02693   *     @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
02694   *     @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
02695   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
02696   *   This parameter must be a value between 0x00 and 0x0F.
02697   * @retval None
02698   */
02699 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
02700                        uint16_t TIM_ICFilter)
02701 {
02702   uint16_t tmpccmr1 = 0, tmpccer = 0;
02703   /* Disable the Channel 1: Reset the CC1E Bit */
02704   TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
02705   tmpccmr1 = TIMx->CCMR1;
02706   tmpccer = TIMx->CCER;
02707   /* Select the Input and set the filter */
02708   tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
02709   tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
02710   
02711   if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
02712      (TIMx == TIM4) ||(TIMx == TIM5))
02713   {
02714     /* Select the Polarity and set the CC1E Bit */
02715     tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P));
02716     tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
02717   }
02718   else
02719   {
02720     /* Select the Polarity and set the CC1E Bit */
02721     tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
02722     tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
02723   }
02724 
02725   /* Write to TIMx CCMR1 and CCER registers */
02726   TIMx->CCMR1 = tmpccmr1;
02727   TIMx->CCER = tmpccer;
02728 }
02729 
02730 /**
02731   * @brief  Configure the TI2 as Input.
02732   * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
02733   * @param  TIM_ICPolarity : The Input Polarity.
02734   *   This parameter can be one of the following values:
02735   *     @arg TIM_ICPolarity_Rising
02736   *     @arg TIM_ICPolarity_Falling
02737   * @param  TIM_ICSelection: specifies the input to be used.
02738   *   This parameter can be one of the following values:
02739   *     @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
02740   *     @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
02741   *     @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
02742   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
02743   *   This parameter must be a value between 0x00 and 0x0F.
02744   * @retval None
02745   */
02746 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
02747                        uint16_t TIM_ICFilter)
02748 {
02749   uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
02750   /* Disable the Channel 2: Reset the CC2E Bit */
02751   TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
02752   tmpccmr1 = TIMx->CCMR1;
02753   tmpccer = TIMx->CCER;
02754   tmp = (uint16_t)(TIM_ICPolarity << 4);
02755   /* Select the Input and set the filter */
02756   tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
02757   tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
02758   tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
02759   
02760   if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
02761      (TIMx == TIM4) ||(TIMx == TIM5))
02762   {
02763     /* Select the Polarity and set the CC2E Bit */
02764     tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P));
02765     tmpccer |=  (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
02766   }
02767   else
02768   {
02769     /* Select the Polarity and set the CC2E Bit */
02770     tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
02771     tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E);
02772   }
02773   
02774   /* Write to TIMx CCMR1 and CCER registers */
02775   TIMx->CCMR1 = tmpccmr1 ;
02776   TIMx->CCER = tmpccer;
02777 }
02778 
02779 /**
02780   * @brief  Configure the TI3 as Input.
02781   * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
02782   * @param  TIM_ICPolarity : The Input Polarity.
02783   *   This parameter can be one of the following values:
02784   *     @arg TIM_ICPolarity_Rising
02785   *     @arg TIM_ICPolarity_Falling
02786   * @param  TIM_ICSelection: specifies the input to be used.
02787   *   This parameter can be one of the following values:
02788   *     @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
02789   *     @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
02790   *     @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
02791   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
02792   *   This parameter must be a value between 0x00 and 0x0F.
02793   * @retval None
02794   */
02795 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
02796                        uint16_t TIM_ICFilter)
02797 {
02798   uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
02799   /* Disable the Channel 3: Reset the CC3E Bit */
02800   TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
02801   tmpccmr2 = TIMx->CCMR2;
02802   tmpccer = TIMx->CCER;
02803   tmp = (uint16_t)(TIM_ICPolarity << 8);
02804   /* Select the Input and set the filter */
02805   tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
02806   tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
02807     
02808   if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
02809      (TIMx == TIM4) ||(TIMx == TIM5))
02810   {
02811     /* Select the Polarity and set the CC3E Bit */
02812     tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P));
02813     tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
02814   }
02815   else
02816   {
02817     /* Select the Polarity and set the CC3E Bit */
02818     tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
02819     tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E);
02820   }
02821   
02822   /* Write to TIMx CCMR2 and CCER registers */
02823   TIMx->CCMR2 = tmpccmr2;
02824   TIMx->CCER = tmpccer;
02825 }
02826 
02827 /**
02828   * @brief  Configure the TI4 as Input.
02829   * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
02830   * @param  TIM_ICPolarity : The Input Polarity.
02831   *   This parameter can be one of the following values:
02832   *     @arg TIM_ICPolarity_Rising
02833   *     @arg TIM_ICPolarity_Falling
02834   * @param  TIM_ICSelection: specifies the input to be used.
02835   *   This parameter can be one of the following values:
02836   *     @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
02837   *     @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
02838   *     @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
02839   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
02840   *   This parameter must be a value between 0x00 and 0x0F.
02841   * @retval None
02842   */
02843 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
02844                        uint16_t TIM_ICFilter)
02845 {
02846   uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
02847 
02848    /* Disable the Channel 4: Reset the CC4E Bit */
02849   TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
02850   tmpccmr2 = TIMx->CCMR2;
02851   tmpccer = TIMx->CCER;
02852   tmp = (uint16_t)(TIM_ICPolarity << 12);
02853   /* Select the Input and set the filter */
02854   tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
02855   tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
02856   tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
02857   
02858   if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
02859      (TIMx == TIM4) ||(TIMx == TIM5))
02860   {
02861     /* Select the Polarity and set the CC4E Bit */
02862     tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P));
02863     tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
02864   }
02865   else
02866   {
02867     /* Select the Polarity and set the CC4E Bit */
02868     tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP));
02869     tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E);
02870   }
02871   /* Write to TIMx CCMR2 and CCER registers */
02872   TIMx->CCMR2 = tmpccmr2;
02873   TIMx->CCER = tmpccer;
02874 }
02875 
02876 /**
02877   * @}
02878   */
02879 
02880 /**
02881   * @}
02882   */
02883 
02884 /**
02885   * @}
02886   */
02887 
02888 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
STM32F10x Standard Peripherals Library: Footer

 

 

 

      For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit  www.st.com/STM32