stm32f10x_spi.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_spi.c
00004   * @author  MCD Application Team
00005   * @version V3.4.0
00006   * @date    10/15/2010
00007   * @brief   This file provides all the SPI firmware functions.
00008   ******************************************************************************
00009   * @copy
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
00019   */ 
00020 
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32f10x_spi.h"
00023 #include "stm32f10x_rcc.h"
00024 
00025 /** @addtogroup STM32F10x_StdPeriph_Driver
00026   * @{
00027   */
00028 
00029 /** @defgroup SPI 
00030   * @brief SPI driver modules
00031   * @{
00032   */ 
00033 
00034 /** @defgroup SPI_Private_TypesDefinitions
00035   * @{
00036   */
00037 
00038 /**
00039   * @}
00040   */ 
00041 
00042 
00043 /** @defgroup SPI_Private_Defines
00044   * @{
00045   */
00046 
00047 /* SPI SPE mask */
00048 #define CR1_SPE_Set          ((uint16_t)0x0040)
00049 #define CR1_SPE_Reset        ((uint16_t)0xFFBF)
00050 
00051 /* I2S I2SE mask */
00052 #define I2SCFGR_I2SE_Set     ((uint16_t)0x0400)
00053 #define I2SCFGR_I2SE_Reset   ((uint16_t)0xFBFF)
00054 
00055 /* SPI CRCNext mask */
00056 #define CR1_CRCNext_Set      ((uint16_t)0x1000)
00057 
00058 /* SPI CRCEN mask */
00059 #define CR1_CRCEN_Set        ((uint16_t)0x2000)
00060 #define CR1_CRCEN_Reset      ((uint16_t)0xDFFF)
00061 
00062 /* SPI SSOE mask */
00063 #define CR2_SSOE_Set         ((uint16_t)0x0004)
00064 #define CR2_SSOE_Reset       ((uint16_t)0xFFFB)
00065 
00066 /* SPI registers Masks */
00067 #define CR1_CLEAR_Mask       ((uint16_t)0x3040)
00068 #define I2SCFGR_CLEAR_Mask   ((uint16_t)0xF040)
00069 
00070 /* SPI or I2S mode selection masks */
00071 #define SPI_Mode_Select      ((uint16_t)0xF7FF)
00072 #define I2S_Mode_Select      ((uint16_t)0x0800) 
00073 
00074 /* I2S clock source selection masks */
00075 #define I2S2_CLOCK_SRC       ((uint32_t)(0x00020000))
00076 #define I2S3_CLOCK_SRC       ((uint32_t)(0x00040000))
00077 #define I2S_MUL_MASK         ((uint32_t)(0x0000F000))
00078 #define I2S_DIV_MASK         ((uint32_t)(0x000000F0))
00079 
00080 /**
00081   * @}
00082   */
00083 
00084 /** @defgroup SPI_Private_Macros
00085   * @{
00086   */
00087 
00088 /**
00089   * @}
00090   */
00091 
00092 /** @defgroup SPI_Private_Variables
00093   * @{
00094   */
00095 
00096 /**
00097   * @}
00098   */
00099 
00100 /** @defgroup SPI_Private_FunctionPrototypes
00101   * @{
00102   */
00103 
00104 /**
00105   * @}
00106   */
00107 
00108 /** @defgroup SPI_Private_Functions
00109   * @{
00110   */
00111 
00112 /**
00113   * @brief  Deinitializes the SPIx peripheral registers to their default
00114   *   reset values (Affects also the I2Ss).
00115   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00116   * @retval None
00117   */
00118 void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
00119 {
00120   /* Check the parameters */
00121   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00122 
00123   if (SPIx == SPI1)
00124   {
00125     /* Enable SPI1 reset state */
00126     RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
00127     /* Release SPI1 from reset state */
00128     RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
00129   }
00130   else if (SPIx == SPI2)
00131   {
00132     /* Enable SPI2 reset state */
00133     RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
00134     /* Release SPI2 from reset state */
00135     RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
00136   }
00137   else
00138   {
00139     if (SPIx == SPI3)
00140     {
00141       /* Enable SPI3 reset state */
00142       RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
00143       /* Release SPI3 from reset state */
00144       RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
00145     }
00146   }
00147 }
00148 
00149 /**
00150   * @brief  Initializes the SPIx peripheral according to the specified 
00151   *   parameters in the SPI_InitStruct.
00152   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00153   * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
00154   *   contains the configuration information for the specified SPI peripheral.
00155   * @retval None
00156   */
00157 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
00158 {
00159   uint16_t tmpreg = 0;
00160   
00161   /* check the parameters */
00162   assert_param(IS_SPI_ALL_PERIPH(SPIx));   
00163   
00164   /* Check the SPI parameters */
00165   assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
00166   assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
00167   assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
00168   assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
00169   assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
00170   assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
00171   assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
00172   assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
00173   assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
00174 
00175 /*---------------------------- SPIx CR1 Configuration ------------------------*/
00176   /* Get the SPIx CR1 value */
00177   tmpreg = SPIx->CR1;
00178   /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
00179   tmpreg &= CR1_CLEAR_Mask;
00180   /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
00181      master/salve mode, CPOL and CPHA */
00182   /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
00183   /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
00184   /* Set LSBFirst bit according to SPI_FirstBit value */
00185   /* Set BR bits according to SPI_BaudRatePrescaler value */
00186   /* Set CPOL bit according to SPI_CPOL value */
00187   /* Set CPHA bit according to SPI_CPHA value */
00188   tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
00189                   SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |  
00190                   SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |  
00191                   SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
00192   /* Write to SPIx CR1 */
00193   SPIx->CR1 = tmpreg;
00194   
00195   /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
00196   SPIx->I2SCFGR &= SPI_Mode_Select;             
00197 
00198 /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
00199   /* Write to SPIx CRCPOLY */
00200   SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
00201 }
00202 
00203 /**
00204   * @brief  Initializes the SPIx peripheral according to the specified 
00205   *   parameters in the I2S_InitStruct.
00206   * @param  SPIx: where x can be  2 or 3 to select the SPI peripheral
00207   *   (configured in I2S mode).
00208   * @param  I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
00209   *   contains the configuration information for the specified SPI peripheral
00210   *   configured in I2S mode.
00211   * @note
00212   *  The function calculates the optimal prescaler needed to obtain the most 
00213   *  accurate audio frequency (depending on the I2S clock source, the PLL values 
00214   *  and the product configuration). But in case the prescaler value is greater 
00215   *  than 511, the default value (0x02) will be configured instead.  *   
00216   * @retval None
00217   */
00218 void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
00219 {
00220   uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
00221   uint32_t tmp = 0;
00222   RCC_ClocksTypeDef RCC_Clocks;
00223   uint32_t sourceclock = 0;
00224   
00225   /* Check the I2S parameters */
00226   assert_param(IS_SPI_23_PERIPH(SPIx));
00227   assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
00228   assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
00229   assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
00230   assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
00231   assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
00232   assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));  
00233 
00234 /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
00235   /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
00236   SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; 
00237   SPIx->I2SPR = 0x0002;
00238   
00239   /* Get the I2SCFGR register value */
00240   tmpreg = SPIx->I2SCFGR;
00241   
00242   /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
00243   if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
00244   {
00245     i2sodd = (uint16_t)0;
00246     i2sdiv = (uint16_t)2;   
00247   }
00248   /* If the requested audio frequency is not the default, compute the prescaler */
00249   else
00250   {
00251     /* Check the frame length (For the Prescaler computing) */
00252     if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
00253     {
00254       /* Packet length is 16 bits */
00255       packetlength = 1;
00256     }
00257     else
00258     {
00259       /* Packet length is 32 bits */
00260       packetlength = 2;
00261     }
00262 
00263     /* Get the I2S clock source mask depending on the peripheral number */
00264     if(((uint32_t)SPIx) == SPI2_BASE)
00265     {
00266       /* The mask is relative to I2S2 */
00267       tmp = I2S2_CLOCK_SRC;
00268     }
00269     else 
00270     {
00271       /* The mask is relative to I2S3 */      
00272       tmp = I2S3_CLOCK_SRC;
00273     }
00274 
00275     /* Check the I2S clock source configuration depending on the Device:
00276        Only Connectivity line devices have the PLL3 VCO clock */
00277 #ifdef STM32F10X_CL
00278     if((RCC->CFGR2 & tmp) != 0)
00279     {
00280       /* Get the configuration bits of RCC PLL3 multiplier */
00281       tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12);
00282 
00283       /* Get the value of the PLL3 multiplier */      
00284       if((tmp > 5) && (tmp < 15))
00285       {
00286         /* Multplier is between 8 and 14 (value 15 is forbidden) */
00287         tmp += 2;
00288       }
00289       else
00290       {
00291         if (tmp == 15)
00292         {
00293           /* Multiplier is 20 */
00294           tmp = 20;
00295         }
00296       }      
00297       /* Get the PREDIV2 value */
00298       sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1);
00299       
00300       /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */
00301       sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2); 
00302     }
00303     else
00304     {
00305       /* I2S Clock source is System clock: Get System Clock frequency */
00306       RCC_GetClocksFreq(&RCC_Clocks);      
00307       
00308       /* Get the source clock value: based on System Clock value */
00309       sourceclock = RCC_Clocks.SYSCLK_Frequency;
00310     }        
00311 #else /* STM32F10X_HD */
00312     /* I2S Clock source is System clock: Get System Clock frequency */
00313     RCC_GetClocksFreq(&RCC_Clocks);      
00314       
00315     /* Get the source clock value: based on System Clock value */
00316     sourceclock = RCC_Clocks.SYSCLK_Frequency;    
00317 #endif /* STM32F10X_CL */    
00318 
00319     /* Compute the Real divider depending on the MCLK output state with a flaoting point */
00320     if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
00321     {
00322       /* MCLK output is enabled */
00323       tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
00324     }
00325     else
00326     {
00327       /* MCLK output is disabled */
00328       tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
00329     }
00330     
00331     /* Remove the flaoting point */
00332     tmp = tmp / 10;  
00333       
00334     /* Check the parity of the divider */
00335     i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
00336    
00337     /* Compute the i2sdiv prescaler */
00338     i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
00339    
00340     /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
00341     i2sodd = (uint16_t) (i2sodd << 8);
00342   }
00343   
00344   /* Test if the divider is 1 or 0 or greater than 0xFF */
00345   if ((i2sdiv < 2) || (i2sdiv > 0xFF))
00346   {
00347     /* Set the default values */
00348     i2sdiv = 2;
00349     i2sodd = 0;
00350   }
00351 
00352   /* Write to SPIx I2SPR register the computed value */
00353   SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));  
00354  
00355   /* Configure the I2S with the SPI_InitStruct values */
00356   tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \
00357                   (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
00358                   (uint16_t)I2S_InitStruct->I2S_CPOL))));
00359  
00360   /* Write to SPIx I2SCFGR */  
00361   SPIx->I2SCFGR = tmpreg;   
00362 }
00363 
00364 /**
00365   * @brief  Fills each SPI_InitStruct member with its default value.
00366   * @param  SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.
00367   * @retval None
00368   */
00369 void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
00370 {
00371 /*--------------- Reset SPI init structure parameters values -----------------*/
00372   /* Initialize the SPI_Direction member */
00373   SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
00374   /* initialize the SPI_Mode member */
00375   SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
00376   /* initialize the SPI_DataSize member */
00377   SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
00378   /* Initialize the SPI_CPOL member */
00379   SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
00380   /* Initialize the SPI_CPHA member */
00381   SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
00382   /* Initialize the SPI_NSS member */
00383   SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
00384   /* Initialize the SPI_BaudRatePrescaler member */
00385   SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
00386   /* Initialize the SPI_FirstBit member */
00387   SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
00388   /* Initialize the SPI_CRCPolynomial member */
00389   SPI_InitStruct->SPI_CRCPolynomial = 7;
00390 }
00391 
00392 /**
00393   * @brief  Fills each I2S_InitStruct member with its default value.
00394   * @param  I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.
00395   * @retval None
00396   */
00397 void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
00398 {
00399 /*--------------- Reset I2S init structure parameters values -----------------*/
00400   /* Initialize the I2S_Mode member */
00401   I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
00402   
00403   /* Initialize the I2S_Standard member */
00404   I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
00405   
00406   /* Initialize the I2S_DataFormat member */
00407   I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
00408   
00409   /* Initialize the I2S_MCLKOutput member */
00410   I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
00411   
00412   /* Initialize the I2S_AudioFreq member */
00413   I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
00414   
00415   /* Initialize the I2S_CPOL member */
00416   I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
00417 }
00418 
00419 /**
00420   * @brief  Enables or disables the specified SPI peripheral.
00421   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00422   * @param  NewState: new state of the SPIx peripheral. 
00423   *   This parameter can be: ENABLE or DISABLE.
00424   * @retval None
00425   */
00426 void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
00427 {
00428   /* Check the parameters */
00429   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00430   assert_param(IS_FUNCTIONAL_STATE(NewState));
00431   if (NewState != DISABLE)
00432   {
00433     /* Enable the selected SPI peripheral */
00434     SPIx->CR1 |= CR1_SPE_Set;
00435   }
00436   else
00437   {
00438     /* Disable the selected SPI peripheral */
00439     SPIx->CR1 &= CR1_SPE_Reset;
00440   }
00441 }
00442 
00443 /**
00444   * @brief  Enables or disables the specified SPI peripheral (in I2S mode).
00445   * @param  SPIx: where x can be 2 or 3 to select the SPI peripheral.
00446   * @param  NewState: new state of the SPIx peripheral. 
00447   *   This parameter can be: ENABLE or DISABLE.
00448   * @retval None
00449   */
00450 void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
00451 {
00452   /* Check the parameters */
00453   assert_param(IS_SPI_23_PERIPH(SPIx));
00454   assert_param(IS_FUNCTIONAL_STATE(NewState));
00455   if (NewState != DISABLE)
00456   {
00457     /* Enable the selected SPI peripheral (in I2S mode) */
00458     SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
00459   }
00460   else
00461   {
00462     /* Disable the selected SPI peripheral (in I2S mode) */
00463     SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
00464   }
00465 }
00466 
00467 /**
00468   * @brief  Enables or disables the specified SPI/I2S interrupts.
00469   * @param  SPIx: where x can be
00470   *   - 1, 2 or 3 in SPI mode 
00471   *   - 2 or 3 in I2S mode
00472   * @param  SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled. 
00473   *   This parameter can be one of the following values:
00474   *     @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
00475   *     @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
00476   *     @arg SPI_I2S_IT_ERR: Error interrupt mask
00477   * @param  NewState: new state of the specified SPI/I2S interrupt.
00478   *   This parameter can be: ENABLE or DISABLE.
00479   * @retval None
00480   */
00481 void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
00482 {
00483   uint16_t itpos = 0, itmask = 0 ;
00484   /* Check the parameters */
00485   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00486   assert_param(IS_FUNCTIONAL_STATE(NewState));
00487   assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
00488 
00489   /* Get the SPI/I2S IT index */
00490   itpos = SPI_I2S_IT >> 4;
00491 
00492   /* Set the IT mask */
00493   itmask = (uint16_t)1 << (uint16_t)itpos;
00494 
00495   if (NewState != DISABLE)
00496   {
00497     /* Enable the selected SPI/I2S interrupt */
00498     SPIx->CR2 |= itmask;
00499   }
00500   else
00501   {
00502     /* Disable the selected SPI/I2S interrupt */
00503     SPIx->CR2 &= (uint16_t)~itmask;
00504   }
00505 }
00506 
00507 /**
00508   * @brief  Enables or disables the SPIx/I2Sx DMA interface.
00509   * @param  SPIx: where x can be
00510   *   - 1, 2 or 3 in SPI mode 
00511   *   - 2 or 3 in I2S mode
00512   * @param  SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled. 
00513   *   This parameter can be any combination of the following values:
00514   *     @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
00515   *     @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
00516   * @param  NewState: new state of the selected SPI/I2S DMA transfer request.
00517   *   This parameter can be: ENABLE or DISABLE.
00518   * @retval None
00519   */
00520 void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
00521 {
00522   /* Check the parameters */
00523   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00524   assert_param(IS_FUNCTIONAL_STATE(NewState));
00525   assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
00526   if (NewState != DISABLE)
00527   {
00528     /* Enable the selected SPI/I2S DMA requests */
00529     SPIx->CR2 |= SPI_I2S_DMAReq;
00530   }
00531   else
00532   {
00533     /* Disable the selected SPI/I2S DMA requests */
00534     SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
00535   }
00536 }
00537 
00538 /**
00539   * @brief  Transmits a Data through the SPIx/I2Sx peripheral.
00540   * @param  SPIx: where x can be
00541   *   - 1, 2 or 3 in SPI mode 
00542   *   - 2 or 3 in I2S mode
00543   * @param  Data : Data to be transmitted.
00544   * @retval None
00545   */
00546 void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
00547 {
00548   /* Check the parameters */
00549   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00550   
00551   /* Write in the DR register the data to be sent */
00552   SPIx->DR = Data;
00553 }
00554 
00555 /**
00556   * @brief  Returns the most recent received data by the SPIx/I2Sx peripheral. 
00557   * @param  SPIx: where x can be
00558   *   - 1, 2 or 3 in SPI mode 
00559   *   - 2 or 3 in I2S mode
00560   * @retval The value of the received data.
00561   */
00562 uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
00563 {
00564   /* Check the parameters */
00565   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00566   
00567   /* Return the data in the DR register */
00568   return SPIx->DR;
00569 }
00570 
00571 /**
00572   * @brief  Configures internally by software the NSS pin for the selected SPI.
00573   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00574   * @param  SPI_NSSInternalSoft: specifies the SPI NSS internal state.
00575   *   This parameter can be one of the following values:
00576   *     @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
00577   *     @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
00578   * @retval None
00579   */
00580 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
00581 {
00582   /* Check the parameters */
00583   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00584   assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
00585   if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
00586   {
00587     /* Set NSS pin internally by software */
00588     SPIx->CR1 |= SPI_NSSInternalSoft_Set;
00589   }
00590   else
00591   {
00592     /* Reset NSS pin internally by software */
00593     SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
00594   }
00595 }
00596 
00597 /**
00598   * @brief  Enables or disables the SS output for the selected SPI.
00599   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00600   * @param  NewState: new state of the SPIx SS output. 
00601   *   This parameter can be: ENABLE or DISABLE.
00602   * @retval None
00603   */
00604 void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
00605 {
00606   /* Check the parameters */
00607   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00608   assert_param(IS_FUNCTIONAL_STATE(NewState));
00609   if (NewState != DISABLE)
00610   {
00611     /* Enable the selected SPI SS output */
00612     SPIx->CR2 |= CR2_SSOE_Set;
00613   }
00614   else
00615   {
00616     /* Disable the selected SPI SS output */
00617     SPIx->CR2 &= CR2_SSOE_Reset;
00618   }
00619 }
00620 
00621 /**
00622   * @brief  Configures the data size for the selected SPI.
00623   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00624   * @param  SPI_DataSize: specifies the SPI data size.
00625   *   This parameter can be one of the following values:
00626   *     @arg SPI_DataSize_16b: Set data frame format to 16bit
00627   *     @arg SPI_DataSize_8b: Set data frame format to 8bit
00628   * @retval None
00629   */
00630 void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
00631 {
00632   /* Check the parameters */
00633   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00634   assert_param(IS_SPI_DATASIZE(SPI_DataSize));
00635   /* Clear DFF bit */
00636   SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
00637   /* Set new DFF bit value */
00638   SPIx->CR1 |= SPI_DataSize;
00639 }
00640 
00641 /**
00642   * @brief  Transmit the SPIx CRC value.
00643   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00644   * @retval None
00645   */
00646 void SPI_TransmitCRC(SPI_TypeDef* SPIx)
00647 {
00648   /* Check the parameters */
00649   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00650   
00651   /* Enable the selected SPI CRC transmission */
00652   SPIx->CR1 |= CR1_CRCNext_Set;
00653 }
00654 
00655 /**
00656   * @brief  Enables or disables the CRC value calculation of the transfered bytes.
00657   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00658   * @param  NewState: new state of the SPIx CRC value calculation.
00659   *   This parameter can be: ENABLE or DISABLE.
00660   * @retval None
00661   */
00662 void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
00663 {
00664   /* Check the parameters */
00665   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00666   assert_param(IS_FUNCTIONAL_STATE(NewState));
00667   if (NewState != DISABLE)
00668   {
00669     /* Enable the selected SPI CRC calculation */
00670     SPIx->CR1 |= CR1_CRCEN_Set;
00671   }
00672   else
00673   {
00674     /* Disable the selected SPI CRC calculation */
00675     SPIx->CR1 &= CR1_CRCEN_Reset;
00676   }
00677 }
00678 
00679 /**
00680   * @brief  Returns the transmit or the receive CRC register value for the specified SPI.
00681   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00682   * @param  SPI_CRC: specifies the CRC register to be read.
00683   *   This parameter can be one of the following values:
00684   *     @arg SPI_CRC_Tx: Selects Tx CRC register
00685   *     @arg SPI_CRC_Rx: Selects Rx CRC register
00686   * @retval The selected CRC register value..
00687   */
00688 uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
00689 {
00690   uint16_t crcreg = 0;
00691   /* Check the parameters */
00692   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00693   assert_param(IS_SPI_CRC(SPI_CRC));
00694   if (SPI_CRC != SPI_CRC_Rx)
00695   {
00696     /* Get the Tx CRC register */
00697     crcreg = SPIx->TXCRCR;
00698   }
00699   else
00700   {
00701     /* Get the Rx CRC register */
00702     crcreg = SPIx->RXCRCR;
00703   }
00704   /* Return the selected CRC register */
00705   return crcreg;
00706 }
00707 
00708 /**
00709   * @brief  Returns the CRC Polynomial register value for the specified SPI.
00710   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00711   * @retval The CRC Polynomial register value.
00712   */
00713 uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
00714 {
00715   /* Check the parameters */
00716   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00717   
00718   /* Return the CRC polynomial register */
00719   return SPIx->CRCPR;
00720 }
00721 
00722 /**
00723   * @brief  Selects the data transfer direction in bi-directional mode for the specified SPI.
00724   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00725   * @param  SPI_Direction: specifies the data transfer direction in bi-directional mode. 
00726   *   This parameter can be one of the following values:
00727   *     @arg SPI_Direction_Tx: Selects Tx transmission direction
00728   *     @arg SPI_Direction_Rx: Selects Rx receive direction
00729   * @retval None
00730   */
00731 void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
00732 {
00733   /* Check the parameters */
00734   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00735   assert_param(IS_SPI_DIRECTION(SPI_Direction));
00736   if (SPI_Direction == SPI_Direction_Tx)
00737   {
00738     /* Set the Tx only mode */
00739     SPIx->CR1 |= SPI_Direction_Tx;
00740   }
00741   else
00742   {
00743     /* Set the Rx only mode */
00744     SPIx->CR1 &= SPI_Direction_Rx;
00745   }
00746 }
00747 
00748 /**
00749   * @brief  Checks whether the specified SPI/I2S flag is set or not.
00750   * @param  SPIx: where x can be
00751   *   - 1, 2 or 3 in SPI mode 
00752   *   - 2 or 3 in I2S mode
00753   * @param  SPI_I2S_FLAG: specifies the SPI/I2S flag to check. 
00754   *   This parameter can be one of the following values:
00755   *     @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
00756   *     @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
00757   *     @arg SPI_I2S_FLAG_BSY: Busy flag.
00758   *     @arg SPI_I2S_FLAG_OVR: Overrun flag.
00759   *     @arg SPI_FLAG_MODF: Mode Fault flag.
00760   *     @arg SPI_FLAG_CRCERR: CRC Error flag.
00761   *     @arg I2S_FLAG_UDR: Underrun Error flag.
00762   *     @arg I2S_FLAG_CHSIDE: Channel Side flag.
00763   * @retval The new state of SPI_I2S_FLAG (SET or RESET).
00764   */
00765 FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
00766 {
00767   FlagStatus bitstatus = RESET;
00768   /* Check the parameters */
00769   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00770   assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
00771   /* Check the status of the specified SPI/I2S flag */
00772   if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
00773   {
00774     /* SPI_I2S_FLAG is set */
00775     bitstatus = SET;
00776   }
00777   else
00778   {
00779     /* SPI_I2S_FLAG is reset */
00780     bitstatus = RESET;
00781   }
00782   /* Return the SPI_I2S_FLAG status */
00783   return  bitstatus;
00784 }
00785 
00786 /**
00787   * @brief  Clears the SPIx CRC Error (CRCERR) flag.
00788   * @param  SPIx: where x can be
00789   *   - 1, 2 or 3 in SPI mode 
00790   * @param  SPI_I2S_FLAG: specifies the SPI flag to clear. 
00791   *   This function clears only CRCERR flag.
00792   * @note
00793   *   - OVR (OverRun error) flag is cleared by software sequence: a read 
00794   *     operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read 
00795   *     operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
00796   *   - UDR (UnderRun error) flag is cleared by a read operation to 
00797   *     SPI_SR register (SPI_I2S_GetFlagStatus()).
00798   *   - MODF (Mode Fault) flag is cleared by software sequence: a read/write 
00799   *     operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a 
00800   *     write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
00801   * @retval None
00802   */
00803 void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
00804 {
00805   /* Check the parameters */
00806   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00807   assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
00808     
00809     /* Clear the selected SPI CRC Error (CRCERR) flag */
00810     SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
00811 }
00812 
00813 /**
00814   * @brief  Checks whether the specified SPI/I2S interrupt has occurred or not.
00815   * @param  SPIx: where x can be
00816   *   - 1, 2 or 3 in SPI mode 
00817   *   - 2 or 3 in I2S mode
00818   * @param  SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. 
00819   *   This parameter can be one of the following values:
00820   *     @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
00821   *     @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
00822   *     @arg SPI_I2S_IT_OVR: Overrun interrupt.
00823   *     @arg SPI_IT_MODF: Mode Fault interrupt.
00824   *     @arg SPI_IT_CRCERR: CRC Error interrupt.
00825   *     @arg I2S_IT_UDR: Underrun Error interrupt.
00826   * @retval The new state of SPI_I2S_IT (SET or RESET).
00827   */
00828 ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
00829 {
00830   ITStatus bitstatus = RESET;
00831   uint16_t itpos = 0, itmask = 0, enablestatus = 0;
00832 
00833   /* Check the parameters */
00834   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00835   assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
00836 
00837   /* Get the SPI/I2S IT index */
00838   itpos = 0x01 << (SPI_I2S_IT & 0x0F);
00839 
00840   /* Get the SPI/I2S IT mask */
00841   itmask = SPI_I2S_IT >> 4;
00842 
00843   /* Set the IT mask */
00844   itmask = 0x01 << itmask;
00845 
00846   /* Get the SPI_I2S_IT enable bit status */
00847   enablestatus = (SPIx->CR2 & itmask) ;
00848 
00849   /* Check the status of the specified SPI/I2S interrupt */
00850   if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
00851   {
00852     /* SPI_I2S_IT is set */
00853     bitstatus = SET;
00854   }
00855   else
00856   {
00857     /* SPI_I2S_IT is reset */
00858     bitstatus = RESET;
00859   }
00860   /* Return the SPI_I2S_IT status */
00861   return bitstatus;
00862 }
00863 
00864 /**
00865   * @brief  Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
00866   * @param  SPIx: where x can be
00867   *   - 1, 2 or 3 in SPI mode 
00868   * @param  SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
00869   *   This function clears only CRCERR intetrrupt pending bit.   
00870   * @note
00871   *   - OVR (OverRun Error) interrupt pending bit is cleared by software 
00872   *     sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) 
00873   *     followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
00874   *   - UDR (UnderRun Error) interrupt pending bit is cleared by a read 
00875   *     operation to SPI_SR register (SPI_I2S_GetITStatus()).
00876   *   - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
00877   *     a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) 
00878   *     followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable 
00879   *     the SPI).
00880   * @retval None
00881   */
00882 void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
00883 {
00884   uint16_t itpos = 0;
00885   /* Check the parameters */
00886   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00887   assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
00888 
00889   /* Get the SPI IT index */
00890   itpos = 0x01 << (SPI_I2S_IT & 0x0F);
00891 
00892   /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
00893   SPIx->SR = (uint16_t)~itpos;
00894 }
00895 /**
00896   * @}
00897   */ 
00898 
00899 /**
00900   * @}
00901   */ 
00902 
00903 /**
00904   * @}
00905   */ 
00906 
00907 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
STM32F10x Standard Peripherals Library: Footer

 

 

 

      For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit  www.st.com/STM32