stm32f10x_sdio.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_sdio.c
00004   * @author  MCD Application Team
00005   * @version V3.4.0
00006   * @date    10/15/2010
00007   * @brief   This file provides all the SDIO firmware functions.
00008   ******************************************************************************
00009   * @copy
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
00019   */ 
00020 
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32f10x_sdio.h"
00023 #include "stm32f10x_rcc.h"
00024 
00025 /** @addtogroup STM32F10x_StdPeriph_Driver
00026   * @{
00027   */
00028 
00029 /** @defgroup SDIO 
00030   * @brief SDIO driver modules
00031   * @{
00032   */ 
00033 
00034 /** @defgroup SDIO_Private_TypesDefinitions
00035   * @{
00036   */ 
00037 
00038 /* ------------ SDIO registers bit address in the alias region ----------- */
00039 #define SDIO_OFFSET                (SDIO_BASE - PERIPH_BASE)
00040 
00041 /* --- CLKCR Register ---*/
00042 
00043 /* Alias word address of CLKEN bit */
00044 #define CLKCR_OFFSET              (SDIO_OFFSET + 0x04)
00045 #define CLKEN_BitNumber           0x08
00046 #define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
00047 
00048 /* --- CMD Register ---*/
00049 
00050 /* Alias word address of SDIOSUSPEND bit */
00051 #define CMD_OFFSET                (SDIO_OFFSET + 0x0C)
00052 #define SDIOSUSPEND_BitNumber     0x0B
00053 #define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
00054 
00055 /* Alias word address of ENCMDCOMPL bit */
00056 #define ENCMDCOMPL_BitNumber      0x0C
00057 #define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
00058 
00059 /* Alias word address of NIEN bit */
00060 #define NIEN_BitNumber            0x0D
00061 #define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
00062 
00063 /* Alias word address of ATACMD bit */
00064 #define ATACMD_BitNumber          0x0E
00065 #define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
00066 
00067 /* --- DCTRL Register ---*/
00068 
00069 /* Alias word address of DMAEN bit */
00070 #define DCTRL_OFFSET              (SDIO_OFFSET + 0x2C)
00071 #define DMAEN_BitNumber           0x03
00072 #define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
00073 
00074 /* Alias word address of RWSTART bit */
00075 #define RWSTART_BitNumber         0x08
00076 #define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
00077 
00078 /* Alias word address of RWSTOP bit */
00079 #define RWSTOP_BitNumber          0x09
00080 #define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
00081 
00082 /* Alias word address of RWMOD bit */
00083 #define RWMOD_BitNumber           0x0A
00084 #define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
00085 
00086 /* Alias word address of SDIOEN bit */
00087 #define SDIOEN_BitNumber          0x0B
00088 #define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
00089 
00090 /* ---------------------- SDIO registers bit mask ------------------------ */
00091 
00092 /* --- CLKCR Register ---*/
00093 
00094 /* CLKCR register clear mask */
00095 #define CLKCR_CLEAR_MASK         ((uint32_t)0xFFFF8100) 
00096 
00097 /* --- PWRCTRL Register ---*/
00098 
00099 /* SDIO PWRCTRL Mask */
00100 #define PWR_PWRCTRL_MASK         ((uint32_t)0xFFFFFFFC)
00101 
00102 /* --- DCTRL Register ---*/
00103 
00104 /* SDIO DCTRL Clear Mask */
00105 #define DCTRL_CLEAR_MASK         ((uint32_t)0xFFFFFF08)
00106 
00107 /* --- CMD Register ---*/
00108 
00109 /* CMD Register clear mask */
00110 #define CMD_CLEAR_MASK           ((uint32_t)0xFFFFF800)
00111 
00112 /* SDIO RESP Registers Address */
00113 #define SDIO_RESP_ADDR           ((uint32_t)(SDIO_BASE + 0x14))
00114 
00115 /**
00116   * @}
00117   */
00118 
00119 /** @defgroup SDIO_Private_Defines
00120   * @{
00121   */
00122 
00123 /**
00124   * @}
00125   */
00126 
00127 /** @defgroup SDIO_Private_Macros
00128   * @{
00129   */
00130 
00131 /**
00132   * @}
00133   */
00134 
00135 /** @defgroup SDIO_Private_Variables
00136   * @{
00137   */
00138 
00139 /**
00140   * @}
00141   */
00142 
00143 /** @defgroup SDIO_Private_FunctionPrototypes
00144   * @{
00145   */
00146 
00147 /**
00148   * @}
00149   */
00150 
00151 /** @defgroup SDIO_Private_Functions
00152   * @{
00153   */
00154 
00155 /**
00156   * @brief  Deinitializes the SDIO peripheral registers to their default reset values.
00157   * @param  None
00158   * @retval None
00159   */
00160 void SDIO_DeInit(void)
00161 {
00162   SDIO->POWER = 0x00000000;
00163   SDIO->CLKCR = 0x00000000;
00164   SDIO->ARG = 0x00000000;
00165   SDIO->CMD = 0x00000000;
00166   SDIO->DTIMER = 0x00000000;
00167   SDIO->DLEN = 0x00000000;
00168   SDIO->DCTRL = 0x00000000;
00169   SDIO->ICR = 0x00C007FF;
00170   SDIO->MASK = 0x00000000;
00171 }
00172 
00173 /**
00174   * @brief  Initializes the SDIO peripheral according to the specified 
00175   *   parameters in the SDIO_InitStruct.
00176   * @param  SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure 
00177   *   that contains the configuration information for the SDIO peripheral.
00178   * @retval None
00179   */
00180 void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
00181 {
00182   uint32_t tmpreg = 0;
00183     
00184   /* Check the parameters */
00185   assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
00186   assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
00187   assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
00188   assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
00189   assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); 
00190    
00191 /*---------------------------- SDIO CLKCR Configuration ------------------------*/  
00192   /* Get the SDIO CLKCR value */
00193   tmpreg = SDIO->CLKCR;
00194   
00195   /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
00196   tmpreg &= CLKCR_CLEAR_MASK;
00197   
00198   /* Set CLKDIV bits according to SDIO_ClockDiv value */
00199   /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
00200   /* Set BYPASS bit according to SDIO_ClockBypass value */
00201   /* Set WIDBUS bits according to SDIO_BusWide value */
00202   /* Set NEGEDGE bits according to SDIO_ClockEdge value */
00203   /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
00204   tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv  | SDIO_InitStruct->SDIO_ClockPowerSave |
00205              SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
00206              SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); 
00207   
00208   /* Write to SDIO CLKCR */
00209   SDIO->CLKCR = tmpreg;
00210 }
00211 
00212 /**
00213   * @brief  Fills each SDIO_InitStruct member with its default value.
00214   * @param  SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which 
00215   *   will be initialized.
00216   * @retval None
00217   */
00218 void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
00219 {
00220   /* SDIO_InitStruct members default value */
00221   SDIO_InitStruct->SDIO_ClockDiv = 0x00;
00222   SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
00223   SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
00224   SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
00225   SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
00226   SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
00227 }
00228 
00229 /**
00230   * @brief  Enables or disables the SDIO Clock.
00231   * @param  NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
00232   * @retval None
00233   */
00234 void SDIO_ClockCmd(FunctionalState NewState)
00235 {
00236   /* Check the parameters */
00237   assert_param(IS_FUNCTIONAL_STATE(NewState));
00238   
00239   *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
00240 }
00241 
00242 /**
00243   * @brief  Sets the power status of the controller.
00244   * @param  SDIO_PowerState: new state of the Power state. 
00245   *   This parameter can be one of the following values:
00246   *     @arg SDIO_PowerState_OFF
00247   *     @arg SDIO_PowerState_ON
00248   * @retval None
00249   */
00250 void SDIO_SetPowerState(uint32_t SDIO_PowerState)
00251 {
00252   /* Check the parameters */
00253   assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
00254   
00255   SDIO->POWER &= PWR_PWRCTRL_MASK;
00256   SDIO->POWER |= SDIO_PowerState;
00257 }
00258 
00259 /**
00260   * @brief  Gets the power status of the controller.
00261   * @param  None
00262   * @retval Power status of the controller. The returned value can
00263   *   be one of the following:
00264   * - 0x00: Power OFF
00265   * - 0x02: Power UP
00266   * - 0x03: Power ON 
00267   */
00268 uint32_t SDIO_GetPowerState(void)
00269 {
00270   return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
00271 }
00272 
00273 /**
00274   * @brief  Enables or disables the SDIO interrupts.
00275   * @param  SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
00276   *   This parameter can be one or a combination of the following values:
00277   *     @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00278   *     @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00279   *     @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
00280   *     @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
00281   *     @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00282   *     @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
00283   *     @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
00284   *     @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
00285   *     @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
00286   *     @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
00287   *                            bus mode interrupt
00288   *     @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
00289   *     @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
00290   *     @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
00291   *     @arg SDIO_IT_RXACT:    Data receive in progress interrupt
00292   *     @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
00293   *     @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
00294   *     @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
00295   *     @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
00296   *     @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
00297   *     @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
00298   *     @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
00299   *     @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
00300   *     @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
00301   *     @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
00302   * @param  NewState: new state of the specified SDIO interrupts.
00303   *   This parameter can be: ENABLE or DISABLE.
00304   * @retval None 
00305   */
00306 void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
00307 {
00308   /* Check the parameters */
00309   assert_param(IS_SDIO_IT(SDIO_IT));
00310   assert_param(IS_FUNCTIONAL_STATE(NewState));
00311   
00312   if (NewState != DISABLE)
00313   {
00314     /* Enable the SDIO interrupts */
00315     SDIO->MASK |= SDIO_IT;
00316   }
00317   else
00318   {
00319     /* Disable the SDIO interrupts */
00320     SDIO->MASK &= ~SDIO_IT;
00321   } 
00322 }
00323 
00324 /**
00325   * @brief  Enables or disables the SDIO DMA request.
00326   * @param  NewState: new state of the selected SDIO DMA request.
00327   *   This parameter can be: ENABLE or DISABLE.
00328   * @retval None
00329   */
00330 void SDIO_DMACmd(FunctionalState NewState)
00331 {
00332   /* Check the parameters */
00333   assert_param(IS_FUNCTIONAL_STATE(NewState));
00334   
00335   *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
00336 }
00337 
00338 /**
00339   * @brief  Initializes the SDIO Command according to the specified 
00340   *   parameters in the SDIO_CmdInitStruct and send the command.
00341   * @param  SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef 
00342   *   structure that contains the configuration information for the SDIO command.
00343   * @retval None
00344   */
00345 void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
00346 {
00347   uint32_t tmpreg = 0;
00348   
00349   /* Check the parameters */
00350   assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
00351   assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
00352   assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
00353   assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
00354   
00355 /*---------------------------- SDIO ARG Configuration ------------------------*/
00356   /* Set the SDIO Argument value */
00357   SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
00358   
00359 /*---------------------------- SDIO CMD Configuration ------------------------*/  
00360   /* Get the SDIO CMD value */
00361   tmpreg = SDIO->CMD;
00362   /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
00363   tmpreg &= CMD_CLEAR_MASK;
00364   /* Set CMDINDEX bits according to SDIO_CmdIndex value */
00365   /* Set WAITRESP bits according to SDIO_Response value */
00366   /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
00367   /* Set CPSMEN bits according to SDIO_CPSM value */
00368   tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
00369            | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
00370   
00371   /* Write to SDIO CMD */
00372   SDIO->CMD = tmpreg;
00373 }
00374 
00375 /**
00376   * @brief  Fills each SDIO_CmdInitStruct member with its default value.
00377   * @param  SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef 
00378   *   structure which will be initialized.
00379   * @retval None
00380   */
00381 void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
00382 {
00383   /* SDIO_CmdInitStruct members default value */
00384   SDIO_CmdInitStruct->SDIO_Argument = 0x00;
00385   SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
00386   SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
00387   SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
00388   SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
00389 }
00390 
00391 /**
00392   * @brief  Returns command index of last command for which response received.
00393   * @param  None
00394   * @retval Returns the command index of the last command response received.
00395   */
00396 uint8_t SDIO_GetCommandResponse(void)
00397 {
00398   return (uint8_t)(SDIO->RESPCMD);
00399 }
00400 
00401 /**
00402   * @brief  Returns response received from the card for the last command.
00403   * @param  SDIO_RESP: Specifies the SDIO response register. 
00404   *   This parameter can be one of the following values:
00405   *     @arg SDIO_RESP1: Response Register 1
00406   *     @arg SDIO_RESP2: Response Register 2
00407   *     @arg SDIO_RESP3: Response Register 3
00408   *     @arg SDIO_RESP4: Response Register 4
00409   * @retval The Corresponding response register value.
00410   */
00411 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
00412 {
00413   __IO uint32_t tmp = 0;
00414 
00415   /* Check the parameters */
00416   assert_param(IS_SDIO_RESP(SDIO_RESP));
00417 
00418   tmp = SDIO_RESP_ADDR + SDIO_RESP;
00419   
00420   return (*(__IO uint32_t *) tmp); 
00421 }
00422 
00423 /**
00424   * @brief  Initializes the SDIO data path according to the specified 
00425   *   parameters in the SDIO_DataInitStruct.
00426   * @param  SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that
00427   *   contains the configuration information for the SDIO command.
00428   * @retval None
00429   */
00430 void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
00431 {
00432   uint32_t tmpreg = 0;
00433   
00434   /* Check the parameters */
00435   assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
00436   assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
00437   assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
00438   assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
00439   assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
00440 
00441 /*---------------------------- SDIO DTIMER Configuration ---------------------*/
00442   /* Set the SDIO Data TimeOut value */
00443   SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
00444 
00445 /*---------------------------- SDIO DLEN Configuration -----------------------*/
00446   /* Set the SDIO DataLength value */
00447   SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
00448 
00449 /*---------------------------- SDIO DCTRL Configuration ----------------------*/  
00450   /* Get the SDIO DCTRL value */
00451   tmpreg = SDIO->DCTRL;
00452   /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
00453   tmpreg &= DCTRL_CLEAR_MASK;
00454   /* Set DEN bit according to SDIO_DPSM value */
00455   /* Set DTMODE bit according to SDIO_TransferMode value */
00456   /* Set DTDIR bit according to SDIO_TransferDir value */
00457   /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
00458   tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
00459            | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
00460 
00461   /* Write to SDIO DCTRL */
00462   SDIO->DCTRL = tmpreg;
00463 }
00464 
00465 /**
00466   * @brief  Fills each SDIO_DataInitStruct member with its default value.
00467   * @param  SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which
00468   *   will be initialized.
00469   * @retval None
00470   */
00471 void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
00472 {
00473   /* SDIO_DataInitStruct members default value */
00474   SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
00475   SDIO_DataInitStruct->SDIO_DataLength = 0x00;
00476   SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
00477   SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
00478   SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;  
00479   SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
00480 }
00481 
00482 /**
00483   * @brief  Returns number of remaining data bytes to be transferred.
00484   * @param  None
00485   * @retval Number of remaining data bytes to be transferred
00486   */
00487 uint32_t SDIO_GetDataCounter(void)
00488 { 
00489   return SDIO->DCOUNT;
00490 }
00491 
00492 /**
00493   * @brief  Read one data word from Rx FIFO.
00494   * @param  None
00495   * @retval Data received
00496   */
00497 uint32_t SDIO_ReadData(void)
00498 { 
00499   return SDIO->FIFO;
00500 }
00501 
00502 /**
00503   * @brief  Write one data word to Tx FIFO.
00504   * @param  Data: 32-bit data word to write.
00505   * @retval None
00506   */
00507 void SDIO_WriteData(uint32_t Data)
00508 { 
00509   SDIO->FIFO = Data;
00510 }
00511 
00512 /**
00513   * @brief  Returns the number of words left to be written to or read from FIFO.        
00514   * @param  None
00515   * @retval Remaining number of words.
00516   */
00517 uint32_t SDIO_GetFIFOCount(void)
00518 { 
00519   return SDIO->FIFOCNT;
00520 }
00521 
00522 /**
00523   * @brief  Starts the SD I/O Read Wait operation.      
00524   * @param  NewState: new state of the Start SDIO Read Wait operation. 
00525   *   This parameter can be: ENABLE or DISABLE.
00526   * @retval None
00527   */
00528 void SDIO_StartSDIOReadWait(FunctionalState NewState)
00529 { 
00530   /* Check the parameters */
00531   assert_param(IS_FUNCTIONAL_STATE(NewState));
00532   
00533   *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
00534 }
00535 
00536 /**
00537   * @brief  Stops the SD I/O Read Wait operation.       
00538   * @param  NewState: new state of the Stop SDIO Read Wait operation. 
00539   *   This parameter can be: ENABLE or DISABLE.
00540   * @retval None
00541   */
00542 void SDIO_StopSDIOReadWait(FunctionalState NewState)
00543 { 
00544   /* Check the parameters */
00545   assert_param(IS_FUNCTIONAL_STATE(NewState));
00546   
00547   *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
00548 }
00549 
00550 /**
00551   * @brief  Sets one of the two options of inserting read wait interval.
00552   * @param  SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
00553   *   This parametre can be:
00554   *     @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
00555   *     @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
00556   * @retval None
00557   */
00558 void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
00559 {
00560   /* Check the parameters */
00561   assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
00562   
00563   *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
00564 }
00565 
00566 /**
00567   * @brief  Enables or disables the SD I/O Mode Operation.
00568   * @param  NewState: new state of SDIO specific operation. 
00569   *   This parameter can be: ENABLE or DISABLE.
00570   * @retval None
00571   */
00572 void SDIO_SetSDIOOperation(FunctionalState NewState)
00573 { 
00574   /* Check the parameters */
00575   assert_param(IS_FUNCTIONAL_STATE(NewState));
00576   
00577   *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
00578 }
00579 
00580 /**
00581   * @brief  Enables or disables the SD I/O Mode suspend command sending.
00582   * @param  NewState: new state of the SD I/O Mode suspend command.
00583   *   This parameter can be: ENABLE or DISABLE.
00584   * @retval None
00585   */
00586 void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
00587 { 
00588   /* Check the parameters */
00589   assert_param(IS_FUNCTIONAL_STATE(NewState));
00590   
00591   *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
00592 }
00593 
00594 /**
00595   * @brief  Enables or disables the command completion signal.
00596   * @param  NewState: new state of command completion signal. 
00597   *   This parameter can be: ENABLE or DISABLE.
00598   * @retval None
00599   */
00600 void SDIO_CommandCompletionCmd(FunctionalState NewState)
00601 { 
00602   /* Check the parameters */
00603   assert_param(IS_FUNCTIONAL_STATE(NewState));
00604   
00605   *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
00606 }
00607 
00608 /**
00609   * @brief  Enables or disables the CE-ATA interrupt.
00610   * @param  NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
00611   * @retval None
00612   */
00613 void SDIO_CEATAITCmd(FunctionalState NewState)
00614 { 
00615   /* Check the parameters */
00616   assert_param(IS_FUNCTIONAL_STATE(NewState));
00617   
00618   *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
00619 }
00620 
00621 /**
00622   * @brief  Sends CE-ATA command (CMD61).
00623   * @param  NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
00624   * @retval None
00625   */
00626 void SDIO_SendCEATACmd(FunctionalState NewState)
00627 { 
00628   /* Check the parameters */
00629   assert_param(IS_FUNCTIONAL_STATE(NewState));
00630   
00631   *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
00632 }
00633 
00634 /**
00635   * @brief  Checks whether the specified SDIO flag is set or not.
00636   * @param  SDIO_FLAG: specifies the flag to check. 
00637   *   This parameter can be one of the following values:
00638   *     @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
00639   *     @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
00640   *     @arg SDIO_FLAG_CTIMEOUT: Command response timeout
00641   *     @arg SDIO_FLAG_DTIMEOUT: Data timeout
00642   *     @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
00643   *     @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
00644   *     @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
00645   *     @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
00646   *     @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
00647   *     @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide 
00648   *                              bus mode.
00649   *     @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
00650   *     @arg SDIO_FLAG_CMDACT:   Command transfer in progress
00651   *     @arg SDIO_FLAG_TXACT:    Data transmit in progress
00652   *     @arg SDIO_FLAG_RXACT:    Data receive in progress
00653   *     @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
00654   *     @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
00655   *     @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
00656   *     @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
00657   *     @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
00658   *     @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
00659   *     @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
00660   *     @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
00661   *     @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
00662   *     @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
00663   * @retval The new state of SDIO_FLAG (SET or RESET).
00664   */
00665 FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
00666 { 
00667   FlagStatus bitstatus = RESET;
00668   
00669   /* Check the parameters */
00670   assert_param(IS_SDIO_FLAG(SDIO_FLAG));
00671   
00672   if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
00673   {
00674     bitstatus = SET;
00675   }
00676   else
00677   {
00678     bitstatus = RESET;
00679   }
00680   return bitstatus;
00681 }
00682 
00683 /**
00684   * @brief  Clears the SDIO's pending flags.
00685   * @param  SDIO_FLAG: specifies the flag to clear.  
00686   *   This parameter can be one or a combination of the following values:
00687   *     @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
00688   *     @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
00689   *     @arg SDIO_FLAG_CTIMEOUT: Command response timeout
00690   *     @arg SDIO_FLAG_DTIMEOUT: Data timeout
00691   *     @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
00692   *     @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
00693   *     @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
00694   *     @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
00695   *     @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
00696   *     @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide 
00697   *                              bus mode
00698   *     @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
00699   *     @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
00700   *     @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
00701   * @retval None
00702   */
00703 void SDIO_ClearFlag(uint32_t SDIO_FLAG)
00704 { 
00705   /* Check the parameters */
00706   assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
00707    
00708   SDIO->ICR = SDIO_FLAG;
00709 }
00710 
00711 /**
00712   * @brief  Checks whether the specified SDIO interrupt has occurred or not.
00713   * @param  SDIO_IT: specifies the SDIO interrupt source to check. 
00714   *   This parameter can be one of the following values:
00715   *     @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00716   *     @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00717   *     @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
00718   *     @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
00719   *     @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00720   *     @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
00721   *     @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
00722   *     @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
00723   *     @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
00724   *     @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
00725   *                            bus mode interrupt
00726   *     @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
00727   *     @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
00728   *     @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
00729   *     @arg SDIO_IT_RXACT:    Data receive in progress interrupt
00730   *     @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
00731   *     @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
00732   *     @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
00733   *     @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
00734   *     @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
00735   *     @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
00736   *     @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
00737   *     @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
00738   *     @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
00739   *     @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
00740   * @retval The new state of SDIO_IT (SET or RESET).
00741   */
00742 ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
00743 { 
00744   ITStatus bitstatus = RESET;
00745   
00746   /* Check the parameters */
00747   assert_param(IS_SDIO_GET_IT(SDIO_IT));
00748   if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)  
00749   {
00750     bitstatus = SET;
00751   }
00752   else
00753   {
00754     bitstatus = RESET;
00755   }
00756   return bitstatus;
00757 }
00758 
00759 /**
00760   * @brief  Clears the SDIO’s interrupt pending bits.
00761   * @param  SDIO_IT: specifies the interrupt pending bit to clear. 
00762   *   This parameter can be one or a combination of the following values:
00763   *     @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00764   *     @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00765   *     @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
00766   *     @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
00767   *     @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00768   *     @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
00769   *     @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
00770   *     @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
00771   *     @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
00772   *     @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
00773   *                            bus mode interrupt
00774   *     @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
00775   *     @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
00776   * @retval None
00777   */
00778 void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
00779 { 
00780   /* Check the parameters */
00781   assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
00782    
00783   SDIO->ICR = SDIO_IT;
00784 }
00785 
00786 /**
00787   * @}
00788   */
00789 
00790 /**
00791   * @}
00792   */
00793 
00794 /**
00795   * @}
00796   */
00797 
00798 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
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