stm32f10x_rcc.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_rcc.h
00004   * @author  MCD Application Team
00005   * @version V3.4.0
00006   * @date    10/15/2010
00007   * @brief   This file contains all the functions prototypes for the RCC firmware 
00008   *          library.
00009   ******************************************************************************
00010   * @copy
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
00020   */ 
00021 
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_RCC_H
00024 #define __STM32F10x_RCC_H
00025 
00026 #ifdef __cplusplus
00027  extern "C" {
00028 #endif
00029 
00030 /* Includes ------------------------------------------------------------------*/
00031 #include "stm32f10x.h"
00032 
00033 /** @addtogroup STM32F10x_StdPeriph_Driver
00034   * @{
00035   */
00036 
00037 /** @addtogroup RCC
00038   * @{
00039   */
00040 
00041 /** @defgroup RCC_Exported_Types
00042   * @{
00043   */
00044 
00045 typedef struct
00046 {
00047   uint32_t SYSCLK_Frequency;  /*!< returns SYSCLK clock frequency expressed in Hz */
00048   uint32_t HCLK_Frequency;    /*!< returns HCLK clock frequency expressed in Hz */
00049   uint32_t PCLK1_Frequency;   /*!< returns PCLK1 clock frequency expressed in Hz */
00050   uint32_t PCLK2_Frequency;   /*!< returns PCLK2 clock frequency expressed in Hz */
00051   uint32_t ADCCLK_Frequency;  /*!< returns ADCCLK clock frequency expressed in Hz */
00052 }RCC_ClocksTypeDef;
00053 
00054 /**
00055   * @}
00056   */
00057 
00058 /** @defgroup RCC_Exported_Constants
00059   * @{
00060   */
00061 
00062 /** @defgroup HSE_configuration 
00063   * @{
00064   */
00065 
00066 #define RCC_HSE_OFF                      ((uint32_t)0x00000000)
00067 #define RCC_HSE_ON                       ((uint32_t)0x00010000)
00068 #define RCC_HSE_Bypass                   ((uint32_t)0x00040000)
00069 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
00070                          ((HSE) == RCC_HSE_Bypass))
00071 
00072 /**
00073   * @}
00074   */ 
00075 
00076 /** @defgroup PLL_entry_clock_source 
00077   * @{
00078   */
00079 
00080 #define RCC_PLLSource_HSI_Div2           ((uint32_t)0x00000000)
00081 
00082 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL)
00083  #define RCC_PLLSource_HSE_Div1           ((uint32_t)0x00010000)
00084  #define RCC_PLLSource_HSE_Div2           ((uint32_t)0x00030000)
00085  #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
00086                                    ((SOURCE) == RCC_PLLSource_HSE_Div1) || \
00087                                    ((SOURCE) == RCC_PLLSource_HSE_Div2))
00088 #else
00089  #define RCC_PLLSource_PREDIV1            ((uint32_t)0x00010000)
00090  #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
00091                                    ((SOURCE) == RCC_PLLSource_PREDIV1))
00092 #endif /* STM32F10X_CL */ 
00093 
00094 /**
00095   * @}
00096   */ 
00097 
00098 /** @defgroup PLL_multiplication_factor 
00099   * @{
00100   */
00101 #ifndef STM32F10X_CL
00102  #define RCC_PLLMul_2                    ((uint32_t)0x00000000)
00103  #define RCC_PLLMul_3                    ((uint32_t)0x00040000)
00104  #define RCC_PLLMul_4                    ((uint32_t)0x00080000)
00105  #define RCC_PLLMul_5                    ((uint32_t)0x000C0000)
00106  #define RCC_PLLMul_6                    ((uint32_t)0x00100000)
00107  #define RCC_PLLMul_7                    ((uint32_t)0x00140000)
00108  #define RCC_PLLMul_8                    ((uint32_t)0x00180000)
00109  #define RCC_PLLMul_9                    ((uint32_t)0x001C0000)
00110  #define RCC_PLLMul_10                   ((uint32_t)0x00200000)
00111  #define RCC_PLLMul_11                   ((uint32_t)0x00240000)
00112  #define RCC_PLLMul_12                   ((uint32_t)0x00280000)
00113  #define RCC_PLLMul_13                   ((uint32_t)0x002C0000)
00114  #define RCC_PLLMul_14                   ((uint32_t)0x00300000)
00115  #define RCC_PLLMul_15                   ((uint32_t)0x00340000)
00116  #define RCC_PLLMul_16                   ((uint32_t)0x00380000)
00117  #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3)   || \
00118                               ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5)   || \
00119                               ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7)   || \
00120                               ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9)   || \
00121                               ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
00122                               ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
00123                               ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
00124                               ((MUL) == RCC_PLLMul_16))
00125 
00126 #else
00127  #define RCC_PLLMul_4                    ((uint32_t)0x00080000)
00128  #define RCC_PLLMul_5                    ((uint32_t)0x000C0000)
00129  #define RCC_PLLMul_6                    ((uint32_t)0x00100000)
00130  #define RCC_PLLMul_7                    ((uint32_t)0x00140000)
00131  #define RCC_PLLMul_8                    ((uint32_t)0x00180000)
00132  #define RCC_PLLMul_9                    ((uint32_t)0x001C0000)
00133  #define RCC_PLLMul_6_5                  ((uint32_t)0x00340000)
00134 
00135  #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
00136                               ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
00137                               ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
00138                               ((MUL) == RCC_PLLMul_6_5))
00139 #endif /* STM32F10X_CL */                              
00140 /**
00141   * @}
00142   */
00143 
00144 /** @defgroup PREDIV1_division_factor
00145   * @{
00146   */
00147 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
00148  #define  RCC_PREDIV1_Div1               ((uint32_t)0x00000000)
00149  #define  RCC_PREDIV1_Div2               ((uint32_t)0x00000001)
00150  #define  RCC_PREDIV1_Div3               ((uint32_t)0x00000002)
00151  #define  RCC_PREDIV1_Div4               ((uint32_t)0x00000003)
00152  #define  RCC_PREDIV1_Div5               ((uint32_t)0x00000004)
00153  #define  RCC_PREDIV1_Div6               ((uint32_t)0x00000005)
00154  #define  RCC_PREDIV1_Div7               ((uint32_t)0x00000006)
00155  #define  RCC_PREDIV1_Div8               ((uint32_t)0x00000007)
00156  #define  RCC_PREDIV1_Div9               ((uint32_t)0x00000008)
00157  #define  RCC_PREDIV1_Div10              ((uint32_t)0x00000009)
00158  #define  RCC_PREDIV1_Div11              ((uint32_t)0x0000000A)
00159  #define  RCC_PREDIV1_Div12              ((uint32_t)0x0000000B)
00160  #define  RCC_PREDIV1_Div13              ((uint32_t)0x0000000C)
00161  #define  RCC_PREDIV1_Div14              ((uint32_t)0x0000000D)
00162  #define  RCC_PREDIV1_Div15              ((uint32_t)0x0000000E)
00163  #define  RCC_PREDIV1_Div16              ((uint32_t)0x0000000F)
00164 
00165  #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
00166                                   ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
00167                                   ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
00168                                   ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
00169                                   ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
00170                                   ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
00171                                   ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
00172                                   ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
00173 #endif
00174 /**
00175   * @}
00176   */
00177 
00178 
00179 /** @defgroup PREDIV1_clock_source
00180   * @{
00181   */
00182 #ifdef STM32F10X_CL
00183 /* PREDIV1 clock source (for STM32 connectivity line devices) */
00184  #define  RCC_PREDIV1_Source_HSE         ((uint32_t)0x00000000) 
00185  #define  RCC_PREDIV1_Source_PLL2        ((uint32_t)0x00010000) 
00186 
00187  #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \
00188                                         ((SOURCE) == RCC_PREDIV1_Source_PLL2)) 
00189 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00190 /* PREDIV1 clock source (for STM32 Value line devices) */
00191  #define  RCC_PREDIV1_Source_HSE         ((uint32_t)0x00000000) 
00192 
00193  #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) 
00194 #endif
00195 /**
00196   * @}
00197   */
00198 
00199 #ifdef STM32F10X_CL
00200 /** @defgroup PREDIV2_division_factor
00201   * @{
00202   */
00203   
00204  #define  RCC_PREDIV2_Div1               ((uint32_t)0x00000000)
00205  #define  RCC_PREDIV2_Div2               ((uint32_t)0x00000010)
00206  #define  RCC_PREDIV2_Div3               ((uint32_t)0x00000020)
00207  #define  RCC_PREDIV2_Div4               ((uint32_t)0x00000030)
00208  #define  RCC_PREDIV2_Div5               ((uint32_t)0x00000040)
00209  #define  RCC_PREDIV2_Div6               ((uint32_t)0x00000050)
00210  #define  RCC_PREDIV2_Div7               ((uint32_t)0x00000060)
00211  #define  RCC_PREDIV2_Div8               ((uint32_t)0x00000070)
00212  #define  RCC_PREDIV2_Div9               ((uint32_t)0x00000080)
00213  #define  RCC_PREDIV2_Div10              ((uint32_t)0x00000090)
00214  #define  RCC_PREDIV2_Div11              ((uint32_t)0x000000A0)
00215  #define  RCC_PREDIV2_Div12              ((uint32_t)0x000000B0)
00216  #define  RCC_PREDIV2_Div13              ((uint32_t)0x000000C0)
00217  #define  RCC_PREDIV2_Div14              ((uint32_t)0x000000D0)
00218  #define  RCC_PREDIV2_Div15              ((uint32_t)0x000000E0)
00219  #define  RCC_PREDIV2_Div16              ((uint32_t)0x000000F0)
00220 
00221  #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \
00222                                   ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \
00223                                   ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \
00224                                   ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \
00225                                   ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \
00226                                   ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \
00227                                   ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \
00228                                   ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16))
00229 /**
00230   * @}
00231   */
00232 
00233 
00234 /** @defgroup PLL2_multiplication_factor
00235   * @{
00236   */
00237   
00238  #define  RCC_PLL2Mul_8                  ((uint32_t)0x00000600)
00239  #define  RCC_PLL2Mul_9                  ((uint32_t)0x00000700)
00240  #define  RCC_PLL2Mul_10                 ((uint32_t)0x00000800)
00241  #define  RCC_PLL2Mul_11                 ((uint32_t)0x00000900)
00242  #define  RCC_PLL2Mul_12                 ((uint32_t)0x00000A00)
00243  #define  RCC_PLL2Mul_13                 ((uint32_t)0x00000B00)
00244  #define  RCC_PLL2Mul_14                 ((uint32_t)0x00000C00)
00245  #define  RCC_PLL2Mul_16                 ((uint32_t)0x00000E00)
00246  #define  RCC_PLL2Mul_20                 ((uint32_t)0x00000F00)
00247 
00248  #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9)  || \
00249                                ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \
00250                                ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \
00251                                ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \
00252                                ((MUL) == RCC_PLL2Mul_20))
00253 /**
00254   * @}
00255   */
00256 
00257 
00258 /** @defgroup PLL3_multiplication_factor
00259   * @{
00260   */
00261 
00262  #define  RCC_PLL3Mul_8                  ((uint32_t)0x00006000)
00263  #define  RCC_PLL3Mul_9                  ((uint32_t)0x00007000)
00264  #define  RCC_PLL3Mul_10                 ((uint32_t)0x00008000)
00265  #define  RCC_PLL3Mul_11                 ((uint32_t)0x00009000)
00266  #define  RCC_PLL3Mul_12                 ((uint32_t)0x0000A000)
00267  #define  RCC_PLL3Mul_13                 ((uint32_t)0x0000B000)
00268  #define  RCC_PLL3Mul_14                 ((uint32_t)0x0000C000)
00269  #define  RCC_PLL3Mul_16                 ((uint32_t)0x0000E000)
00270  #define  RCC_PLL3Mul_20                 ((uint32_t)0x0000F000)
00271 
00272  #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9)  || \
00273                                ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \
00274                                ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \
00275                                ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \
00276                                ((MUL) == RCC_PLL3Mul_20))
00277 /**
00278   * @}
00279   */
00280 
00281 #endif /* STM32F10X_CL */
00282 
00283 
00284 /** @defgroup System_clock_source 
00285   * @{
00286   */
00287 
00288 #define RCC_SYSCLKSource_HSI             ((uint32_t)0x00000000)
00289 #define RCC_SYSCLKSource_HSE             ((uint32_t)0x00000001)
00290 #define RCC_SYSCLKSource_PLLCLK          ((uint32_t)0x00000002)
00291 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
00292                                       ((SOURCE) == RCC_SYSCLKSource_HSE) || \
00293                                       ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
00294 /**
00295   * @}
00296   */
00297 
00298 /** @defgroup AHB_clock_source 
00299   * @{
00300   */
00301 
00302 #define RCC_SYSCLK_Div1                  ((uint32_t)0x00000000)
00303 #define RCC_SYSCLK_Div2                  ((uint32_t)0x00000080)
00304 #define RCC_SYSCLK_Div4                  ((uint32_t)0x00000090)
00305 #define RCC_SYSCLK_Div8                  ((uint32_t)0x000000A0)
00306 #define RCC_SYSCLK_Div16                 ((uint32_t)0x000000B0)
00307 #define RCC_SYSCLK_Div64                 ((uint32_t)0x000000C0)
00308 #define RCC_SYSCLK_Div128                ((uint32_t)0x000000D0)
00309 #define RCC_SYSCLK_Div256                ((uint32_t)0x000000E0)
00310 #define RCC_SYSCLK_Div512                ((uint32_t)0x000000F0)
00311 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
00312                            ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
00313                            ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
00314                            ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
00315                            ((HCLK) == RCC_SYSCLK_Div512))
00316 /**
00317   * @}
00318   */ 
00319 
00320 /** @defgroup APB1_APB2_clock_source 
00321   * @{
00322   */
00323 
00324 #define RCC_HCLK_Div1                    ((uint32_t)0x00000000)
00325 #define RCC_HCLK_Div2                    ((uint32_t)0x00000400)
00326 #define RCC_HCLK_Div4                    ((uint32_t)0x00000500)
00327 #define RCC_HCLK_Div8                    ((uint32_t)0x00000600)
00328 #define RCC_HCLK_Div16                   ((uint32_t)0x00000700)
00329 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
00330                            ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
00331                            ((PCLK) == RCC_HCLK_Div16))
00332 /**
00333   * @}
00334   */
00335 
00336 /** @defgroup RCC_Interrupt_source 
00337   * @{
00338   */
00339 
00340 #define RCC_IT_LSIRDY                    ((uint8_t)0x01)
00341 #define RCC_IT_LSERDY                    ((uint8_t)0x02)
00342 #define RCC_IT_HSIRDY                    ((uint8_t)0x04)
00343 #define RCC_IT_HSERDY                    ((uint8_t)0x08)
00344 #define RCC_IT_PLLRDY                    ((uint8_t)0x10)
00345 #define RCC_IT_CSS                       ((uint8_t)0x80)
00346 
00347 #ifndef STM32F10X_CL
00348  #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
00349  #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
00350                             ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
00351                             ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
00352  #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
00353 #else
00354  #define RCC_IT_PLL2RDY                  ((uint8_t)0x20)
00355  #define RCC_IT_PLL3RDY                  ((uint8_t)0x40)
00356  #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
00357  #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
00358                             ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
00359                             ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
00360                             ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY))
00361  #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
00362 #endif /* STM32F10X_CL */ 
00363 
00364 
00365 /**
00366   * @}
00367   */
00368 
00369 #ifndef STM32F10X_CL
00370 /** @defgroup USB_Device_clock_source 
00371   * @{
00372   */
00373 
00374  #define RCC_USBCLKSource_PLLCLK_1Div5   ((uint8_t)0x00)
00375  #define RCC_USBCLKSource_PLLCLK_Div1    ((uint8_t)0x01)
00376 
00377  #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
00378                                       ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
00379 /**
00380   * @}
00381   */
00382 #else
00383 /** @defgroup USB_OTG_FS_clock_source 
00384   * @{
00385   */
00386  #define RCC_OTGFSCLKSource_PLLVCO_Div3    ((uint8_t)0x00)
00387  #define RCC_OTGFSCLKSource_PLLVCO_Div2    ((uint8_t)0x01)
00388 
00389  #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \
00390                                          ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2))
00391 /**
00392   * @}
00393   */
00394 #endif /* STM32F10X_CL */ 
00395 
00396 
00397 #ifdef STM32F10X_CL
00398 /** @defgroup I2S2_clock_source 
00399   * @{
00400   */
00401  #define RCC_I2S2CLKSource_SYSCLK        ((uint8_t)0x00)
00402  #define RCC_I2S2CLKSource_PLL3_VCO      ((uint8_t)0x01)
00403 
00404  #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \
00405                                         ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO))
00406 /**
00407   * @}
00408   */
00409 
00410 /** @defgroup I2S3_clock_source 
00411   * @{
00412   */
00413  #define RCC_I2S3CLKSource_SYSCLK        ((uint8_t)0x00)
00414  #define RCC_I2S3CLKSource_PLL3_VCO      ((uint8_t)0x01)
00415 
00416  #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \
00417                                         ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO))    
00418 /**
00419   * @}
00420   */
00421 #endif /* STM32F10X_CL */  
00422   
00423 
00424 /** @defgroup ADC_clock_source 
00425   * @{
00426   */
00427 
00428 #define RCC_PCLK2_Div2                   ((uint32_t)0x00000000)
00429 #define RCC_PCLK2_Div4                   ((uint32_t)0x00004000)
00430 #define RCC_PCLK2_Div6                   ((uint32_t)0x00008000)
00431 #define RCC_PCLK2_Div8                   ((uint32_t)0x0000C000)
00432 #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
00433                                ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
00434 /**
00435   * @}
00436   */
00437 
00438 /** @defgroup LSE_configuration 
00439   * @{
00440   */
00441 
00442 #define RCC_LSE_OFF                      ((uint8_t)0x00)
00443 #define RCC_LSE_ON                       ((uint8_t)0x01)
00444 #define RCC_LSE_Bypass                   ((uint8_t)0x04)
00445 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
00446                          ((LSE) == RCC_LSE_Bypass))
00447 /**
00448   * @}
00449   */
00450 
00451 /** @defgroup RTC_clock_source 
00452   * @{
00453   */
00454 
00455 #define RCC_RTCCLKSource_LSE             ((uint32_t)0x00000100)
00456 #define RCC_RTCCLKSource_LSI             ((uint32_t)0x00000200)
00457 #define RCC_RTCCLKSource_HSE_Div128      ((uint32_t)0x00000300)
00458 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
00459                                       ((SOURCE) == RCC_RTCCLKSource_LSI) || \
00460                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
00461 /**
00462   * @}
00463   */
00464 
00465 /** @defgroup AHB_peripheral 
00466   * @{
00467   */
00468 
00469 #define RCC_AHBPeriph_DMA1               ((uint32_t)0x00000001)
00470 #define RCC_AHBPeriph_DMA2               ((uint32_t)0x00000002)
00471 #define RCC_AHBPeriph_SRAM               ((uint32_t)0x00000004)
00472 #define RCC_AHBPeriph_FLITF              ((uint32_t)0x00000010)
00473 #define RCC_AHBPeriph_CRC                ((uint32_t)0x00000040)
00474 
00475 #ifndef STM32F10X_CL
00476  #define RCC_AHBPeriph_FSMC              ((uint32_t)0x00000100)
00477  #define RCC_AHBPeriph_SDIO              ((uint32_t)0x00000400)
00478  #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
00479 #else
00480  #define RCC_AHBPeriph_OTG_FS            ((uint32_t)0x00001000)
00481  #define RCC_AHBPeriph_ETH_MAC           ((uint32_t)0x00004000)
00482  #define RCC_AHBPeriph_ETH_MAC_Tx        ((uint32_t)0x00008000)
00483  #define RCC_AHBPeriph_ETH_MAC_Rx        ((uint32_t)0x00010000)
00484 
00485  #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00))
00486  #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00))
00487 #endif /* STM32F10X_CL */
00488 /**
00489   * @}
00490   */
00491 
00492 /** @defgroup APB2_peripheral 
00493   * @{
00494   */
00495 
00496 #define RCC_APB2Periph_AFIO              ((uint32_t)0x00000001)
00497 #define RCC_APB2Periph_GPIOA             ((uint32_t)0x00000004)
00498 #define RCC_APB2Periph_GPIOB             ((uint32_t)0x00000008)
00499 #define RCC_APB2Periph_GPIOC             ((uint32_t)0x00000010)
00500 #define RCC_APB2Periph_GPIOD             ((uint32_t)0x00000020)
00501 #define RCC_APB2Periph_GPIOE             ((uint32_t)0x00000040)
00502 #define RCC_APB2Periph_GPIOF             ((uint32_t)0x00000080)
00503 #define RCC_APB2Periph_GPIOG             ((uint32_t)0x00000100)
00504 #define RCC_APB2Periph_ADC1              ((uint32_t)0x00000200)
00505 #define RCC_APB2Periph_ADC2              ((uint32_t)0x00000400)
00506 #define RCC_APB2Periph_TIM1              ((uint32_t)0x00000800)
00507 #define RCC_APB2Periph_SPI1              ((uint32_t)0x00001000)
00508 #define RCC_APB2Periph_TIM8              ((uint32_t)0x00002000)
00509 #define RCC_APB2Periph_USART1            ((uint32_t)0x00004000)
00510 #define RCC_APB2Periph_ADC3              ((uint32_t)0x00008000)
00511 #define RCC_APB2Periph_TIM15             ((uint32_t)0x00010000)
00512 #define RCC_APB2Periph_TIM16             ((uint32_t)0x00020000)
00513 #define RCC_APB2Periph_TIM17             ((uint32_t)0x00040000)
00514 #define RCC_APB2Periph_TIM9              ((uint32_t)0x00080000)
00515 #define RCC_APB2Periph_TIM10             ((uint32_t)0x00100000)
00516 #define RCC_APB2Periph_TIM11             ((uint32_t)0x00200000)
00517 
00518 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))
00519 /**
00520   * @}
00521   */ 
00522 
00523 /** @defgroup APB1_peripheral 
00524   * @{
00525   */
00526 
00527 #define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)
00528 #define RCC_APB1Periph_TIM3              ((uint32_t)0x00000002)
00529 #define RCC_APB1Periph_TIM4              ((uint32_t)0x00000004)
00530 #define RCC_APB1Periph_TIM5              ((uint32_t)0x00000008)
00531 #define RCC_APB1Periph_TIM6              ((uint32_t)0x00000010)
00532 #define RCC_APB1Periph_TIM7              ((uint32_t)0x00000020)
00533 #define RCC_APB1Periph_TIM12             ((uint32_t)0x00000040)
00534 #define RCC_APB1Periph_TIM13             ((uint32_t)0x00000080)
00535 #define RCC_APB1Periph_TIM14             ((uint32_t)0x00000100)
00536 #define RCC_APB1Periph_WWDG              ((uint32_t)0x00000800)
00537 #define RCC_APB1Periph_SPI2              ((uint32_t)0x00004000)
00538 #define RCC_APB1Periph_SPI3              ((uint32_t)0x00008000)
00539 #define RCC_APB1Periph_USART2            ((uint32_t)0x00020000)
00540 #define RCC_APB1Periph_USART3            ((uint32_t)0x00040000)
00541 #define RCC_APB1Periph_UART4             ((uint32_t)0x00080000)
00542 #define RCC_APB1Periph_UART5             ((uint32_t)0x00100000)
00543 #define RCC_APB1Periph_I2C1              ((uint32_t)0x00200000)
00544 #define RCC_APB1Periph_I2C2              ((uint32_t)0x00400000)
00545 #define RCC_APB1Periph_USB               ((uint32_t)0x00800000)
00546 #define RCC_APB1Periph_CAN1              ((uint32_t)0x02000000)
00547 #define RCC_APB1Periph_CAN2              ((uint32_t)0x04000000)
00548 #define RCC_APB1Periph_BKP               ((uint32_t)0x08000000)
00549 #define RCC_APB1Periph_PWR               ((uint32_t)0x10000000)
00550 #define RCC_APB1Periph_DAC               ((uint32_t)0x20000000)
00551 #define RCC_APB1Periph_CEC               ((uint32_t)0x40000000)
00552  
00553 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))
00554 
00555 /**
00556   * @}
00557   */
00558 
00559 /** @defgroup Clock_source_to_output_on_MCO_pin 
00560   * @{
00561   */
00562 
00563 #define RCC_MCO_NoClock                  ((uint8_t)0x00)
00564 #define RCC_MCO_SYSCLK                   ((uint8_t)0x04)
00565 #define RCC_MCO_HSI                      ((uint8_t)0x05)
00566 #define RCC_MCO_HSE                      ((uint8_t)0x06)
00567 #define RCC_MCO_PLLCLK_Div2              ((uint8_t)0x07)
00568 
00569 #ifndef STM32F10X_CL
00570  #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
00571                           ((MCO) == RCC_MCO_SYSCLK)  || ((MCO) == RCC_MCO_HSE) || \
00572                           ((MCO) == RCC_MCO_PLLCLK_Div2))
00573 #else
00574  #define RCC_MCO_PLL2CLK                 ((uint8_t)0x08)
00575  #define RCC_MCO_PLL3CLK_Div2            ((uint8_t)0x09)
00576  #define RCC_MCO_XT1                     ((uint8_t)0x0A)
00577  #define RCC_MCO_PLL3CLK                 ((uint8_t)0x0B)
00578 
00579  #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
00580                           ((MCO) == RCC_MCO_SYSCLK)  || ((MCO) == RCC_MCO_HSE) || \
00581                           ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \
00582                           ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \
00583                           ((MCO) == RCC_MCO_PLL3CLK))
00584 #endif /* STM32F10X_CL */ 
00585 
00586 /**
00587   * @}
00588   */
00589 
00590 /** @defgroup RCC_Flag 
00591   * @{
00592   */
00593 
00594 #define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
00595 #define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
00596 #define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
00597 #define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
00598 #define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
00599 #define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
00600 #define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
00601 #define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
00602 #define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
00603 #define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
00604 #define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
00605 
00606 #ifndef STM32F10X_CL
00607  #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
00608                             ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
00609                             ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
00610                             ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
00611                             ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
00612                             ((FLAG) == RCC_FLAG_LPWRRST))
00613 #else
00614  #define RCC_FLAG_PLL2RDY                ((uint8_t)0x3B) 
00615  #define RCC_FLAG_PLL3RDY                ((uint8_t)0x3D) 
00616  #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
00617                             ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
00618                             ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \
00619                             ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
00620                             ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
00621                             ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
00622                             ((FLAG) == RCC_FLAG_LPWRRST))
00623 #endif /* STM32F10X_CL */ 
00624 
00625 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
00626 /**
00627   * @}
00628   */
00629 
00630 /**
00631   * @}
00632   */
00633 
00634 /** @defgroup RCC_Exported_Macros
00635   * @{
00636   */
00637 
00638 /**
00639   * @}
00640   */
00641 
00642 /** @defgroup RCC_Exported_Functions
00643   * @{
00644   */
00645 
00646 void RCC_DeInit(void);
00647 void RCC_HSEConfig(uint32_t RCC_HSE);
00648 ErrorStatus RCC_WaitForHSEStartUp(void);
00649 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
00650 void RCC_HSICmd(FunctionalState NewState);
00651 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
00652 void RCC_PLLCmd(FunctionalState NewState);
00653 
00654 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
00655  void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
00656 #endif
00657 
00658 #ifdef  STM32F10X_CL
00659  void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
00660  void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
00661  void RCC_PLL2Cmd(FunctionalState NewState);
00662  void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
00663  void RCC_PLL3Cmd(FunctionalState NewState);
00664 #endif /* STM32F10X_CL */ 
00665 
00666 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
00667 uint8_t RCC_GetSYSCLKSource(void);
00668 void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
00669 void RCC_PCLK1Config(uint32_t RCC_HCLK);
00670 void RCC_PCLK2Config(uint32_t RCC_HCLK);
00671 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
00672 
00673 #ifndef STM32F10X_CL
00674  void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
00675 #else
00676  void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);
00677 #endif /* STM32F10X_CL */ 
00678 
00679 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
00680 
00681 #ifdef STM32F10X_CL
00682  void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);                                  
00683  void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
00684 #endif /* STM32F10X_CL */ 
00685 
00686 void RCC_LSEConfig(uint8_t RCC_LSE);
00687 void RCC_LSICmd(FunctionalState NewState);
00688 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
00689 void RCC_RTCCLKCmd(FunctionalState NewState);
00690 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
00691 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
00692 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
00693 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
00694 
00695 #ifdef STM32F10X_CL
00696 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
00697 #endif /* STM32F10X_CL */ 
00698 
00699 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
00700 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
00701 void RCC_BackupResetCmd(FunctionalState NewState);
00702 void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
00703 void RCC_MCOConfig(uint8_t RCC_MCO);
00704 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
00705 void RCC_ClearFlag(void);
00706 ITStatus RCC_GetITStatus(uint8_t RCC_IT);
00707 void RCC_ClearITPendingBit(uint8_t RCC_IT);
00708 
00709 #ifdef __cplusplus
00710 }
00711 #endif
00712 
00713 #endif /* __STM32F10x_RCC_H */
00714 /**
00715   * @}
00716   */
00717 
00718 /**
00719   * @}
00720   */
00721 
00722 /**
00723   * @}
00724   */ 
00725 
00726 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
STM32F10x Standard Peripherals Library: Footer

 

 

 

      For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit  www.st.com/STM32