stm32f10x_rcc.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_rcc.c
00004   * @author  MCD Application Team
00005   * @version V3.4.0
00006   * @date    10/15/2010
00007   * @brief   This file provides all the RCC firmware functions.
00008   ******************************************************************************
00009   * @copy
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
00019   */ 
00020 
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32f10x_rcc.h"
00023 
00024 /** @addtogroup STM32F10x_StdPeriph_Driver
00025   * @{
00026   */
00027 
00028 /** @defgroup RCC 
00029   * @brief RCC driver modules
00030   * @{
00031   */ 
00032 
00033 /** @defgroup RCC_Private_TypesDefinitions
00034   * @{
00035   */
00036 
00037 /**
00038   * @}
00039   */
00040 
00041 /** @defgroup RCC_Private_Defines
00042   * @{
00043   */
00044 
00045 /* ------------ RCC registers bit address in the alias region ----------- */
00046 #define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
00047 
00048 /* --- CR Register ---*/
00049 
00050 /* Alias word address of HSION bit */
00051 #define CR_OFFSET                 (RCC_OFFSET + 0x00)
00052 #define HSION_BitNumber           0x00
00053 #define CR_HSION_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
00054 
00055 /* Alias word address of PLLON bit */
00056 #define PLLON_BitNumber           0x18
00057 #define CR_PLLON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
00058 
00059 #ifdef STM32F10X_CL
00060  /* Alias word address of PLL2ON bit */
00061  #define PLL2ON_BitNumber          0x1A
00062  #define CR_PLL2ON_BB              (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4))
00063 
00064  /* Alias word address of PLL3ON bit */
00065  #define PLL3ON_BitNumber          0x1C
00066  #define CR_PLL3ON_BB              (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4))
00067 #endif /* STM32F10X_CL */ 
00068 
00069 /* Alias word address of CSSON bit */
00070 #define CSSON_BitNumber           0x13
00071 #define CR_CSSON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
00072 
00073 /* --- CFGR Register ---*/
00074 
00075 /* Alias word address of USBPRE bit */
00076 #define CFGR_OFFSET               (RCC_OFFSET + 0x04)
00077 
00078 #ifndef STM32F10X_CL
00079  #define USBPRE_BitNumber          0x16
00080  #define CFGR_USBPRE_BB            (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
00081 #else
00082  #define OTGFSPRE_BitNumber        0x16
00083  #define CFGR_OTGFSPRE_BB          (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4))
00084 #endif /* STM32F10X_CL */ 
00085 
00086 /* --- BDCR Register ---*/
00087 
00088 /* Alias word address of RTCEN bit */
00089 #define BDCR_OFFSET               (RCC_OFFSET + 0x20)
00090 #define RTCEN_BitNumber           0x0F
00091 #define BDCR_RTCEN_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
00092 
00093 /* Alias word address of BDRST bit */
00094 #define BDRST_BitNumber           0x10
00095 #define BDCR_BDRST_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
00096 
00097 /* --- CSR Register ---*/
00098 
00099 /* Alias word address of LSION bit */
00100 #define CSR_OFFSET                (RCC_OFFSET + 0x24)
00101 #define LSION_BitNumber           0x00
00102 #define CSR_LSION_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
00103 
00104 #ifdef STM32F10X_CL
00105 /* --- CFGR2 Register ---*/
00106 
00107  /* Alias word address of I2S2SRC bit */
00108  #define CFGR2_OFFSET              (RCC_OFFSET + 0x2C)
00109  #define I2S2SRC_BitNumber         0x11
00110  #define CFGR2_I2S2SRC_BB          (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4))
00111 
00112  /* Alias word address of I2S3SRC bit */
00113  #define I2S3SRC_BitNumber         0x12
00114  #define CFGR2_I2S3SRC_BB          (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4))
00115 #endif /* STM32F10X_CL */
00116 
00117 /* ---------------------- RCC registers bit mask ------------------------ */
00118 
00119 /* CR register bit mask */
00120 #define CR_HSEBYP_Reset           ((uint32_t)0xFFFBFFFF)
00121 #define CR_HSEBYP_Set             ((uint32_t)0x00040000)
00122 #define CR_HSEON_Reset            ((uint32_t)0xFFFEFFFF)
00123 #define CR_HSEON_Set              ((uint32_t)0x00010000)
00124 #define CR_HSITRIM_Mask           ((uint32_t)0xFFFFFF07)
00125 
00126 /* CFGR register bit mask */
00127 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) 
00128  #define CFGR_PLL_Mask            ((uint32_t)0xFFC2FFFF)
00129 #else
00130  #define CFGR_PLL_Mask            ((uint32_t)0xFFC0FFFF)
00131 #endif /* STM32F10X_CL */ 
00132 
00133 #define CFGR_PLLMull_Mask         ((uint32_t)0x003C0000)
00134 #define CFGR_PLLSRC_Mask          ((uint32_t)0x00010000)
00135 #define CFGR_PLLXTPRE_Mask        ((uint32_t)0x00020000)
00136 #define CFGR_SWS_Mask             ((uint32_t)0x0000000C)
00137 #define CFGR_SW_Mask              ((uint32_t)0xFFFFFFFC)
00138 #define CFGR_HPRE_Reset_Mask      ((uint32_t)0xFFFFFF0F)
00139 #define CFGR_HPRE_Set_Mask        ((uint32_t)0x000000F0)
00140 #define CFGR_PPRE1_Reset_Mask     ((uint32_t)0xFFFFF8FF)
00141 #define CFGR_PPRE1_Set_Mask       ((uint32_t)0x00000700)
00142 #define CFGR_PPRE2_Reset_Mask     ((uint32_t)0xFFFFC7FF)
00143 #define CFGR_PPRE2_Set_Mask       ((uint32_t)0x00003800)
00144 #define CFGR_ADCPRE_Reset_Mask    ((uint32_t)0xFFFF3FFF)
00145 #define CFGR_ADCPRE_Set_Mask      ((uint32_t)0x0000C000)
00146 
00147 /* CSR register bit mask */
00148 #define CSR_RMVF_Set              ((uint32_t)0x01000000)
00149 
00150 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) 
00151 /* CFGR2 register bit mask */
00152  #define CFGR2_PREDIV1SRC         ((uint32_t)0x00010000)
00153  #define CFGR2_PREDIV1            ((uint32_t)0x0000000F)
00154 #endif
00155 #ifdef STM32F10X_CL
00156  #define CFGR2_PREDIV2            ((uint32_t)0x000000F0)
00157  #define CFGR2_PLL2MUL            ((uint32_t)0x00000F00)
00158  #define CFGR2_PLL3MUL            ((uint32_t)0x0000F000)
00159 #endif /* STM32F10X_CL */ 
00160 
00161 /* RCC Flag Mask */
00162 #define FLAG_Mask                 ((uint8_t)0x1F)
00163 
00164 /* CIR register byte 2 (Bits[15:8]) base address */
00165 #define CIR_BYTE2_ADDRESS         ((uint32_t)0x40021009)
00166 
00167 /* CIR register byte 3 (Bits[23:16]) base address */
00168 #define CIR_BYTE3_ADDRESS         ((uint32_t)0x4002100A)
00169 
00170 /* CFGR register byte 4 (Bits[31:24]) base address */
00171 #define CFGR_BYTE4_ADDRESS        ((uint32_t)0x40021007)
00172 
00173 /* BDCR register base address */
00174 #define BDCR_ADDRESS              (PERIPH_BASE + BDCR_OFFSET)
00175 
00176 /**
00177   * @}
00178   */ 
00179 
00180 /** @defgroup RCC_Private_Macros
00181   * @{
00182   */ 
00183 
00184 /**
00185   * @}
00186   */ 
00187 
00188 /** @defgroup RCC_Private_Variables
00189   * @{
00190   */ 
00191 
00192 static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
00193 static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
00194 
00195 /**
00196   * @}
00197   */
00198 
00199 /** @defgroup RCC_Private_FunctionPrototypes
00200   * @{
00201   */
00202 
00203 /**
00204   * @}
00205   */
00206 
00207 /** @defgroup RCC_Private_Functions
00208   * @{
00209   */
00210 
00211 /**
00212   * @brief  Resets the RCC clock configuration to the default reset state.
00213   * @param  None
00214   * @retval None
00215   */
00216 void RCC_DeInit(void)
00217 {
00218   /* Set HSION bit */
00219   RCC->CR |= (uint32_t)0x00000001;
00220 
00221   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00222 #ifndef STM32F10X_CL
00223   RCC->CFGR &= (uint32_t)0xF8FF0000;
00224 #else
00225   RCC->CFGR &= (uint32_t)0xF0FF0000;
00226 #endif /* STM32F10X_CL */   
00227   
00228   /* Reset HSEON, CSSON and PLLON bits */
00229   RCC->CR &= (uint32_t)0xFEF6FFFF;
00230 
00231   /* Reset HSEBYP bit */
00232   RCC->CR &= (uint32_t)0xFFFBFFFF;
00233 
00234   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00235   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00236 
00237 #ifdef STM32F10X_CL
00238   /* Reset PLL2ON and PLL3ON bits */
00239   RCC->CR &= (uint32_t)0xEBFFFFFF;
00240 
00241   /* Disable all interrupts and clear pending bits  */
00242   RCC->CIR = 0x00FF0000;
00243 
00244   /* Reset CFGR2 register */
00245   RCC->CFGR2 = 0x00000000;
00246 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00247   /* Disable all interrupts and clear pending bits  */
00248   RCC->CIR = 0x009F0000;
00249 
00250   /* Reset CFGR2 register */
00251   RCC->CFGR2 = 0x00000000;      
00252 #else
00253   /* Disable all interrupts and clear pending bits  */
00254   RCC->CIR = 0x009F0000;
00255 #endif /* STM32F10X_CL */
00256 
00257 }
00258 
00259 /**
00260   * @brief  Configures the External High Speed oscillator (HSE).
00261   * @note   HSE can not be stopped if it is used directly or through the PLL as system clock.
00262   * @param  RCC_HSE: specifies the new state of the HSE.
00263   *   This parameter can be one of the following values:
00264   *     @arg RCC_HSE_OFF: HSE oscillator OFF
00265   *     @arg RCC_HSE_ON: HSE oscillator ON
00266   *     @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
00267   * @retval None
00268   */
00269 void RCC_HSEConfig(uint32_t RCC_HSE)
00270 {
00271   /* Check the parameters */
00272   assert_param(IS_RCC_HSE(RCC_HSE));
00273   /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
00274   /* Reset HSEON bit */
00275   RCC->CR &= CR_HSEON_Reset;
00276   /* Reset HSEBYP bit */
00277   RCC->CR &= CR_HSEBYP_Reset;
00278   /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
00279   switch(RCC_HSE)
00280   {
00281     case RCC_HSE_ON:
00282       /* Set HSEON bit */
00283       RCC->CR |= CR_HSEON_Set;
00284       break;
00285       
00286     case RCC_HSE_Bypass:
00287       /* Set HSEBYP and HSEON bits */
00288       RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
00289       break;
00290       
00291     default:
00292       break;
00293   }
00294 }
00295 
00296 /**
00297   * @brief  Waits for HSE start-up.
00298   * @param  None
00299   * @retval An ErrorStatus enumuration value:
00300   * - SUCCESS: HSE oscillator is stable and ready to use
00301   * - ERROR: HSE oscillator not yet ready
00302   */
00303 ErrorStatus RCC_WaitForHSEStartUp(void)
00304 {
00305   __IO uint32_t StartUpCounter = 0;
00306   ErrorStatus status = ERROR;
00307   FlagStatus HSEStatus = RESET;
00308   
00309   /* Wait till HSE is ready and if Time out is reached exit */
00310   do
00311   {
00312     HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
00313     StartUpCounter++;  
00314   } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
00315   
00316   if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
00317   {
00318     status = SUCCESS;
00319   }
00320   else
00321   {
00322     status = ERROR;
00323   }  
00324   return (status);
00325 }
00326 
00327 /**
00328   * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.
00329   * @param  HSICalibrationValue: specifies the calibration trimming value.
00330   *   This parameter must be a number between 0 and 0x1F.
00331   * @retval None
00332   */
00333 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
00334 {
00335   uint32_t tmpreg = 0;
00336   /* Check the parameters */
00337   assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
00338   tmpreg = RCC->CR;
00339   /* Clear HSITRIM[4:0] bits */
00340   tmpreg &= CR_HSITRIM_Mask;
00341   /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
00342   tmpreg |= (uint32_t)HSICalibrationValue << 3;
00343   /* Store the new value */
00344   RCC->CR = tmpreg;
00345 }
00346 
00347 /**
00348   * @brief  Enables or disables the Internal High Speed oscillator (HSI).
00349   * @note   HSI can not be stopped if it is used directly or through the PLL as system clock.
00350   * @param  NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE.
00351   * @retval None
00352   */
00353 void RCC_HSICmd(FunctionalState NewState)
00354 {
00355   /* Check the parameters */
00356   assert_param(IS_FUNCTIONAL_STATE(NewState));
00357   *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
00358 }
00359 
00360 /**
00361   * @brief  Configures the PLL clock source and multiplication factor.
00362   * @note   This function must be used only when the PLL is disabled.
00363   * @param  RCC_PLLSource: specifies the PLL entry clock source.
00364   *   For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices, 
00365   *   this parameter can be one of the following values:
00366   *     @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
00367   *     @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
00368   *   For @b other_STM32_devices, this parameter can be one of the following values:
00369   *     @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
00370   *     @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry
00371   *     @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry 
00372   * @param  RCC_PLLMul: specifies the PLL multiplication factor.
00373   *   For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5}
00374   *   For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16]  
00375   * @retval None
00376   */
00377 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
00378 {
00379   uint32_t tmpreg = 0;
00380 
00381   /* Check the parameters */
00382   assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
00383   assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
00384 
00385   tmpreg = RCC->CFGR;
00386   /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
00387   tmpreg &= CFGR_PLL_Mask;
00388   /* Set the PLL configuration bits */
00389   tmpreg |= RCC_PLLSource | RCC_PLLMul;
00390   /* Store the new value */
00391   RCC->CFGR = tmpreg;
00392 }
00393 
00394 /**
00395   * @brief  Enables or disables the PLL.
00396   * @note   The PLL can not be disabled if it is used as system clock.
00397   * @param  NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE.
00398   * @retval None
00399   */
00400 void RCC_PLLCmd(FunctionalState NewState)
00401 {
00402   /* Check the parameters */
00403   assert_param(IS_FUNCTIONAL_STATE(NewState));
00404 
00405   *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
00406 }
00407 
00408 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
00409 /**
00410   * @brief  Configures the PREDIV1 division factor.
00411   * @note 
00412   *   - This function must be used only when the PLL is disabled.
00413   *   - This function applies only to STM32 Connectivity line and Value line 
00414   *     devices.
00415   * @param  RCC_PREDIV1_Source: specifies the PREDIV1 clock source.
00416   *   This parameter can be one of the following values:
00417   *     @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock
00418   *     @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock
00419   * @note 
00420   *   For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE  
00421   * @param  RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
00422   *   This parameter can be RCC_PREDIV1_Divx where x:[1,16]
00423   * @retval None
00424   */
00425 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div)
00426 {
00427   uint32_t tmpreg = 0;
00428   
00429   /* Check the parameters */
00430   assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source));
00431   assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
00432 
00433   tmpreg = RCC->CFGR2;
00434   /* Clear PREDIV1[3:0] and PREDIV1SRC bits */
00435   tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC);
00436   /* Set the PREDIV1 clock source and division factor */
00437   tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ;
00438   /* Store the new value */
00439   RCC->CFGR2 = tmpreg;
00440 }
00441 #endif
00442 
00443 #ifdef STM32F10X_CL
00444 /**
00445   * @brief  Configures the PREDIV2 division factor.
00446   * @note 
00447   *   - This function must be used only when both PLL2 and PLL3 are disabled.
00448   *   - This function applies only to STM32 Connectivity line devices.
00449   * @param  RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor.
00450   *   This parameter can be RCC_PREDIV2_Divx where x:[1,16]
00451   * @retval None
00452   */
00453 void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div)
00454 {
00455   uint32_t tmpreg = 0;
00456 
00457   /* Check the parameters */
00458   assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div));
00459 
00460   tmpreg = RCC->CFGR2;
00461   /* Clear PREDIV2[3:0] bits */
00462   tmpreg &= ~CFGR2_PREDIV2;
00463   /* Set the PREDIV2 division factor */
00464   tmpreg |= RCC_PREDIV2_Div;
00465   /* Store the new value */
00466   RCC->CFGR2 = tmpreg;
00467 }
00468 
00469 /**
00470   * @brief  Configures the PLL2 multiplication factor.
00471   * @note
00472   *   - This function must be used only when the PLL2 is disabled.
00473   *   - This function applies only to STM32 Connectivity line devices.
00474   * @param  RCC_PLL2Mul: specifies the PLL2 multiplication factor.
00475   *   This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}
00476   * @retval None
00477   */
00478 void RCC_PLL2Config(uint32_t RCC_PLL2Mul)
00479 {
00480   uint32_t tmpreg = 0;
00481 
00482   /* Check the parameters */
00483   assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul));
00484 
00485   tmpreg = RCC->CFGR2;
00486   /* Clear PLL2Mul[3:0] bits */
00487   tmpreg &= ~CFGR2_PLL2MUL;
00488   /* Set the PLL2 configuration bits */
00489   tmpreg |= RCC_PLL2Mul;
00490   /* Store the new value */
00491   RCC->CFGR2 = tmpreg;
00492 }
00493 
00494 
00495 /**
00496   * @brief  Enables or disables the PLL2.
00497   * @note 
00498   *   - The PLL2 can not be disabled if it is used indirectly as system clock
00499   *     (i.e. it is used as PLL clock entry that is used as System clock).
00500   *   - This function applies only to STM32 Connectivity line devices.
00501   * @param  NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE.
00502   * @retval None
00503   */
00504 void RCC_PLL2Cmd(FunctionalState NewState)
00505 {
00506   /* Check the parameters */
00507   assert_param(IS_FUNCTIONAL_STATE(NewState));
00508 
00509   *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState;
00510 }
00511 
00512 
00513 /**
00514   * @brief  Configures the PLL3 multiplication factor.
00515   * @note 
00516   *   - This function must be used only when the PLL3 is disabled.
00517   *   - This function applies only to STM32 Connectivity line devices.
00518   * @param  RCC_PLL3Mul: specifies the PLL3 multiplication factor.
00519   *   This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20}
00520   * @retval None
00521   */
00522 void RCC_PLL3Config(uint32_t RCC_PLL3Mul)
00523 {
00524   uint32_t tmpreg = 0;
00525 
00526   /* Check the parameters */
00527   assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul));
00528 
00529   tmpreg = RCC->CFGR2;
00530   /* Clear PLL3Mul[3:0] bits */
00531   tmpreg &= ~CFGR2_PLL3MUL;
00532   /* Set the PLL3 configuration bits */
00533   tmpreg |= RCC_PLL3Mul;
00534   /* Store the new value */
00535   RCC->CFGR2 = tmpreg;
00536 }
00537 
00538 
00539 /**
00540   * @brief  Enables or disables the PLL3.
00541   * @note   This function applies only to STM32 Connectivity line devices.
00542   * @param  NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE.
00543   * @retval None
00544   */
00545 void RCC_PLL3Cmd(FunctionalState NewState)
00546 {
00547   /* Check the parameters */
00548 
00549   assert_param(IS_FUNCTIONAL_STATE(NewState));
00550   *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState;
00551 }
00552 #endif /* STM32F10X_CL */
00553 
00554 /**
00555   * @brief  Configures the system clock (SYSCLK).
00556   * @param  RCC_SYSCLKSource: specifies the clock source used as system clock.
00557   *   This parameter can be one of the following values:
00558   *     @arg RCC_SYSCLKSource_HSI: HSI selected as system clock
00559   *     @arg RCC_SYSCLKSource_HSE: HSE selected as system clock
00560   *     @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
00561   * @retval None
00562   */
00563 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
00564 {
00565   uint32_t tmpreg = 0;
00566   /* Check the parameters */
00567   assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
00568   tmpreg = RCC->CFGR;
00569   /* Clear SW[1:0] bits */
00570   tmpreg &= CFGR_SW_Mask;
00571   /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
00572   tmpreg |= RCC_SYSCLKSource;
00573   /* Store the new value */
00574   RCC->CFGR = tmpreg;
00575 }
00576 
00577 /**
00578   * @brief  Returns the clock source used as system clock.
00579   * @param  None
00580   * @retval The clock source used as system clock. The returned value can
00581   *   be one of the following:
00582   *     - 0x00: HSI used as system clock
00583   *     - 0x04: HSE used as system clock
00584   *     - 0x08: PLL used as system clock
00585   */
00586 uint8_t RCC_GetSYSCLKSource(void)
00587 {
00588   return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
00589 }
00590 
00591 /**
00592   * @brief  Configures the AHB clock (HCLK).
00593   * @param  RCC_SYSCLK: defines the AHB clock divider. This clock is derived from 
00594   *   the system clock (SYSCLK).
00595   *   This parameter can be one of the following values:
00596   *     @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
00597   *     @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
00598   *     @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
00599   *     @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
00600   *     @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
00601   *     @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
00602   *     @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
00603   *     @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
00604   *     @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
00605   * @retval None
00606   */
00607 void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
00608 {
00609   uint32_t tmpreg = 0;
00610   /* Check the parameters */
00611   assert_param(IS_RCC_HCLK(RCC_SYSCLK));
00612   tmpreg = RCC->CFGR;
00613   /* Clear HPRE[3:0] bits */
00614   tmpreg &= CFGR_HPRE_Reset_Mask;
00615   /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
00616   tmpreg |= RCC_SYSCLK;
00617   /* Store the new value */
00618   RCC->CFGR = tmpreg;
00619 }
00620 
00621 /**
00622   * @brief  Configures the Low Speed APB clock (PCLK1).
00623   * @param  RCC_HCLK: defines the APB1 clock divider. This clock is derived from 
00624   *   the AHB clock (HCLK).
00625   *   This parameter can be one of the following values:
00626   *     @arg RCC_HCLK_Div1: APB1 clock = HCLK
00627   *     @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
00628   *     @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
00629   *     @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
00630   *     @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
00631   * @retval None
00632   */
00633 void RCC_PCLK1Config(uint32_t RCC_HCLK)
00634 {
00635   uint32_t tmpreg = 0;
00636   /* Check the parameters */
00637   assert_param(IS_RCC_PCLK(RCC_HCLK));
00638   tmpreg = RCC->CFGR;
00639   /* Clear PPRE1[2:0] bits */
00640   tmpreg &= CFGR_PPRE1_Reset_Mask;
00641   /* Set PPRE1[2:0] bits according to RCC_HCLK value */
00642   tmpreg |= RCC_HCLK;
00643   /* Store the new value */
00644   RCC->CFGR = tmpreg;
00645 }
00646 
00647 /**
00648   * @brief  Configures the High Speed APB clock (PCLK2).
00649   * @param  RCC_HCLK: defines the APB2 clock divider. This clock is derived from 
00650   *   the AHB clock (HCLK).
00651   *   This parameter can be one of the following values:
00652   *     @arg RCC_HCLK_Div1: APB2 clock = HCLK
00653   *     @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
00654   *     @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
00655   *     @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
00656   *     @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
00657   * @retval None
00658   */
00659 void RCC_PCLK2Config(uint32_t RCC_HCLK)
00660 {
00661   uint32_t tmpreg = 0;
00662   /* Check the parameters */
00663   assert_param(IS_RCC_PCLK(RCC_HCLK));
00664   tmpreg = RCC->CFGR;
00665   /* Clear PPRE2[2:0] bits */
00666   tmpreg &= CFGR_PPRE2_Reset_Mask;
00667   /* Set PPRE2[2:0] bits according to RCC_HCLK value */
00668   tmpreg |= RCC_HCLK << 3;
00669   /* Store the new value */
00670   RCC->CFGR = tmpreg;
00671 }
00672 
00673 /**
00674   * @brief  Enables or disables the specified RCC interrupts.
00675   * @param  RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
00676   * 
00677   *   For @b STM32_Connectivity_line_devices, this parameter can be any combination
00678   *   of the following values        
00679   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
00680   *     @arg RCC_IT_LSERDY: LSE ready interrupt
00681   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
00682   *     @arg RCC_IT_HSERDY: HSE ready interrupt
00683   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
00684   *     @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
00685   *     @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
00686   * 
00687   *   For @b other_STM32_devices, this parameter can be any combination of the 
00688   *   following values        
00689   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
00690   *     @arg RCC_IT_LSERDY: LSE ready interrupt
00691   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
00692   *     @arg RCC_IT_HSERDY: HSE ready interrupt
00693   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
00694   *       
00695   * @param  NewState: new state of the specified RCC interrupts.
00696   *   This parameter can be: ENABLE or DISABLE.
00697   * @retval None
00698   */
00699 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
00700 {
00701   /* Check the parameters */
00702   assert_param(IS_RCC_IT(RCC_IT));
00703   assert_param(IS_FUNCTIONAL_STATE(NewState));
00704   if (NewState != DISABLE)
00705   {
00706     /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */
00707     *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
00708   }
00709   else
00710   {
00711     /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */
00712     *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
00713   }
00714 }
00715 
00716 #ifndef STM32F10X_CL
00717 /**
00718   * @brief  Configures the USB clock (USBCLK).
00719   * @param  RCC_USBCLKSource: specifies the USB clock source. This clock is 
00720   *   derived from the PLL output.
00721   *   This parameter can be one of the following values:
00722   *     @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB 
00723   *                                     clock source
00724   *     @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
00725   * @retval None
00726   */
00727 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
00728 {
00729   /* Check the parameters */
00730   assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
00731 
00732   *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
00733 }
00734 #else
00735 /**
00736   * @brief  Configures the USB OTG FS clock (OTGFSCLK).
00737   *   This function applies only to STM32 Connectivity line devices.
00738   * @param  RCC_OTGFSCLKSource: specifies the USB OTG FS clock source.
00739   *   This clock is derived from the PLL output.
00740   *   This parameter can be one of the following values:
00741   *     @arg  RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source
00742   *     @arg  RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source
00743   * @retval None
00744   */
00745 void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource)
00746 {
00747   /* Check the parameters */
00748   assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource));
00749 
00750   *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource;
00751 }
00752 #endif /* STM32F10X_CL */ 
00753 
00754 /**
00755   * @brief  Configures the ADC clock (ADCCLK).
00756   * @param  RCC_PCLK2: defines the ADC clock divider. This clock is derived from 
00757   *   the APB2 clock (PCLK2).
00758   *   This parameter can be one of the following values:
00759   *     @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2
00760   *     @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4
00761   *     @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6
00762   *     @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8
00763   * @retval None
00764   */
00765 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
00766 {
00767   uint32_t tmpreg = 0;
00768   /* Check the parameters */
00769   assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
00770   tmpreg = RCC->CFGR;
00771   /* Clear ADCPRE[1:0] bits */
00772   tmpreg &= CFGR_ADCPRE_Reset_Mask;
00773   /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
00774   tmpreg |= RCC_PCLK2;
00775   /* Store the new value */
00776   RCC->CFGR = tmpreg;
00777 }
00778 
00779 #ifdef STM32F10X_CL
00780 /**
00781   * @brief  Configures the I2S2 clock source(I2S2CLK).
00782   * @note
00783   *   - This function must be called before enabling I2S2 APB clock.
00784   *   - This function applies only to STM32 Connectivity line devices.
00785   * @param  RCC_I2S2CLKSource: specifies the I2S2 clock source.
00786   *   This parameter can be one of the following values:
00787   *     @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry
00788   *     @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry
00789   * @retval None
00790   */
00791 void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource)
00792 {
00793   /* Check the parameters */
00794   assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource));
00795 
00796   *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource;
00797 }
00798 
00799 /**
00800   * @brief  Configures the I2S3 clock source(I2S2CLK).
00801   * @note
00802   *   - This function must be called before enabling I2S3 APB clock.
00803   *   - This function applies only to STM32 Connectivity line devices.
00804   * @param  RCC_I2S3CLKSource: specifies the I2S3 clock source.
00805   *   This parameter can be one of the following values:
00806   *     @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry
00807   *     @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry
00808   * @retval None
00809   */
00810 void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource)
00811 {
00812   /* Check the parameters */
00813   assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource));
00814 
00815   *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource;
00816 }
00817 #endif /* STM32F10X_CL */
00818 
00819 /**
00820   * @brief  Configures the External Low Speed oscillator (LSE).
00821   * @param  RCC_LSE: specifies the new state of the LSE.
00822   *   This parameter can be one of the following values:
00823   *     @arg RCC_LSE_OFF: LSE oscillator OFF
00824   *     @arg RCC_LSE_ON: LSE oscillator ON
00825   *     @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
00826   * @retval None
00827   */
00828 void RCC_LSEConfig(uint8_t RCC_LSE)
00829 {
00830   /* Check the parameters */
00831   assert_param(IS_RCC_LSE(RCC_LSE));
00832   /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
00833   /* Reset LSEON bit */
00834   *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
00835   /* Reset LSEBYP bit */
00836   *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
00837   /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
00838   switch(RCC_LSE)
00839   {
00840     case RCC_LSE_ON:
00841       /* Set LSEON bit */
00842       *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
00843       break;
00844       
00845     case RCC_LSE_Bypass:
00846       /* Set LSEBYP and LSEON bits */
00847       *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
00848       break;            
00849       
00850     default:
00851       break;      
00852   }
00853 }
00854 
00855 /**
00856   * @brief  Enables or disables the Internal Low Speed oscillator (LSI).
00857   * @note   LSI can not be disabled if the IWDG is running.
00858   * @param  NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE.
00859   * @retval None
00860   */
00861 void RCC_LSICmd(FunctionalState NewState)
00862 {
00863   /* Check the parameters */
00864   assert_param(IS_FUNCTIONAL_STATE(NewState));
00865   *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
00866 }
00867 
00868 /**
00869   * @brief  Configures the RTC clock (RTCCLK).
00870   * @note   Once the RTC clock is selected it canít be changed unless the Backup domain is reset.
00871   * @param  RCC_RTCCLKSource: specifies the RTC clock source.
00872   *   This parameter can be one of the following values:
00873   *     @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
00874   *     @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
00875   *     @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock
00876   * @retval None
00877   */
00878 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
00879 {
00880   /* Check the parameters */
00881   assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
00882   /* Select the RTC clock source */
00883   RCC->BDCR |= RCC_RTCCLKSource;
00884 }
00885 
00886 /**
00887   * @brief  Enables or disables the RTC clock.
00888   * @note   This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.
00889   * @param  NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
00890   * @retval None
00891   */
00892 void RCC_RTCCLKCmd(FunctionalState NewState)
00893 {
00894   /* Check the parameters */
00895   assert_param(IS_FUNCTIONAL_STATE(NewState));
00896   *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
00897 }
00898 
00899 /**
00900   * @brief  Returns the frequencies of different on chip clocks.
00901   * @param  RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
00902   *         the clocks frequencies.
00903   * @note   The result of this function could be not correct when using 
00904   *         fractional value for HSE crystal.  
00905   * @retval None
00906   */
00907 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
00908 {
00909   uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
00910 
00911 #ifdef  STM32F10X_CL
00912   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00913 #endif /* STM32F10X_CL */
00914 
00915 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00916   uint32_t prediv1factor = 0;
00917 #endif
00918     
00919   /* Get SYSCLK source -------------------------------------------------------*/
00920   tmp = RCC->CFGR & CFGR_SWS_Mask;
00921   
00922   switch (tmp)
00923   {
00924     case 0x00:  /* HSI used as system clock */
00925       RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
00926       break;
00927     case 0x04:  /* HSE used as system clock */
00928       RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
00929       break;
00930     case 0x08:  /* PLL used as system clock */
00931 
00932       /* Get PLL clock source and multiplication factor ----------------------*/
00933       pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
00934       pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
00935       
00936 #ifndef STM32F10X_CL      
00937       pllmull = ( pllmull >> 18) + 2;
00938       
00939       if (pllsource == 0x00)
00940       {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
00941         RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
00942       }
00943       else
00944       {
00945  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00946        prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
00947        /* HSE oscillator clock selected as PREDIV1 clock entry */
00948        RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; 
00949  #else
00950         /* HSE selected as PLL clock entry */
00951         if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
00952         {/* HSE oscillator clock divided by 2 */
00953           RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
00954         }
00955         else
00956         {
00957           RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
00958         }
00959  #endif
00960       }
00961 #else
00962       pllmull = pllmull >> 18;
00963       
00964       if (pllmull != 0x0D)
00965       {
00966          pllmull += 2;
00967       }
00968       else
00969       { /* PLL multiplication factor = PLL input clock * 6.5 */
00970         pllmull = 13 / 2; 
00971       }
00972             
00973       if (pllsource == 0x00)
00974       {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
00975         RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
00976       }
00977       else
00978       {/* PREDIV1 selected as PLL clock entry */
00979         
00980         /* Get PREDIV1 clock source and division factor */
00981         prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;
00982         prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
00983         
00984         if (prediv1source == 0)
00985         { /* HSE oscillator clock selected as PREDIV1 clock entry */
00986           RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull;          
00987         }
00988         else
00989         {/* PLL2 clock selected as PREDIV1 clock entry */
00990           
00991           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00992           prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;
00993           pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; 
00994           RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
00995         }
00996       }
00997 #endif /* STM32F10X_CL */ 
00998       break;
00999 
01000     default:
01001       RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
01002       break;
01003   }
01004 
01005   /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
01006   /* Get HCLK prescaler */
01007   tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
01008   tmp = tmp >> 4;
01009   presc = APBAHBPrescTable[tmp];
01010   /* HCLK clock frequency */
01011   RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
01012   /* Get PCLK1 prescaler */
01013   tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
01014   tmp = tmp >> 8;
01015   presc = APBAHBPrescTable[tmp];
01016   /* PCLK1 clock frequency */
01017   RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
01018   /* Get PCLK2 prescaler */
01019   tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
01020   tmp = tmp >> 11;
01021   presc = APBAHBPrescTable[tmp];
01022   /* PCLK2 clock frequency */
01023   RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
01024   /* Get ADCCLK prescaler */
01025   tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
01026   tmp = tmp >> 14;
01027   presc = ADCPrescTable[tmp];
01028   /* ADCCLK clock frequency */
01029   RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
01030 }
01031 
01032 /**
01033   * @brief  Enables or disables the AHB peripheral clock.
01034   * @param  RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
01035   *   
01036   *   For @b STM32_Connectivity_line_devices, this parameter can be any combination
01037   *   of the following values:        
01038   *     @arg RCC_AHBPeriph_DMA1
01039   *     @arg RCC_AHBPeriph_DMA2
01040   *     @arg RCC_AHBPeriph_SRAM
01041   *     @arg RCC_AHBPeriph_FLITF
01042   *     @arg RCC_AHBPeriph_CRC
01043   *     @arg RCC_AHBPeriph_OTG_FS    
01044   *     @arg RCC_AHBPeriph_ETH_MAC   
01045   *     @arg RCC_AHBPeriph_ETH_MAC_Tx
01046   *     @arg RCC_AHBPeriph_ETH_MAC_Rx
01047   * 
01048   *   For @b other_STM32_devices, this parameter can be any combination of the 
01049   *   following values:        
01050   *     @arg RCC_AHBPeriph_DMA1
01051   *     @arg RCC_AHBPeriph_DMA2
01052   *     @arg RCC_AHBPeriph_SRAM
01053   *     @arg RCC_AHBPeriph_FLITF
01054   *     @arg RCC_AHBPeriph_CRC
01055   *     @arg RCC_AHBPeriph_FSMC
01056   *     @arg RCC_AHBPeriph_SDIO
01057   *   
01058   * @note SRAM and FLITF clock can be disabled only during sleep mode.
01059   * @param  NewState: new state of the specified peripheral clock.
01060   *   This parameter can be: ENABLE or DISABLE.
01061   * @retval None
01062   */
01063 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
01064 {
01065   /* Check the parameters */
01066   assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
01067   assert_param(IS_FUNCTIONAL_STATE(NewState));
01068 
01069   if (NewState != DISABLE)
01070   {
01071     RCC->AHBENR |= RCC_AHBPeriph;
01072   }
01073   else
01074   {
01075     RCC->AHBENR &= ~RCC_AHBPeriph;
01076   }
01077 }
01078 
01079 /**
01080   * @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
01081   * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
01082   *   This parameter can be any combination of the following values:
01083   *     @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
01084   *          RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
01085   *          RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
01086   *          RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
01087   *          RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
01088   *          RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,
01089   *          RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11     
01090   * @param  NewState: new state of the specified peripheral clock.
01091   *   This parameter can be: ENABLE or DISABLE.
01092   * @retval None
01093   */
01094 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
01095 {
01096   /* Check the parameters */
01097   assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
01098   assert_param(IS_FUNCTIONAL_STATE(NewState));
01099   if (NewState != DISABLE)
01100   {
01101     RCC->APB2ENR |= RCC_APB2Periph;
01102   }
01103   else
01104   {
01105     RCC->APB2ENR &= ~RCC_APB2Periph;
01106   }
01107 }
01108 
01109 /**
01110   * @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
01111   * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
01112   *   This parameter can be any combination of the following values:
01113   *     @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
01114   *          RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
01115   *          RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
01116   *          RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, 
01117   *          RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
01118   *          RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
01119   *          RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,
01120   *          RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
01121   * @param  NewState: new state of the specified peripheral clock.
01122   *   This parameter can be: ENABLE or DISABLE.
01123   * @retval None
01124   */
01125 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
01126 {
01127   /* Check the parameters */
01128   assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
01129   assert_param(IS_FUNCTIONAL_STATE(NewState));
01130   if (NewState != DISABLE)
01131   {
01132     RCC->APB1ENR |= RCC_APB1Periph;
01133   }
01134   else
01135   {
01136     RCC->APB1ENR &= ~RCC_APB1Periph;
01137   }
01138 }
01139 
01140 #ifdef STM32F10X_CL
01141 /**
01142   * @brief  Forces or releases AHB peripheral reset.
01143   * @note   This function applies only to STM32 Connectivity line devices.
01144   * @param  RCC_AHBPeriph: specifies the AHB peripheral to reset.
01145   *   This parameter can be any combination of the following values:
01146   *     @arg RCC_AHBPeriph_OTG_FS 
01147   *     @arg RCC_AHBPeriph_ETH_MAC
01148   * @param  NewState: new state of the specified peripheral reset.
01149   *   This parameter can be: ENABLE or DISABLE.
01150   * @retval None
01151   */
01152 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
01153 {
01154   /* Check the parameters */
01155   assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph));
01156   assert_param(IS_FUNCTIONAL_STATE(NewState));
01157 
01158   if (NewState != DISABLE)
01159   {
01160     RCC->AHBRSTR |= RCC_AHBPeriph;
01161   }
01162   else
01163   {
01164     RCC->AHBRSTR &= ~RCC_AHBPeriph;
01165   }
01166 }
01167 #endif /* STM32F10X_CL */ 
01168 
01169 /**
01170   * @brief  Forces or releases High Speed APB (APB2) peripheral reset.
01171   * @param  RCC_APB2Periph: specifies the APB2 peripheral to reset.
01172   *   This parameter can be any combination of the following values:
01173   *     @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
01174   *          RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
01175   *          RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
01176   *          RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
01177   *          RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
01178   *          RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,
01179   *          RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11  
01180   * @param  NewState: new state of the specified peripheral reset.
01181   *   This parameter can be: ENABLE or DISABLE.
01182   * @retval None
01183   */
01184 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
01185 {
01186   /* Check the parameters */
01187   assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
01188   assert_param(IS_FUNCTIONAL_STATE(NewState));
01189   if (NewState != DISABLE)
01190   {
01191     RCC->APB2RSTR |= RCC_APB2Periph;
01192   }
01193   else
01194   {
01195     RCC->APB2RSTR &= ~RCC_APB2Periph;
01196   }
01197 }
01198 
01199 /**
01200   * @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
01201   * @param  RCC_APB1Periph: specifies the APB1 peripheral to reset.
01202   *   This parameter can be any combination of the following values:
01203   *     @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
01204   *          RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
01205   *          RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
01206   *          RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, 
01207   *          RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
01208   *          RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
01209   *          RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,
01210   *          RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14  
01211   * @param  NewState: new state of the specified peripheral clock.
01212   *   This parameter can be: ENABLE or DISABLE.
01213   * @retval None
01214   */
01215 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
01216 {
01217   /* Check the parameters */
01218   assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
01219   assert_param(IS_FUNCTIONAL_STATE(NewState));
01220   if (NewState != DISABLE)
01221   {
01222     RCC->APB1RSTR |= RCC_APB1Periph;
01223   }
01224   else
01225   {
01226     RCC->APB1RSTR &= ~RCC_APB1Periph;
01227   }
01228 }
01229 
01230 /**
01231   * @brief  Forces or releases the Backup domain reset.
01232   * @param  NewState: new state of the Backup domain reset.
01233   *   This parameter can be: ENABLE or DISABLE.
01234   * @retval None
01235   */
01236 void RCC_BackupResetCmd(FunctionalState NewState)
01237 {
01238   /* Check the parameters */
01239   assert_param(IS_FUNCTIONAL_STATE(NewState));
01240   *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
01241 }
01242 
01243 /**
01244   * @brief  Enables or disables the Clock Security System.
01245   * @param  NewState: new state of the Clock Security System..
01246   *   This parameter can be: ENABLE or DISABLE.
01247   * @retval None
01248   */
01249 void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
01250 {
01251   /* Check the parameters */
01252   assert_param(IS_FUNCTIONAL_STATE(NewState));
01253   *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
01254 }
01255 
01256 /**
01257   * @brief  Selects the clock source to output on MCO pin.
01258   * @param  RCC_MCO: specifies the clock source to output.
01259   *   
01260   *   For @b STM32_Connectivity_line_devices, this parameter can be one of the
01261   *   following values:       
01262   *     @arg RCC_MCO_NoClock: No clock selected
01263   *     @arg RCC_MCO_SYSCLK: System clock selected
01264   *     @arg RCC_MCO_HSI: HSI oscillator clock selected
01265   *     @arg RCC_MCO_HSE: HSE oscillator clock selected
01266   *     @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
01267   *     @arg RCC_MCO_PLL2CLK: PLL2 clock selected                     
01268   *     @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected   
01269   *     @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected  
01270   *     @arg RCC_MCO_PLL3CLK: PLL3 clock selected 
01271   * 
01272   *   For  @b other_STM32_devices, this parameter can be one of the following values:        
01273   *     @arg RCC_MCO_NoClock: No clock selected
01274   *     @arg RCC_MCO_SYSCLK: System clock selected
01275   *     @arg RCC_MCO_HSI: HSI oscillator clock selected
01276   *     @arg RCC_MCO_HSE: HSE oscillator clock selected
01277   *     @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
01278   *   
01279   * @retval None
01280   */
01281 void RCC_MCOConfig(uint8_t RCC_MCO)
01282 {
01283   /* Check the parameters */
01284   assert_param(IS_RCC_MCO(RCC_MCO));
01285 
01286   /* Perform Byte access to MCO bits to select the MCO source */
01287   *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO;
01288 }
01289 
01290 /**
01291   * @brief  Checks whether the specified RCC flag is set or not.
01292   * @param  RCC_FLAG: specifies the flag to check.
01293   *   
01294   *   For @b STM32_Connectivity_line_devices, this parameter can be one of the
01295   *   following values:
01296   *     @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
01297   *     @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
01298   *     @arg RCC_FLAG_PLLRDY: PLL clock ready
01299   *     @arg RCC_FLAG_PLL2RDY: PLL2 clock ready      
01300   *     @arg RCC_FLAG_PLL3RDY: PLL3 clock ready                           
01301   *     @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
01302   *     @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
01303   *     @arg RCC_FLAG_PINRST: Pin reset
01304   *     @arg RCC_FLAG_PORRST: POR/PDR reset
01305   *     @arg RCC_FLAG_SFTRST: Software reset
01306   *     @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
01307   *     @arg RCC_FLAG_WWDGRST: Window Watchdog reset
01308   *     @arg RCC_FLAG_LPWRRST: Low Power reset
01309   * 
01310   *   For @b other_STM32_devices, this parameter can be one of the following values:        
01311   *     @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
01312   *     @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
01313   *     @arg RCC_FLAG_PLLRDY: PLL clock ready
01314   *     @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
01315   *     @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
01316   *     @arg RCC_FLAG_PINRST: Pin reset
01317   *     @arg RCC_FLAG_PORRST: POR/PDR reset
01318   *     @arg RCC_FLAG_SFTRST: Software reset
01319   *     @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
01320   *     @arg RCC_FLAG_WWDGRST: Window Watchdog reset
01321   *     @arg RCC_FLAG_LPWRRST: Low Power reset
01322   *   
01323   * @retval The new state of RCC_FLAG (SET or RESET).
01324   */
01325 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
01326 {
01327   uint32_t tmp = 0;
01328   uint32_t statusreg = 0;
01329   FlagStatus bitstatus = RESET;
01330   /* Check the parameters */
01331   assert_param(IS_RCC_FLAG(RCC_FLAG));
01332 
01333   /* Get the RCC register index */
01334   tmp = RCC_FLAG >> 5;
01335   if (tmp == 1)               /* The flag to check is in CR register */
01336   {
01337     statusreg = RCC->CR;
01338   }
01339   else if (tmp == 2)          /* The flag to check is in BDCR register */
01340   {
01341     statusreg = RCC->BDCR;
01342   }
01343   else                       /* The flag to check is in CSR register */
01344   {
01345     statusreg = RCC->CSR;
01346   }
01347 
01348   /* Get the flag position */
01349   tmp = RCC_FLAG & FLAG_Mask;
01350   if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
01351   {
01352     bitstatus = SET;
01353   }
01354   else
01355   {
01356     bitstatus = RESET;
01357   }
01358 
01359   /* Return the flag status */
01360   return bitstatus;
01361 }
01362 
01363 /**
01364   * @brief  Clears the RCC reset flags.
01365   * @note   The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
01366   *   RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
01367   * @param  None
01368   * @retval None
01369   */
01370 void RCC_ClearFlag(void)
01371 {
01372   /* Set RMVF bit to clear the reset flags */
01373   RCC->CSR |= CSR_RMVF_Set;
01374 }
01375 
01376 /**
01377   * @brief  Checks whether the specified RCC interrupt has occurred or not.
01378   * @param  RCC_IT: specifies the RCC interrupt source to check.
01379   *   
01380   *   For @b STM32_Connectivity_line_devices, this parameter can be one of the
01381   *   following values:
01382   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
01383   *     @arg RCC_IT_LSERDY: LSE ready interrupt
01384   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
01385   *     @arg RCC_IT_HSERDY: HSE ready interrupt
01386   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
01387   *     @arg RCC_IT_PLL2RDY: PLL2 ready interrupt 
01388   *     @arg RCC_IT_PLL3RDY: PLL3 ready interrupt                      
01389   *     @arg RCC_IT_CSS: Clock Security System interrupt
01390   * 
01391   *   For @b other_STM32_devices, this parameter can be one of the following values:        
01392   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
01393   *     @arg RCC_IT_LSERDY: LSE ready interrupt
01394   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
01395   *     @arg RCC_IT_HSERDY: HSE ready interrupt
01396   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
01397   *     @arg RCC_IT_CSS: Clock Security System interrupt
01398   *   
01399   * @retval The new state of RCC_IT (SET or RESET).
01400   */
01401 ITStatus RCC_GetITStatus(uint8_t RCC_IT)
01402 {
01403   ITStatus bitstatus = RESET;
01404   /* Check the parameters */
01405   assert_param(IS_RCC_GET_IT(RCC_IT));
01406 
01407   /* Check the status of the specified RCC interrupt */
01408   if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
01409   {
01410     bitstatus = SET;
01411   }
01412   else
01413   {
01414     bitstatus = RESET;
01415   }
01416 
01417   /* Return the RCC_IT status */
01418   return  bitstatus;
01419 }
01420 
01421 /**
01422   * @brief  Clears the RCCís interrupt pending bits.
01423   * @param  RCC_IT: specifies the interrupt pending bit to clear.
01424   *   
01425   *   For @b STM32_Connectivity_line_devices, this parameter can be any combination
01426   *   of the following values:
01427   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
01428   *     @arg RCC_IT_LSERDY: LSE ready interrupt
01429   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
01430   *     @arg RCC_IT_HSERDY: HSE ready interrupt
01431   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
01432   *     @arg RCC_IT_PLL2RDY: PLL2 ready interrupt 
01433   *     @arg RCC_IT_PLL3RDY: PLL3 ready interrupt                      
01434   *     @arg RCC_IT_CSS: Clock Security System interrupt
01435   * 
01436   *   For @b other_STM32_devices, this parameter can be any combination of the
01437   *   following values:        
01438   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
01439   *     @arg RCC_IT_LSERDY: LSE ready interrupt
01440   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
01441   *     @arg RCC_IT_HSERDY: HSE ready interrupt
01442   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
01443   *   
01444   *     @arg RCC_IT_CSS: Clock Security System interrupt
01445   * @retval None
01446   */
01447 void RCC_ClearITPendingBit(uint8_t RCC_IT)
01448 {
01449   /* Check the parameters */
01450   assert_param(IS_RCC_CLEAR_IT(RCC_IT));
01451 
01452   /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
01453      pending bits */
01454   *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
01455 }
01456 
01457 /**
01458   * @}
01459   */
01460 
01461 /**
01462   * @}
01463   */
01464 
01465 /**
01466   * @}
01467   */
01468 
01469 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
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