stm32f10x_pwr.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_pwr.c
00004   * @author  MCD Application Team
00005   * @version V3.4.0
00006   * @date    10/15/2010
00007   * @brief   This file provides all the PWR firmware functions.
00008   ******************************************************************************
00009   * @copy
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
00019   */ 
00020 
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32f10x_pwr.h"
00023 #include "stm32f10x_rcc.h"
00024 
00025 /** @addtogroup STM32F10x_StdPeriph_Driver
00026   * @{
00027   */
00028 
00029 /** @defgroup PWR 
00030   * @brief PWR driver modules
00031   * @{
00032   */ 
00033 
00034 /** @defgroup PWR_Private_TypesDefinitions
00035   * @{
00036   */
00037 
00038 /**
00039   * @}
00040   */
00041 
00042 /** @defgroup PWR_Private_Defines
00043   * @{
00044   */
00045 
00046 /* --------- PWR registers bit address in the alias region ---------- */
00047 #define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
00048 
00049 /* --- CR Register ---*/
00050 
00051 /* Alias word address of DBP bit */
00052 #define CR_OFFSET                (PWR_OFFSET + 0x00)
00053 #define DBP_BitNumber            0x08
00054 #define CR_DBP_BB                (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
00055 
00056 /* Alias word address of PVDE bit */
00057 #define PVDE_BitNumber           0x04
00058 #define CR_PVDE_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
00059 
00060 /* --- CSR Register ---*/
00061 
00062 /* Alias word address of EWUP bit */
00063 #define CSR_OFFSET               (PWR_OFFSET + 0x04)
00064 #define EWUP_BitNumber           0x08
00065 #define CSR_EWUP_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
00066 
00067 /* ------------------ PWR registers bit mask ------------------------ */
00068 
00069 /* CR register bit mask */
00070 #define CR_DS_MASK               ((uint32_t)0xFFFFFFFC)
00071 #define CR_PLS_MASK              ((uint32_t)0xFFFFFF1F)
00072 
00073 
00074 /**
00075   * @}
00076   */
00077 
00078 /** @defgroup PWR_Private_Macros
00079   * @{
00080   */
00081 
00082 /**
00083   * @}
00084   */
00085 
00086 /** @defgroup PWR_Private_Variables
00087   * @{
00088   */
00089 
00090 /**
00091   * @}
00092   */
00093 
00094 /** @defgroup PWR_Private_FunctionPrototypes
00095   * @{
00096   */
00097 
00098 /**
00099   * @}
00100   */
00101 
00102 /** @defgroup PWR_Private_Functions
00103   * @{
00104   */
00105 
00106 /**
00107   * @brief  Deinitializes the PWR peripheral registers to their default reset values.
00108   * @param  None
00109   * @retval None
00110   */
00111 void PWR_DeInit(void)
00112 {
00113   RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
00114   RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
00115 }
00116 
00117 /**
00118   * @brief  Enables or disables access to the RTC and backup registers.
00119   * @param  NewState: new state of the access to the RTC and backup registers.
00120   *   This parameter can be: ENABLE or DISABLE.
00121   * @retval None
00122   */
00123 void PWR_BackupAccessCmd(FunctionalState NewState)
00124 {
00125   /* Check the parameters */
00126   assert_param(IS_FUNCTIONAL_STATE(NewState));
00127   *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
00128 }
00129 
00130 /**
00131   * @brief  Enables or disables the Power Voltage Detector(PVD).
00132   * @param  NewState: new state of the PVD.
00133   *   This parameter can be: ENABLE or DISABLE.
00134   * @retval None
00135   */
00136 void PWR_PVDCmd(FunctionalState NewState)
00137 {
00138   /* Check the parameters */
00139   assert_param(IS_FUNCTIONAL_STATE(NewState));
00140   *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
00141 }
00142 
00143 /**
00144   * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
00145   * @param  PWR_PVDLevel: specifies the PVD detection level
00146   *   This parameter can be one of the following values:
00147   *     @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
00148   *     @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
00149   *     @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
00150   *     @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
00151   *     @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
00152   *     @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
00153   *     @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
00154   *     @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
00155   * @retval None
00156   */
00157 void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
00158 {
00159   uint32_t tmpreg = 0;
00160   /* Check the parameters */
00161   assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
00162   tmpreg = PWR->CR;
00163   /* Clear PLS[7:5] bits */
00164   tmpreg &= CR_PLS_MASK;
00165   /* Set PLS[7:5] bits according to PWR_PVDLevel value */
00166   tmpreg |= PWR_PVDLevel;
00167   /* Store the new value */
00168   PWR->CR = tmpreg;
00169 }
00170 
00171 /**
00172   * @brief  Enables or disables the WakeUp Pin functionality.
00173   * @param  NewState: new state of the WakeUp Pin functionality.
00174   *   This parameter can be: ENABLE or DISABLE.
00175   * @retval None
00176   */
00177 void PWR_WakeUpPinCmd(FunctionalState NewState)
00178 {
00179   /* Check the parameters */
00180   assert_param(IS_FUNCTIONAL_STATE(NewState));
00181   *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
00182 }
00183 
00184 /**
00185   * @brief  Enters STOP mode.
00186   * @param  PWR_Regulator: specifies the regulator state in STOP mode.
00187   *   This parameter can be one of the following values:
00188   *     @arg PWR_Regulator_ON: STOP mode with regulator ON
00189   *     @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
00190   * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
00191   *   This parameter can be one of the following values:
00192   *     @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
00193   *     @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
00194   * @retval None
00195   */
00196 void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
00197 {
00198   uint32_t tmpreg = 0;
00199   /* Check the parameters */
00200   assert_param(IS_PWR_REGULATOR(PWR_Regulator));
00201   assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
00202   
00203   /* Select the regulator state in STOP mode ---------------------------------*/
00204   tmpreg = PWR->CR;
00205   /* Clear PDDS and LPDS bits */
00206   tmpreg &= CR_DS_MASK;
00207   /* Set LPDS bit according to PWR_Regulator value */
00208   tmpreg |= PWR_Regulator;
00209   /* Store the new value */
00210   PWR->CR = tmpreg;
00211   /* Set SLEEPDEEP bit of Cortex System Control Register */
00212   SCB->SCR |= SCB_SCR_SLEEPDEEP;
00213   
00214   /* Select STOP mode entry --------------------------------------------------*/
00215   if(PWR_STOPEntry == PWR_STOPEntry_WFI)
00216   {   
00217     /* Request Wait For Interrupt */
00218     __WFI();
00219   }
00220   else
00221   {
00222     /* Request Wait For Event */
00223     __WFE();
00224   }
00225   
00226   /* Reset SLEEPDEEP bit of Cortex System Control Register */
00227   SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);  
00228 }
00229 
00230 /**
00231   * @brief  Enters STANDBY mode.
00232   * @param  None
00233   * @retval None
00234   */
00235 void PWR_EnterSTANDBYMode(void)
00236 {
00237   /* Clear Wake-up flag */
00238   PWR->CR |= PWR_CR_CWUF;
00239   /* Select STANDBY mode */
00240   PWR->CR |= PWR_CR_PDDS;
00241   /* Set SLEEPDEEP bit of Cortex System Control Register */
00242   SCB->SCR |= SCB_SCR_SLEEPDEEP;
00243 /* This option is used to ensure that store operations are completed */
00244 #if defined ( __CC_ARM   )
00245   __force_stores();
00246 #endif
00247   /* Request Wait For Interrupt */
00248   __WFI();
00249 }
00250 
00251 /**
00252   * @brief  Checks whether the specified PWR flag is set or not.
00253   * @param  PWR_FLAG: specifies the flag to check.
00254   *   This parameter can be one of the following values:
00255   *     @arg PWR_FLAG_WU: Wake Up flag
00256   *     @arg PWR_FLAG_SB: StandBy flag
00257   *     @arg PWR_FLAG_PVDO: PVD Output
00258   * @retval The new state of PWR_FLAG (SET or RESET).
00259   */
00260 FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
00261 {
00262   FlagStatus bitstatus = RESET;
00263   /* Check the parameters */
00264   assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
00265   
00266   if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
00267   {
00268     bitstatus = SET;
00269   }
00270   else
00271   {
00272     bitstatus = RESET;
00273   }
00274   /* Return the flag status */
00275   return bitstatus;
00276 }
00277 
00278 /**
00279   * @brief  Clears the PWR's pending flags.
00280   * @param  PWR_FLAG: specifies the flag to clear.
00281   *   This parameter can be one of the following values:
00282   *     @arg PWR_FLAG_WU: Wake Up flag
00283   *     @arg PWR_FLAG_SB: StandBy flag
00284   * @retval None
00285   */
00286 void PWR_ClearFlag(uint32_t PWR_FLAG)
00287 {
00288   /* Check the parameters */
00289   assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
00290          
00291   PWR->CR |=  PWR_FLAG << 2;
00292 }
00293 
00294 /**
00295   * @}
00296   */
00297 
00298 /**
00299   * @}
00300   */
00301 
00302 /**
00303   * @}
00304   */
00305 
00306 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
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