stm32f10x_fsmc.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_fsmc.h
00004   * @author  MCD Application Team
00005   * @version V3.4.0
00006   * @date    10/15/2010
00007   * @brief   This file contains all the functions prototypes for the FSMC firmware 
00008   *          library.
00009   ******************************************************************************
00010   * @copy
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
00020   */ 
00021 
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_FSMC_H
00024 #define __STM32F10x_FSMC_H
00025 
00026 #ifdef __cplusplus
00027  extern "C" {
00028 #endif
00029 
00030 /* Includes ------------------------------------------------------------------*/
00031 #include "stm32f10x.h"
00032 
00033 /** @addtogroup STM32F10x_StdPeriph_Driver
00034   * @{
00035   */
00036 
00037 /** @addtogroup FSMC
00038   * @{
00039   */
00040 
00041 /** @defgroup FSMC_Exported_Types
00042   * @{
00043   */
00044 
00045 /** 
00046   * @brief  Timing parameters For NOR/SRAM Banks  
00047   */
00048 
00049 typedef struct
00050 {
00051   uint32_t FSMC_AddressSetupTime;       /*!< Defines the number of HCLK cycles to configure
00052                                              the duration of the address setup time. 
00053                                              This parameter can be a value between 0 and 0xF.
00054                                              @note: It is not used with synchronous NOR Flash memories. */
00055 
00056   uint32_t FSMC_AddressHoldTime;        /*!< Defines the number of HCLK cycles to configure
00057                                              the duration of the address hold time.
00058                                              This parameter can be a value between 0 and 0xF. 
00059                                              @note: It is not used with synchronous NOR Flash memories.*/
00060 
00061   uint32_t FSMC_DataSetupTime;          /*!< Defines the number of HCLK cycles to configure
00062                                              the duration of the data setup time.
00063                                              This parameter can be a value between 0 and 0xFF.
00064                                              @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
00065 
00066   uint32_t FSMC_BusTurnAroundDuration;  /*!< Defines the number of HCLK cycles to configure
00067                                              the duration of the bus turnaround.
00068                                              This parameter can be a value between 0 and 0xF.
00069                                              @note: It is only used for multiplexed NOR Flash memories. */
00070 
00071   uint32_t FSMC_CLKDivision;            /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
00072                                              This parameter can be a value between 1 and 0xF.
00073                                              @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
00074 
00075   uint32_t FSMC_DataLatency;            /*!< Defines the number of memory clock cycles to issue
00076                                              to the memory before getting the first data.
00077                                              The value of this parameter depends on the memory type as shown below:
00078                                               - It must be set to 0 in case of a CRAM
00079                                               - It is don’t care in asynchronous NOR, SRAM or ROM accesses
00080                                               - It may assume a value between 0 and 0xF in NOR Flash memories
00081                                                 with synchronous burst mode enable */
00082 
00083   uint32_t FSMC_AccessMode;             /*!< Specifies the asynchronous access mode. 
00084                                              This parameter can be a value of @ref FSMC_Access_Mode */
00085 }FSMC_NORSRAMTimingInitTypeDef;
00086 
00087 /** 
00088   * @brief  FSMC NOR/SRAM Init structure definition
00089   */
00090 
00091 typedef struct
00092 {
00093   uint32_t FSMC_Bank;                /*!< Specifies the NOR/SRAM memory bank that will be used.
00094                                           This parameter can be a value of @ref FSMC_NORSRAM_Bank */
00095 
00096   uint32_t FSMC_DataAddressMux;      /*!< Specifies whether the address and data values are
00097                                           multiplexed on the databus or not. 
00098                                           This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
00099 
00100   uint32_t FSMC_MemoryType;          /*!< Specifies the type of external memory attached to
00101                                           the corresponding memory bank.
00102                                           This parameter can be a value of @ref FSMC_Memory_Type */
00103 
00104   uint32_t FSMC_MemoryDataWidth;     /*!< Specifies the external memory device width.
00105                                           This parameter can be a value of @ref FSMC_Data_Width */
00106 
00107   uint32_t FSMC_BurstAccessMode;     /*!< Enables or disables the burst access mode for Flash memory,
00108                                           valid only with synchronous burst Flash memories.
00109                                           This parameter can be a value of @ref FSMC_Burst_Access_Mode */
00110                                        
00111   uint32_t FSMC_AsynchronousWait;     /*!< Enables or disables wait signal during asynchronous transfers,
00112                                           valid only with asynchronous Flash memories.
00113                                           This parameter can be a value of @ref FSMC_AsynchronousWait */
00114 
00115   uint32_t FSMC_WaitSignalPolarity;  /*!< Specifies the wait signal polarity, valid only when accessing
00116                                           the Flash memory in burst mode.
00117                                           This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
00118 
00119   uint32_t FSMC_WrapMode;            /*!< Enables or disables the Wrapped burst access mode for Flash
00120                                           memory, valid only when accessing Flash memories in burst mode.
00121                                           This parameter can be a value of @ref FSMC_Wrap_Mode */
00122 
00123   uint32_t FSMC_WaitSignalActive;    /*!< Specifies if the wait signal is asserted by the memory one
00124                                           clock cycle before the wait state or during the wait state,
00125                                           valid only when accessing memories in burst mode. 
00126                                           This parameter can be a value of @ref FSMC_Wait_Timing */
00127 
00128   uint32_t FSMC_WriteOperation;      /*!< Enables or disables the write operation in the selected bank by the FSMC. 
00129                                           This parameter can be a value of @ref FSMC_Write_Operation */
00130 
00131   uint32_t FSMC_WaitSignal;          /*!< Enables or disables the wait-state insertion via wait
00132                                           signal, valid for Flash memory access in burst mode. 
00133                                           This parameter can be a value of @ref FSMC_Wait_Signal */
00134 
00135   uint32_t FSMC_ExtendedMode;        /*!< Enables or disables the extended mode.
00136                                           This parameter can be a value of @ref FSMC_Extended_Mode */
00137 
00138   uint32_t FSMC_WriteBurst;          /*!< Enables or disables the write burst operation.
00139                                           This parameter can be a value of @ref FSMC_Write_Burst */ 
00140 
00141   FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the  ExtendedMode is not used*/  
00142 
00143   FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;     /*!< Timing Parameters for write access if the  ExtendedMode is used*/      
00144 }FSMC_NORSRAMInitTypeDef;
00145 
00146 /** 
00147   * @brief  Timing parameters For FSMC NAND and PCCARD Banks
00148   */
00149 
00150 typedef struct
00151 {
00152   uint32_t FSMC_SetupTime;      /*!< Defines the number of HCLK cycles to setup address before
00153                                      the command assertion for NAND-Flash read or write access
00154                                      to common/Attribute or I/O memory space (depending on
00155                                      the memory space timing to be configured).
00156                                      This parameter can be a value between 0 and 0xFF.*/
00157 
00158   uint32_t FSMC_WaitSetupTime;  /*!< Defines the minimum number of HCLK cycles to assert the
00159                                      command for NAND-Flash read or write access to
00160                                      common/Attribute or I/O memory space (depending on the
00161                                      memory space timing to be configured). 
00162                                      This parameter can be a number between 0x00 and 0xFF */
00163 
00164   uint32_t FSMC_HoldSetupTime;  /*!< Defines the number of HCLK clock cycles to hold address
00165                                      (and data for write access) after the command deassertion
00166                                      for NAND-Flash read or write access to common/Attribute
00167                                      or I/O memory space (depending on the memory space timing
00168                                      to be configured).
00169                                      This parameter can be a number between 0x00 and 0xFF */
00170 
00171   uint32_t FSMC_HiZSetupTime;   /*!< Defines the number of HCLK clock cycles during which the
00172                                      databus is kept in HiZ after the start of a NAND-Flash
00173                                      write access to common/Attribute or I/O memory space (depending
00174                                      on the memory space timing to be configured).
00175                                      This parameter can be a number between 0x00 and 0xFF */
00176 }FSMC_NAND_PCCARDTimingInitTypeDef;
00177 
00178 /** 
00179   * @brief  FSMC NAND Init structure definition
00180   */
00181 
00182 typedef struct
00183 {
00184   uint32_t FSMC_Bank;              /*!< Specifies the NAND memory bank that will be used.
00185                                       This parameter can be a value of @ref FSMC_NAND_Bank */
00186 
00187   uint32_t FSMC_Waitfeature;      /*!< Enables or disables the Wait feature for the NAND Memory Bank.
00188                                        This parameter can be any value of @ref FSMC_Wait_feature */
00189 
00190   uint32_t FSMC_MemoryDataWidth;  /*!< Specifies the external memory device width.
00191                                        This parameter can be any value of @ref FSMC_Data_Width */
00192 
00193   uint32_t FSMC_ECC;              /*!< Enables or disables the ECC computation.
00194                                        This parameter can be any value of @ref FSMC_ECC */
00195 
00196   uint32_t FSMC_ECCPageSize;      /*!< Defines the page size for the extended ECC.
00197                                        This parameter can be any value of @ref FSMC_ECC_Page_Size */
00198 
00199   uint32_t FSMC_TCLRSetupTime;    /*!< Defines the number of HCLK cycles to configure the
00200                                        delay between CLE low and RE low.
00201                                        This parameter can be a value between 0 and 0xFF. */
00202 
00203   uint32_t FSMC_TARSetupTime;     /*!< Defines the number of HCLK cycles to configure the
00204                                        delay between ALE low and RE low.
00205                                        This parameter can be a number between 0x0 and 0xFF */ 
00206 
00207   FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;   /*!< FSMC Common Space Timing */ 
00208 
00209   FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
00210 }FSMC_NANDInitTypeDef;
00211 
00212 /** 
00213   * @brief  FSMC PCCARD Init structure definition
00214   */
00215 
00216 typedef struct
00217 {
00218   uint32_t FSMC_Waitfeature;    /*!< Enables or disables the Wait feature for the Memory Bank.
00219                                     This parameter can be any value of @ref FSMC_Wait_feature */
00220 
00221   uint32_t FSMC_TCLRSetupTime;  /*!< Defines the number of HCLK cycles to configure the
00222                                      delay between CLE low and RE low.
00223                                      This parameter can be a value between 0 and 0xFF. */
00224 
00225   uint32_t FSMC_TARSetupTime;   /*!< Defines the number of HCLK cycles to configure the
00226                                      delay between ALE low and RE low.
00227                                      This parameter can be a number between 0x0 and 0xFF */ 
00228 
00229   
00230   FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
00231 
00232   FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct;  /*!< FSMC Attribute Space Timing */ 
00233   
00234   FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */  
00235 }FSMC_PCCARDInitTypeDef;
00236 
00237 /**
00238   * @}
00239   */
00240 
00241 /** @defgroup FSMC_Exported_Constants
00242   * @{
00243   */
00244 
00245 /** @defgroup FSMC_NORSRAM_Bank 
00246   * @{
00247   */
00248 #define FSMC_Bank1_NORSRAM1                             ((uint32_t)0x00000000)
00249 #define FSMC_Bank1_NORSRAM2                             ((uint32_t)0x00000002)
00250 #define FSMC_Bank1_NORSRAM3                             ((uint32_t)0x00000004)
00251 #define FSMC_Bank1_NORSRAM4                             ((uint32_t)0x00000006)
00252 /**
00253   * @}
00254   */
00255 
00256 /** @defgroup FSMC_NAND_Bank 
00257   * @{
00258   */  
00259 #define FSMC_Bank2_NAND                                 ((uint32_t)0x00000010)
00260 #define FSMC_Bank3_NAND                                 ((uint32_t)0x00000100)
00261 /**
00262   * @}
00263   */
00264 
00265 /** @defgroup FSMC_PCCARD_Bank 
00266   * @{
00267   */    
00268 #define FSMC_Bank4_PCCARD                               ((uint32_t)0x00001000)
00269 /**
00270   * @}
00271   */
00272 
00273 #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
00274                                     ((BANK) == FSMC_Bank1_NORSRAM2) || \
00275                                     ((BANK) == FSMC_Bank1_NORSRAM3) || \
00276                                     ((BANK) == FSMC_Bank1_NORSRAM4))
00277 
00278 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
00279                                  ((BANK) == FSMC_Bank3_NAND))
00280 
00281 #define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
00282                                     ((BANK) == FSMC_Bank3_NAND) || \
00283                                     ((BANK) == FSMC_Bank4_PCCARD))
00284 
00285 #define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
00286                                ((BANK) == FSMC_Bank3_NAND) || \
00287                                ((BANK) == FSMC_Bank4_PCCARD))
00288 
00289 /** @defgroup NOR_SRAM_Controller 
00290   * @{
00291   */
00292 
00293 /** @defgroup FSMC_Data_Address_Bus_Multiplexing 
00294   * @{
00295   */
00296 
00297 #define FSMC_DataAddressMux_Disable                       ((uint32_t)0x00000000)
00298 #define FSMC_DataAddressMux_Enable                        ((uint32_t)0x00000002)
00299 #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
00300                           ((MUX) == FSMC_DataAddressMux_Enable))
00301 
00302 /**
00303   * @}
00304   */
00305 
00306 /** @defgroup FSMC_Memory_Type 
00307   * @{
00308   */
00309 
00310 #define FSMC_MemoryType_SRAM                            ((uint32_t)0x00000000)
00311 #define FSMC_MemoryType_PSRAM                           ((uint32_t)0x00000004)
00312 #define FSMC_MemoryType_NOR                             ((uint32_t)0x00000008)
00313 #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
00314                                 ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
00315                                 ((MEMORY) == FSMC_MemoryType_NOR))
00316 
00317 /**
00318   * @}
00319   */
00320 
00321 /** @defgroup FSMC_Data_Width 
00322   * @{
00323   */
00324 
00325 #define FSMC_MemoryDataWidth_8b                         ((uint32_t)0x00000000)
00326 #define FSMC_MemoryDataWidth_16b                        ((uint32_t)0x00000010)
00327 #define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
00328                                      ((WIDTH) == FSMC_MemoryDataWidth_16b))
00329 
00330 /**
00331   * @}
00332   */
00333 
00334 /** @defgroup FSMC_Burst_Access_Mode 
00335   * @{
00336   */
00337 
00338 #define FSMC_BurstAccessMode_Disable                    ((uint32_t)0x00000000) 
00339 #define FSMC_BurstAccessMode_Enable                     ((uint32_t)0x00000100)
00340 #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
00341                                   ((STATE) == FSMC_BurstAccessMode_Enable))
00342 /**
00343   * @}
00344   */
00345   
00346 /** @defgroup FSMC_AsynchronousWait 
00347   * @{
00348   */
00349 #define FSMC_AsynchronousWait_Disable                   ((uint32_t)0x00000000)
00350 #define FSMC_AsynchronousWait_Enable                    ((uint32_t)0x00008000)
00351 #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
00352                                  ((STATE) == FSMC_AsynchronousWait_Enable))
00353 
00354 /**
00355   * @}
00356   */
00357   
00358 /** @defgroup FSMC_Wait_Signal_Polarity 
00359   * @{
00360   */
00361 
00362 #define FSMC_WaitSignalPolarity_Low                     ((uint32_t)0x00000000)
00363 #define FSMC_WaitSignalPolarity_High                    ((uint32_t)0x00000200)
00364 #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
00365                                          ((POLARITY) == FSMC_WaitSignalPolarity_High)) 
00366 
00367 /**
00368   * @}
00369   */
00370 
00371 /** @defgroup FSMC_Wrap_Mode 
00372   * @{
00373   */
00374 
00375 #define FSMC_WrapMode_Disable                           ((uint32_t)0x00000000)
00376 #define FSMC_WrapMode_Enable                            ((uint32_t)0x00000400) 
00377 #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
00378                                  ((MODE) == FSMC_WrapMode_Enable))
00379 
00380 /**
00381   * @}
00382   */
00383 
00384 /** @defgroup FSMC_Wait_Timing 
00385   * @{
00386   */
00387 
00388 #define FSMC_WaitSignalActive_BeforeWaitState           ((uint32_t)0x00000000)
00389 #define FSMC_WaitSignalActive_DuringWaitState           ((uint32_t)0x00000800) 
00390 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
00391                                             ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
00392 
00393 /**
00394   * @}
00395   */
00396 
00397 /** @defgroup FSMC_Write_Operation 
00398   * @{
00399   */
00400 
00401 #define FSMC_WriteOperation_Disable                     ((uint32_t)0x00000000)
00402 #define FSMC_WriteOperation_Enable                      ((uint32_t)0x00001000)
00403 #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
00404                                             ((OPERATION) == FSMC_WriteOperation_Enable))
00405                               
00406 /**
00407   * @}
00408   */
00409 
00410 /** @defgroup FSMC_Wait_Signal 
00411   * @{
00412   */
00413 
00414 #define FSMC_WaitSignal_Disable                         ((uint32_t)0x00000000)
00415 #define FSMC_WaitSignal_Enable                          ((uint32_t)0x00002000) 
00416 #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
00417                                       ((SIGNAL) == FSMC_WaitSignal_Enable))
00418 /**
00419   * @}
00420   */
00421 
00422 /** @defgroup FSMC_Extended_Mode 
00423   * @{
00424   */
00425 
00426 #define FSMC_ExtendedMode_Disable                       ((uint32_t)0x00000000)
00427 #define FSMC_ExtendedMode_Enable                        ((uint32_t)0x00004000)
00428 
00429 #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
00430                                      ((MODE) == FSMC_ExtendedMode_Enable)) 
00431 
00432 /**
00433   * @}
00434   */
00435 
00436 /** @defgroup FSMC_Write_Burst 
00437   * @{
00438   */
00439 
00440 #define FSMC_WriteBurst_Disable                         ((uint32_t)0x00000000)
00441 #define FSMC_WriteBurst_Enable                          ((uint32_t)0x00080000) 
00442 #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
00443                                     ((BURST) == FSMC_WriteBurst_Enable))
00444 /**
00445   * @}
00446   */
00447 
00448 /** @defgroup FSMC_Address_Setup_Time 
00449   * @{
00450   */
00451 
00452 #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
00453 
00454 /**
00455   * @}
00456   */
00457 
00458 /** @defgroup FSMC_Address_Hold_Time 
00459   * @{
00460   */
00461 
00462 #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
00463 
00464 /**
00465   * @}
00466   */
00467 
00468 /** @defgroup FSMC_Data_Setup_Time 
00469   * @{
00470   */
00471 
00472 #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
00473 
00474 /**
00475   * @}
00476   */
00477 
00478 /** @defgroup FSMC_Bus_Turn_around_Duration 
00479   * @{
00480   */
00481 
00482 #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
00483 
00484 /**
00485   * @}
00486   */
00487 
00488 /** @defgroup FSMC_CLK_Division 
00489   * @{
00490   */
00491 
00492 #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
00493 
00494 /**
00495   * @}
00496   */
00497 
00498 /** @defgroup FSMC_Data_Latency 
00499   * @{
00500   */
00501 
00502 #define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
00503 
00504 /**
00505   * @}
00506   */
00507 
00508 /** @defgroup FSMC_Access_Mode 
00509   * @{
00510   */
00511 
00512 #define FSMC_AccessMode_A                               ((uint32_t)0x00000000)
00513 #define FSMC_AccessMode_B                               ((uint32_t)0x10000000) 
00514 #define FSMC_AccessMode_C                               ((uint32_t)0x20000000)
00515 #define FSMC_AccessMode_D                               ((uint32_t)0x30000000)
00516 #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
00517                                    ((MODE) == FSMC_AccessMode_B) || \
00518                                    ((MODE) == FSMC_AccessMode_C) || \
00519                                    ((MODE) == FSMC_AccessMode_D)) 
00520 
00521 /**
00522   * @}
00523   */
00524 
00525 /**
00526   * @}
00527   */
00528   
00529 /** @defgroup NAND_PCCARD_Controller 
00530   * @{
00531   */
00532 
00533 /** @defgroup FSMC_Wait_feature 
00534   * @{
00535   */
00536 
00537 #define FSMC_Waitfeature_Disable                        ((uint32_t)0x00000000)
00538 #define FSMC_Waitfeature_Enable                         ((uint32_t)0x00000002)
00539 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
00540                                        ((FEATURE) == FSMC_Waitfeature_Enable))
00541 
00542 /**
00543   * @}
00544   */
00545 
00546 
00547 /** @defgroup FSMC_ECC 
00548   * @{
00549   */
00550 
00551 #define FSMC_ECC_Disable                                ((uint32_t)0x00000000)
00552 #define FSMC_ECC_Enable                                 ((uint32_t)0x00000040)
00553 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
00554                                   ((STATE) == FSMC_ECC_Enable))
00555 
00556 /**
00557   * @}
00558   */
00559 
00560 /** @defgroup FSMC_ECC_Page_Size 
00561   * @{
00562   */
00563 
00564 #define FSMC_ECCPageSize_256Bytes                       ((uint32_t)0x00000000)
00565 #define FSMC_ECCPageSize_512Bytes                       ((uint32_t)0x00020000)
00566 #define FSMC_ECCPageSize_1024Bytes                      ((uint32_t)0x00040000)
00567 #define FSMC_ECCPageSize_2048Bytes                      ((uint32_t)0x00060000)
00568 #define FSMC_ECCPageSize_4096Bytes                      ((uint32_t)0x00080000)
00569 #define FSMC_ECCPageSize_8192Bytes                      ((uint32_t)0x000A0000)
00570 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
00571                                     ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
00572                                     ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
00573                                     ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
00574                                     ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
00575                                     ((SIZE) == FSMC_ECCPageSize_8192Bytes))
00576 
00577 /**
00578   * @}
00579   */
00580 
00581 /** @defgroup FSMC_TCLR_Setup_Time 
00582   * @{
00583   */
00584 
00585 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
00586 
00587 /**
00588   * @}
00589   */
00590 
00591 /** @defgroup FSMC_TAR_Setup_Time 
00592   * @{
00593   */
00594 
00595 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
00596 
00597 /**
00598   * @}
00599   */
00600 
00601 /** @defgroup FSMC_Setup_Time 
00602   * @{
00603   */
00604 
00605 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
00606 
00607 /**
00608   * @}
00609   */
00610 
00611 /** @defgroup FSMC_Wait_Setup_Time 
00612   * @{
00613   */
00614 
00615 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
00616 
00617 /**
00618   * @}
00619   */
00620 
00621 /** @defgroup FSMC_Hold_Setup_Time 
00622   * @{
00623   */
00624 
00625 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
00626 
00627 /**
00628   * @}
00629   */
00630 
00631 /** @defgroup FSMC_HiZ_Setup_Time 
00632   * @{
00633   */
00634 
00635 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
00636 
00637 /**
00638   * @}
00639   */
00640 
00641 /** @defgroup FSMC_Interrupt_sources 
00642   * @{
00643   */
00644 
00645 #define FSMC_IT_RisingEdge                              ((uint32_t)0x00000008)
00646 #define FSMC_IT_Level                                   ((uint32_t)0x00000010)
00647 #define FSMC_IT_FallingEdge                             ((uint32_t)0x00000020)
00648 #define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
00649 #define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
00650                             ((IT) == FSMC_IT_Level) || \
00651                             ((IT) == FSMC_IT_FallingEdge)) 
00652 /**
00653   * @}
00654   */
00655 
00656 /** @defgroup FSMC_Flags 
00657   * @{
00658   */
00659 
00660 #define FSMC_FLAG_RisingEdge                            ((uint32_t)0x00000001)
00661 #define FSMC_FLAG_Level                                 ((uint32_t)0x00000002)
00662 #define FSMC_FLAG_FallingEdge                           ((uint32_t)0x00000004)
00663 #define FSMC_FLAG_FEMPT                                 ((uint32_t)0x00000040)
00664 #define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
00665                                 ((FLAG) == FSMC_FLAG_Level) || \
00666                                 ((FLAG) == FSMC_FLAG_FallingEdge) || \
00667                                 ((FLAG) == FSMC_FLAG_FEMPT))
00668 
00669 #define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
00670 
00671 /**
00672   * @}
00673   */
00674 
00675 /**
00676   * @}
00677   */
00678 
00679 /**
00680   * @}
00681   */
00682 
00683 /** @defgroup FSMC_Exported_Macros
00684   * @{
00685   */
00686 
00687 /**
00688   * @}
00689   */
00690 
00691 /** @defgroup FSMC_Exported_Functions
00692   * @{
00693   */
00694 
00695 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
00696 void FSMC_NANDDeInit(uint32_t FSMC_Bank);
00697 void FSMC_PCCARDDeInit(void);
00698 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
00699 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
00700 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
00701 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
00702 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
00703 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
00704 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
00705 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
00706 void FSMC_PCCARDCmd(FunctionalState NewState);
00707 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
00708 uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
00709 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
00710 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
00711 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
00712 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
00713 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
00714 
00715 #ifdef __cplusplus
00716 }
00717 #endif
00718 
00719 #endif /*__STM32F10x_FSMC_H */
00720 /**
00721   * @}
00722   */
00723 
00724 /**
00725   * @}
00726   */
00727 
00728 /**
00729   * @}
00730   */ 
00731 
00732 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
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