stm32f10x_fsmc.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_fsmc.c
00004   * @author  MCD Application Team
00005   * @version V3.4.0
00006   * @date    10/15/2010
00007   * @brief   This file provides all the FSMC firmware functions.
00008   ******************************************************************************
00009   * @copy
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
00019   */ 
00020 
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32f10x_fsmc.h"
00023 #include "stm32f10x_rcc.h"
00024 
00025 /** @addtogroup STM32F10x_StdPeriph_Driver
00026   * @{
00027   */
00028 
00029 /** @defgroup FSMC 
00030   * @brief FSMC driver modules
00031   * @{
00032   */ 
00033 
00034 /** @defgroup FSMC_Private_TypesDefinitions
00035   * @{
00036   */ 
00037 /**
00038   * @}
00039   */
00040 
00041 /** @defgroup FSMC_Private_Defines
00042   * @{
00043   */
00044 
00045 /* --------------------- FSMC registers bit mask ---------------------------- */
00046 
00047 /* FSMC BCRx Mask */
00048 #define BCR_MBKEN_Set                       ((uint32_t)0x00000001)
00049 #define BCR_MBKEN_Reset                     ((uint32_t)0x000FFFFE)
00050 #define BCR_FACCEN_Set                      ((uint32_t)0x00000040)
00051 
00052 /* FSMC PCRx Mask */
00053 #define PCR_PBKEN_Set                       ((uint32_t)0x00000004)
00054 #define PCR_PBKEN_Reset                     ((uint32_t)0x000FFFFB)
00055 #define PCR_ECCEN_Set                       ((uint32_t)0x00000040)
00056 #define PCR_ECCEN_Reset                     ((uint32_t)0x000FFFBF)
00057 #define PCR_MemoryType_NAND                 ((uint32_t)0x00000008)
00058 /**
00059   * @}
00060   */
00061 
00062 /** @defgroup FSMC_Private_Macros
00063   * @{
00064   */
00065 
00066 /**
00067   * @}
00068   */
00069 
00070 /** @defgroup FSMC_Private_Variables
00071   * @{
00072   */
00073 
00074 /**
00075   * @}
00076   */
00077 
00078 /** @defgroup FSMC_Private_FunctionPrototypes
00079   * @{
00080   */
00081 
00082 /**
00083   * @}
00084   */
00085 
00086 /** @defgroup FSMC_Private_Functions
00087   * @{
00088   */
00089 
00090 /**
00091   * @brief  Deinitializes the FSMC NOR/SRAM Banks registers to their default 
00092   *   reset values.
00093   * @param  FSMC_Bank: specifies the FSMC Bank to be used
00094   *   This parameter can be one of the following values:
00095   *     @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  
00096   *     @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 
00097   *     @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 
00098   *     @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 
00099   * @retval None
00100   */
00101 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
00102 {
00103   /* Check the parameter */
00104   assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
00105   
00106   /* FSMC_Bank1_NORSRAM1 */
00107   if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
00108   {
00109     FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;    
00110   }
00111   /* FSMC_Bank1_NORSRAM2,  FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
00112   else
00113   {   
00114     FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; 
00115   }
00116   FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
00117   FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;  
00118 }
00119 
00120 /**
00121   * @brief  Deinitializes the FSMC NAND Banks registers to their default reset values.
00122   * @param  FSMC_Bank: specifies the FSMC Bank to be used
00123   *   This parameter can be one of the following values:
00124   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
00125   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND 
00126   * @retval None
00127   */
00128 void FSMC_NANDDeInit(uint32_t FSMC_Bank)
00129 {
00130   /* Check the parameter */
00131   assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
00132   
00133   if(FSMC_Bank == FSMC_Bank2_NAND)
00134   {
00135     /* Set the FSMC_Bank2 registers to their reset values */
00136     FSMC_Bank2->PCR2 = 0x00000018;
00137     FSMC_Bank2->SR2 = 0x00000040;
00138     FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
00139     FSMC_Bank2->PATT2 = 0xFCFCFCFC;  
00140   }
00141   /* FSMC_Bank3_NAND */  
00142   else
00143   {
00144     /* Set the FSMC_Bank3 registers to their reset values */
00145     FSMC_Bank3->PCR3 = 0x00000018;
00146     FSMC_Bank3->SR3 = 0x00000040;
00147     FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
00148     FSMC_Bank3->PATT3 = 0xFCFCFCFC; 
00149   }  
00150 }
00151 
00152 /**
00153   * @brief  Deinitializes the FSMC PCCARD Bank registers to their default reset values.
00154   * @param  None                       
00155   * @retval None
00156   */
00157 void FSMC_PCCARDDeInit(void)
00158 {
00159   /* Set the FSMC_Bank4 registers to their reset values */
00160   FSMC_Bank4->PCR4 = 0x00000018; 
00161   FSMC_Bank4->SR4 = 0x00000000; 
00162   FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
00163   FSMC_Bank4->PATT4 = 0xFCFCFCFC;
00164   FSMC_Bank4->PIO4 = 0xFCFCFCFC;
00165 }
00166 
00167 /**
00168   * @brief  Initializes the FSMC NOR/SRAM Banks according to the specified
00169   *   parameters in the FSMC_NORSRAMInitStruct.
00170   * @param  FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
00171   *   structure that contains the configuration information for 
00172   *   the FSMC NOR/SRAM specified Banks.                       
00173   * @retval None
00174   */
00175 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
00176 { 
00177   /* Check the parameters */
00178   assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
00179   assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
00180   assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
00181   assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
00182   assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
00183   assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
00184   assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
00185   assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
00186   assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
00187   assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
00188   assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
00189   assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
00190   assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));  
00191   assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
00192   assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
00193   assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
00194   assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
00195   assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
00196   assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
00197   assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); 
00198   
00199   /* Bank1 NOR/SRAM control register configuration */ 
00200   FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 
00201             (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
00202             FSMC_NORSRAMInitStruct->FSMC_MemoryType |
00203             FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
00204             FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
00205             FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
00206             FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
00207             FSMC_NORSRAMInitStruct->FSMC_WrapMode |
00208             FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
00209             FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
00210             FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
00211             FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
00212             FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
00213 
00214   if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
00215   {
00216     FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
00217   }
00218   
00219   /* Bank1 NOR/SRAM timing register configuration */
00220   FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = 
00221             (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
00222             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
00223             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
00224             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
00225             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
00226             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
00227              FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
00228             
00229     
00230   /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
00231   if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
00232   {
00233     assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
00234     assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
00235     assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
00236     assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
00237     assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
00238     assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
00239     FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 
00240               (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
00241               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
00242               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
00243               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
00244               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
00245                FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
00246   }
00247   else
00248   {
00249     FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
00250   }
00251 }
00252 
00253 /**
00254   * @brief  Initializes the FSMC NAND Banks according to the specified 
00255   *   parameters in the FSMC_NANDInitStruct.
00256   * @param  FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef 
00257   *   structure that contains the configuration information for the FSMC NAND specified Banks.                       
00258   * @retval None
00259   */
00260 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
00261 {
00262   uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; 
00263     
00264   /* Check the parameters */
00265   assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
00266   assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
00267   assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
00268   assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
00269   assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
00270   assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
00271   assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
00272   assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
00273   assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
00274   assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
00275   assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
00276   assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
00277   assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
00278   assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
00279   assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
00280   
00281   /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
00282   tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
00283             PCR_MemoryType_NAND |
00284             FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
00285             FSMC_NANDInitStruct->FSMC_ECC |
00286             FSMC_NANDInitStruct->FSMC_ECCPageSize |
00287             (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
00288             (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
00289             
00290   /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
00291   tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
00292             (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
00293             (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
00294             (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); 
00295             
00296   /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
00297   tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
00298             (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
00299             (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
00300             (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
00301   
00302   if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
00303   {
00304     /* FSMC_Bank2_NAND registers configuration */
00305     FSMC_Bank2->PCR2 = tmppcr;
00306     FSMC_Bank2->PMEM2 = tmppmem;
00307     FSMC_Bank2->PATT2 = tmppatt;
00308   }
00309   else
00310   {
00311     /* FSMC_Bank3_NAND registers configuration */
00312     FSMC_Bank3->PCR3 = tmppcr;
00313     FSMC_Bank3->PMEM3 = tmppmem;
00314     FSMC_Bank3->PATT3 = tmppatt;
00315   }
00316 }
00317 
00318 /**
00319   * @brief  Initializes the FSMC PCCARD Bank according to the specified 
00320   *   parameters in the FSMC_PCCARDInitStruct.
00321   * @param  FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
00322   *   structure that contains the configuration information for the FSMC PCCARD Bank.                       
00323   * @retval None
00324   */
00325 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
00326 {
00327   /* Check the parameters */
00328   assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
00329   assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
00330   assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
00331  
00332   assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
00333   assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
00334   assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
00335   assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
00336   
00337   assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
00338   assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
00339   assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
00340   assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
00341   assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
00342   assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
00343   assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
00344   assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
00345   
00346   /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
00347   FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
00348                      FSMC_MemoryDataWidth_16b |  
00349                      (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
00350                      (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
00351             
00352   /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
00353   FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
00354                       (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
00355                       (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
00356                       (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); 
00357             
00358   /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
00359   FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
00360                       (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
00361                       (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
00362                       (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);        
00363             
00364   /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
00365   FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
00366                      (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
00367                      (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
00368                      (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);             
00369 }
00370 
00371 /**
00372   * @brief  Fills each FSMC_NORSRAMInitStruct member with its default value.
00373   * @param  FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef 
00374   *   structure which will be initialized.
00375   * @retval None
00376   */
00377 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
00378 {  
00379   /* Reset NOR/SRAM Init structure parameters values */
00380   FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
00381   FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
00382   FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
00383   FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
00384   FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
00385   FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
00386   FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
00387   FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
00388   FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
00389   FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
00390   FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
00391   FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
00392   FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
00393   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
00394   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
00395   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
00396   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
00397   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
00398   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
00399   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; 
00400   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
00401   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
00402   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
00403   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
00404   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
00405   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
00406   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
00407 }
00408 
00409 /**
00410   * @brief  Fills each FSMC_NANDInitStruct member with its default value.
00411   * @param  FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef 
00412   *   structure which will be initialized.
00413   * @retval None
00414   */
00415 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
00416 { 
00417   /* Reset NAND Init structure parameters values */
00418   FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
00419   FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
00420   FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
00421   FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
00422   FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
00423   FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
00424   FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
00425   FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
00426   FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00427   FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
00428   FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
00429   FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
00430   FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00431   FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
00432   FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;         
00433 }
00434 
00435 /**
00436   * @brief  Fills each FSMC_PCCARDInitStruct member with its default value.
00437   * @param  FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef 
00438   *   structure which will be initialized.
00439   * @retval None
00440   */
00441 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
00442 {
00443   /* Reset PCCARD Init structure parameters values */
00444   FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
00445   FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
00446   FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
00447   FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
00448   FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00449   FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
00450   FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
00451   FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
00452   FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00453   FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
00454   FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;     
00455   FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
00456   FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00457   FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
00458   FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
00459 }
00460 
00461 /**
00462   * @brief  Enables or disables the specified NOR/SRAM Memory Bank.
00463   * @param  FSMC_Bank: specifies the FSMC Bank to be used
00464   *   This parameter can be one of the following values:
00465   *     @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  
00466   *     @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 
00467   *     @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 
00468   *     @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 
00469   * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
00470   * @retval None
00471   */
00472 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
00473 {
00474   assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
00475   assert_param(IS_FUNCTIONAL_STATE(NewState));
00476   
00477   if (NewState != DISABLE)
00478   {
00479     /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
00480     FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
00481   }
00482   else
00483   {
00484     /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
00485     FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
00486   }
00487 }
00488 
00489 /**
00490   * @brief  Enables or disables the specified NAND Memory Bank.
00491   * @param  FSMC_Bank: specifies the FSMC Bank to be used
00492   *   This parameter can be one of the following values:
00493   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
00494   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
00495   * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
00496   * @retval None
00497   */
00498 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
00499 {
00500   assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
00501   assert_param(IS_FUNCTIONAL_STATE(NewState));
00502   
00503   if (NewState != DISABLE)
00504   {
00505     /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
00506     if(FSMC_Bank == FSMC_Bank2_NAND)
00507     {
00508       FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
00509     }
00510     else
00511     {
00512       FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
00513     }
00514   }
00515   else
00516   {
00517     /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
00518     if(FSMC_Bank == FSMC_Bank2_NAND)
00519     {
00520       FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
00521     }
00522     else
00523     {
00524       FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
00525     }
00526   }
00527 }
00528 
00529 /**
00530   * @brief  Enables or disables the PCCARD Memory Bank.
00531   * @param  NewState: new state of the PCCARD Memory Bank.  
00532   *   This parameter can be: ENABLE or DISABLE.
00533   * @retval None
00534   */
00535 void FSMC_PCCARDCmd(FunctionalState NewState)
00536 {
00537   assert_param(IS_FUNCTIONAL_STATE(NewState));
00538   
00539   if (NewState != DISABLE)
00540   {
00541     /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
00542     FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
00543   }
00544   else
00545   {
00546     /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
00547     FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
00548   }
00549 }
00550 
00551 /**
00552   * @brief  Enables or disables the FSMC NAND ECC feature.
00553   * @param  FSMC_Bank: specifies the FSMC Bank to be used
00554   *   This parameter can be one of the following values:
00555   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
00556   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
00557   * @param  NewState: new state of the FSMC NAND ECC feature.  
00558   *   This parameter can be: ENABLE or DISABLE.
00559   * @retval None
00560   */
00561 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
00562 {
00563   assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
00564   assert_param(IS_FUNCTIONAL_STATE(NewState));
00565   
00566   if (NewState != DISABLE)
00567   {
00568     /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
00569     if(FSMC_Bank == FSMC_Bank2_NAND)
00570     {
00571       FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
00572     }
00573     else
00574     {
00575       FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
00576     }
00577   }
00578   else
00579   {
00580     /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
00581     if(FSMC_Bank == FSMC_Bank2_NAND)
00582     {
00583       FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
00584     }
00585     else
00586     {
00587       FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
00588     }
00589   }
00590 }
00591 
00592 /**
00593   * @brief  Returns the error correction code register value.
00594   * @param  FSMC_Bank: specifies the FSMC Bank to be used
00595   *   This parameter can be one of the following values:
00596   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
00597   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
00598   * @retval The Error Correction Code (ECC) value.
00599   */
00600 uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
00601 {
00602   uint32_t eccval = 0x00000000;
00603   
00604   if(FSMC_Bank == FSMC_Bank2_NAND)
00605   {
00606     /* Get the ECCR2 register value */
00607     eccval = FSMC_Bank2->ECCR2;
00608   }
00609   else
00610   {
00611     /* Get the ECCR3 register value */
00612     eccval = FSMC_Bank3->ECCR3;
00613   }
00614   /* Return the error correction code value */
00615   return(eccval);
00616 }
00617 
00618 /**
00619   * @brief  Enables or disables the specified FSMC interrupts.
00620   * @param  FSMC_Bank: specifies the FSMC Bank to be used
00621   *   This parameter can be one of the following values:
00622   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
00623   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
00624   *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
00625   * @param  FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
00626   *   This parameter can be any combination of the following values:
00627   *     @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. 
00628   *     @arg FSMC_IT_Level: Level edge detection interrupt.
00629   *     @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
00630   * @param  NewState: new state of the specified FSMC interrupts.
00631   *   This parameter can be: ENABLE or DISABLE.
00632   * @retval None
00633   */
00634 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
00635 {
00636   assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
00637   assert_param(IS_FSMC_IT(FSMC_IT));    
00638   assert_param(IS_FUNCTIONAL_STATE(NewState));
00639   
00640   if (NewState != DISABLE)
00641   {
00642     /* Enable the selected FSMC_Bank2 interrupts */
00643     if(FSMC_Bank == FSMC_Bank2_NAND)
00644     {
00645       FSMC_Bank2->SR2 |= FSMC_IT;
00646     }
00647     /* Enable the selected FSMC_Bank3 interrupts */
00648     else if (FSMC_Bank == FSMC_Bank3_NAND)
00649     {
00650       FSMC_Bank3->SR3 |= FSMC_IT;
00651     }
00652     /* Enable the selected FSMC_Bank4 interrupts */
00653     else
00654     {
00655       FSMC_Bank4->SR4 |= FSMC_IT;    
00656     }
00657   }
00658   else
00659   {
00660     /* Disable the selected FSMC_Bank2 interrupts */
00661     if(FSMC_Bank == FSMC_Bank2_NAND)
00662     {
00663       
00664       FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
00665     }
00666     /* Disable the selected FSMC_Bank3 interrupts */
00667     else if (FSMC_Bank == FSMC_Bank3_NAND)
00668     {
00669       FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
00670     }
00671     /* Disable the selected FSMC_Bank4 interrupts */
00672     else
00673     {
00674       FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;    
00675     }
00676   }
00677 }
00678 
00679 /**
00680   * @brief  Checks whether the specified FSMC flag is set or not.
00681   * @param  FSMC_Bank: specifies the FSMC Bank to be used
00682   *   This parameter can be one of the following values:
00683   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
00684   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
00685   *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
00686   * @param  FSMC_FLAG: specifies the flag to check.
00687   *   This parameter can be one of the following values:
00688   *     @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
00689   *     @arg FSMC_FLAG_Level: Level detection Flag.
00690   *     @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
00691   *     @arg FSMC_FLAG_FEMPT: Fifo empty Flag. 
00692   * @retval The new state of FSMC_FLAG (SET or RESET).
00693   */
00694 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
00695 {
00696   FlagStatus bitstatus = RESET;
00697   uint32_t tmpsr = 0x00000000;
00698   
00699   /* Check the parameters */
00700   assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
00701   assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
00702   
00703   if(FSMC_Bank == FSMC_Bank2_NAND)
00704   {
00705     tmpsr = FSMC_Bank2->SR2;
00706   }  
00707   else if(FSMC_Bank == FSMC_Bank3_NAND)
00708   {
00709     tmpsr = FSMC_Bank3->SR3;
00710   }
00711   /* FSMC_Bank4_PCCARD*/
00712   else
00713   {
00714     tmpsr = FSMC_Bank4->SR4;
00715   } 
00716   
00717   /* Get the flag status */
00718   if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
00719   {
00720     bitstatus = SET;
00721   }
00722   else
00723   {
00724     bitstatus = RESET;
00725   }
00726   /* Return the flag status */
00727   return bitstatus;
00728 }
00729 
00730 /**
00731   * @brief  Clears the FSMC’s pending flags.
00732   * @param  FSMC_Bank: specifies the FSMC Bank to be used
00733   *   This parameter can be one of the following values:
00734   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
00735   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
00736   *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
00737   * @param  FSMC_FLAG: specifies the flag to clear.
00738   *   This parameter can be any combination of the following values:
00739   *     @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
00740   *     @arg FSMC_FLAG_Level: Level detection Flag.
00741   *     @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
00742   * @retval None
00743   */
00744 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
00745 {
00746  /* Check the parameters */
00747   assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
00748   assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
00749     
00750   if(FSMC_Bank == FSMC_Bank2_NAND)
00751   {
00752     FSMC_Bank2->SR2 &= ~FSMC_FLAG; 
00753   }  
00754   else if(FSMC_Bank == FSMC_Bank3_NAND)
00755   {
00756     FSMC_Bank3->SR3 &= ~FSMC_FLAG;
00757   }
00758   /* FSMC_Bank4_PCCARD*/
00759   else
00760   {
00761     FSMC_Bank4->SR4 &= ~FSMC_FLAG;
00762   }
00763 }
00764 
00765 /**
00766   * @brief  Checks whether the specified FSMC interrupt has occurred or not.
00767   * @param  FSMC_Bank: specifies the FSMC Bank to be used
00768   *   This parameter can be one of the following values:
00769   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
00770   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
00771   *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
00772   * @param  FSMC_IT: specifies the FSMC interrupt source to check.
00773   *   This parameter can be one of the following values:
00774   *     @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. 
00775   *     @arg FSMC_IT_Level: Level edge detection interrupt.
00776   *     @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. 
00777   * @retval The new state of FSMC_IT (SET or RESET).
00778   */
00779 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
00780 {
00781   ITStatus bitstatus = RESET;
00782   uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; 
00783   
00784   /* Check the parameters */
00785   assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
00786   assert_param(IS_FSMC_GET_IT(FSMC_IT));
00787   
00788   if(FSMC_Bank == FSMC_Bank2_NAND)
00789   {
00790     tmpsr = FSMC_Bank2->SR2;
00791   }  
00792   else if(FSMC_Bank == FSMC_Bank3_NAND)
00793   {
00794     tmpsr = FSMC_Bank3->SR3;
00795   }
00796   /* FSMC_Bank4_PCCARD*/
00797   else
00798   {
00799     tmpsr = FSMC_Bank4->SR4;
00800   } 
00801   
00802   itstatus = tmpsr & FSMC_IT;
00803   
00804   itenable = tmpsr & (FSMC_IT >> 3);
00805   if ((itstatus != (uint32_t)RESET)  && (itenable != (uint32_t)RESET))
00806   {
00807     bitstatus = SET;
00808   }
00809   else
00810   {
00811     bitstatus = RESET;
00812   }
00813   return bitstatus; 
00814 }
00815 
00816 /**
00817   * @brief  Clears the FSMC’s interrupt pending bits.
00818   * @param  FSMC_Bank: specifies the FSMC Bank to be used
00819   *   This parameter can be one of the following values:
00820   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
00821   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
00822   *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
00823   * @param  FSMC_IT: specifies the interrupt pending bit to clear.
00824   *   This parameter can be any combination of the following values:
00825   *     @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. 
00826   *     @arg FSMC_IT_Level: Level edge detection interrupt.
00827   *     @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
00828   * @retval None
00829   */
00830 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
00831 {
00832   /* Check the parameters */
00833   assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
00834   assert_param(IS_FSMC_IT(FSMC_IT));
00835     
00836   if(FSMC_Bank == FSMC_Bank2_NAND)
00837   {
00838     FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); 
00839   }  
00840   else if(FSMC_Bank == FSMC_Bank3_NAND)
00841   {
00842     FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
00843   }
00844   /* FSMC_Bank4_PCCARD*/
00845   else
00846   {
00847     FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
00848   }
00849 }
00850 
00851 /**
00852   * @}
00853   */ 
00854 
00855 /**
00856   * @}
00857   */
00858 
00859 /**
00860   * @}
00861   */
00862 
00863 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
STM32F10x Standard Peripherals Library: Footer

 

 

 

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