stm32f10x_dma.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_dma.h
00004   * @author  MCD Application Team
00005   * @version V3.4.0
00006   * @date    10/15/2010
00007   * @brief   This file contains all the functions prototypes for the DMA firmware 
00008   *          library.
00009   ******************************************************************************
00010   * @copy
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
00020   */ 
00021 
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_DMA_H
00024 #define __STM32F10x_DMA_H
00025 
00026 #ifdef __cplusplus
00027  extern "C" {
00028 #endif
00029 
00030 /* Includes ------------------------------------------------------------------*/
00031 #include "stm32f10x.h"
00032 
00033 /** @addtogroup STM32F10x_StdPeriph_Driver
00034   * @{
00035   */
00036 
00037 /** @addtogroup DMA
00038   * @{
00039   */
00040 
00041 /** @defgroup DMA_Exported_Types
00042   * @{
00043   */
00044 
00045 /** 
00046   * @brief  DMA Init structure definition
00047   */
00048 
00049 typedef struct
00050 {
00051   uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
00052 
00053   uint32_t DMA_MemoryBaseAddr;     /*!< Specifies the memory base address for DMAy Channelx. */
00054 
00055   uint32_t DMA_DIR;                /*!< Specifies if the peripheral is the source or destination.
00056                                         This parameter can be a value of @ref DMA_data_transfer_direction */
00057 
00058   uint32_t DMA_BufferSize;         /*!< Specifies the buffer size, in data unit, of the specified Channel. 
00059                                         The data unit is equal to the configuration set in DMA_PeripheralDataSize
00060                                         or DMA_MemoryDataSize members depending in the transfer direction. */
00061 
00062   uint32_t DMA_PeripheralInc;      /*!< Specifies whether the Peripheral address register is incremented or not.
00063                                         This parameter can be a value of @ref DMA_peripheral_incremented_mode */
00064 
00065   uint32_t DMA_MemoryInc;          /*!< Specifies whether the memory address register is incremented or not.
00066                                         This parameter can be a value of @ref DMA_memory_incremented_mode */
00067 
00068   uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
00069                                         This parameter can be a value of @ref DMA_peripheral_data_size */
00070 
00071   uint32_t DMA_MemoryDataSize;     /*!< Specifies the Memory data width.
00072                                         This parameter can be a value of @ref DMA_memory_data_size */
00073 
00074   uint32_t DMA_Mode;               /*!< Specifies the operation mode of the DMAy Channelx.
00075                                         This parameter can be a value of @ref DMA_circular_normal_mode.
00076                                         @note: The circular buffer mode cannot be used if the memory-to-memory
00077                                               data transfer is configured on the selected Channel */
00078 
00079   uint32_t DMA_Priority;           /*!< Specifies the software priority for the DMAy Channelx.
00080                                         This parameter can be a value of @ref DMA_priority_level */
00081 
00082   uint32_t DMA_M2M;                /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
00083                                         This parameter can be a value of @ref DMA_memory_to_memory */
00084 }DMA_InitTypeDef;
00085 
00086 /**
00087   * @}
00088   */
00089 
00090 /** @defgroup DMA_Exported_Constants
00091   * @{
00092   */
00093 
00094 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
00095                                    ((PERIPH) == DMA1_Channel2) || \
00096                                    ((PERIPH) == DMA1_Channel3) || \
00097                                    ((PERIPH) == DMA1_Channel4) || \
00098                                    ((PERIPH) == DMA1_Channel5) || \
00099                                    ((PERIPH) == DMA1_Channel6) || \
00100                                    ((PERIPH) == DMA1_Channel7) || \
00101                                    ((PERIPH) == DMA2_Channel1) || \
00102                                    ((PERIPH) == DMA2_Channel2) || \
00103                                    ((PERIPH) == DMA2_Channel3) || \
00104                                    ((PERIPH) == DMA2_Channel4) || \
00105                                    ((PERIPH) == DMA2_Channel5))
00106 
00107 /** @defgroup DMA_data_transfer_direction 
00108   * @{
00109   */
00110 
00111 #define DMA_DIR_PeripheralDST              ((uint32_t)0x00000010)
00112 #define DMA_DIR_PeripheralSRC              ((uint32_t)0x00000000)
00113 #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
00114                          ((DIR) == DMA_DIR_PeripheralSRC))
00115 /**
00116   * @}
00117   */
00118 
00119 /** @defgroup DMA_peripheral_incremented_mode 
00120   * @{
00121   */
00122 
00123 #define DMA_PeripheralInc_Enable           ((uint32_t)0x00000040)
00124 #define DMA_PeripheralInc_Disable          ((uint32_t)0x00000000)
00125 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
00126                                             ((STATE) == DMA_PeripheralInc_Disable))
00127 /**
00128   * @}
00129   */
00130 
00131 /** @defgroup DMA_memory_incremented_mode 
00132   * @{
00133   */
00134 
00135 #define DMA_MemoryInc_Enable               ((uint32_t)0x00000080)
00136 #define DMA_MemoryInc_Disable              ((uint32_t)0x00000000)
00137 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
00138                                         ((STATE) == DMA_MemoryInc_Disable))
00139 /**
00140   * @}
00141   */
00142 
00143 /** @defgroup DMA_peripheral_data_size 
00144   * @{
00145   */
00146 
00147 #define DMA_PeripheralDataSize_Byte        ((uint32_t)0x00000000)
00148 #define DMA_PeripheralDataSize_HalfWord    ((uint32_t)0x00000100)
00149 #define DMA_PeripheralDataSize_Word        ((uint32_t)0x00000200)
00150 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
00151                                            ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
00152                                            ((SIZE) == DMA_PeripheralDataSize_Word))
00153 /**
00154   * @}
00155   */
00156 
00157 /** @defgroup DMA_memory_data_size 
00158   * @{
00159   */
00160 
00161 #define DMA_MemoryDataSize_Byte            ((uint32_t)0x00000000)
00162 #define DMA_MemoryDataSize_HalfWord        ((uint32_t)0x00000400)
00163 #define DMA_MemoryDataSize_Word            ((uint32_t)0x00000800)
00164 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
00165                                        ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
00166                                        ((SIZE) == DMA_MemoryDataSize_Word))
00167 /**
00168   * @}
00169   */
00170 
00171 /** @defgroup DMA_circular_normal_mode 
00172   * @{
00173   */
00174 
00175 #define DMA_Mode_Circular                  ((uint32_t)0x00000020)
00176 #define DMA_Mode_Normal                    ((uint32_t)0x00000000)
00177 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
00178 /**
00179   * @}
00180   */
00181 
00182 /** @defgroup DMA_priority_level 
00183   * @{
00184   */
00185 
00186 #define DMA_Priority_VeryHigh              ((uint32_t)0x00003000)
00187 #define DMA_Priority_High                  ((uint32_t)0x00002000)
00188 #define DMA_Priority_Medium                ((uint32_t)0x00001000)
00189 #define DMA_Priority_Low                   ((uint32_t)0x00000000)
00190 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
00191                                    ((PRIORITY) == DMA_Priority_High) || \
00192                                    ((PRIORITY) == DMA_Priority_Medium) || \
00193                                    ((PRIORITY) == DMA_Priority_Low))
00194 /**
00195   * @}
00196   */
00197 
00198 /** @defgroup DMA_memory_to_memory 
00199   * @{
00200   */
00201 
00202 #define DMA_M2M_Enable                     ((uint32_t)0x00004000)
00203 #define DMA_M2M_Disable                    ((uint32_t)0x00000000)
00204 #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
00205 
00206 /**
00207   * @}
00208   */
00209 
00210 /** @defgroup DMA_interrupts_definition 
00211   * @{
00212   */
00213 
00214 #define DMA_IT_TC                          ((uint32_t)0x00000002)
00215 #define DMA_IT_HT                          ((uint32_t)0x00000004)
00216 #define DMA_IT_TE                          ((uint32_t)0x00000008)
00217 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
00218 
00219 #define DMA1_IT_GL1                        ((uint32_t)0x00000001)
00220 #define DMA1_IT_TC1                        ((uint32_t)0x00000002)
00221 #define DMA1_IT_HT1                        ((uint32_t)0x00000004)
00222 #define DMA1_IT_TE1                        ((uint32_t)0x00000008)
00223 #define DMA1_IT_GL2                        ((uint32_t)0x00000010)
00224 #define DMA1_IT_TC2                        ((uint32_t)0x00000020)
00225 #define DMA1_IT_HT2                        ((uint32_t)0x00000040)
00226 #define DMA1_IT_TE2                        ((uint32_t)0x00000080)
00227 #define DMA1_IT_GL3                        ((uint32_t)0x00000100)
00228 #define DMA1_IT_TC3                        ((uint32_t)0x00000200)
00229 #define DMA1_IT_HT3                        ((uint32_t)0x00000400)
00230 #define DMA1_IT_TE3                        ((uint32_t)0x00000800)
00231 #define DMA1_IT_GL4                        ((uint32_t)0x00001000)
00232 #define DMA1_IT_TC4                        ((uint32_t)0x00002000)
00233 #define DMA1_IT_HT4                        ((uint32_t)0x00004000)
00234 #define DMA1_IT_TE4                        ((uint32_t)0x00008000)
00235 #define DMA1_IT_GL5                        ((uint32_t)0x00010000)
00236 #define DMA1_IT_TC5                        ((uint32_t)0x00020000)
00237 #define DMA1_IT_HT5                        ((uint32_t)0x00040000)
00238 #define DMA1_IT_TE5                        ((uint32_t)0x00080000)
00239 #define DMA1_IT_GL6                        ((uint32_t)0x00100000)
00240 #define DMA1_IT_TC6                        ((uint32_t)0x00200000)
00241 #define DMA1_IT_HT6                        ((uint32_t)0x00400000)
00242 #define DMA1_IT_TE6                        ((uint32_t)0x00800000)
00243 #define DMA1_IT_GL7                        ((uint32_t)0x01000000)
00244 #define DMA1_IT_TC7                        ((uint32_t)0x02000000)
00245 #define DMA1_IT_HT7                        ((uint32_t)0x04000000)
00246 #define DMA1_IT_TE7                        ((uint32_t)0x08000000)
00247 
00248 #define DMA2_IT_GL1                        ((uint32_t)0x10000001)
00249 #define DMA2_IT_TC1                        ((uint32_t)0x10000002)
00250 #define DMA2_IT_HT1                        ((uint32_t)0x10000004)
00251 #define DMA2_IT_TE1                        ((uint32_t)0x10000008)
00252 #define DMA2_IT_GL2                        ((uint32_t)0x10000010)
00253 #define DMA2_IT_TC2                        ((uint32_t)0x10000020)
00254 #define DMA2_IT_HT2                        ((uint32_t)0x10000040)
00255 #define DMA2_IT_TE2                        ((uint32_t)0x10000080)
00256 #define DMA2_IT_GL3                        ((uint32_t)0x10000100)
00257 #define DMA2_IT_TC3                        ((uint32_t)0x10000200)
00258 #define DMA2_IT_HT3                        ((uint32_t)0x10000400)
00259 #define DMA2_IT_TE3                        ((uint32_t)0x10000800)
00260 #define DMA2_IT_GL4                        ((uint32_t)0x10001000)
00261 #define DMA2_IT_TC4                        ((uint32_t)0x10002000)
00262 #define DMA2_IT_HT4                        ((uint32_t)0x10004000)
00263 #define DMA2_IT_TE4                        ((uint32_t)0x10008000)
00264 #define DMA2_IT_GL5                        ((uint32_t)0x10010000)
00265 #define DMA2_IT_TC5                        ((uint32_t)0x10020000)
00266 #define DMA2_IT_HT5                        ((uint32_t)0x10040000)
00267 #define DMA2_IT_TE5                        ((uint32_t)0x10080000)
00268 
00269 #define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
00270 
00271 #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
00272                            ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
00273                            ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
00274                            ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
00275                            ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
00276                            ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
00277                            ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
00278                            ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
00279                            ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
00280                            ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
00281                            ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
00282                            ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
00283                            ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
00284                            ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
00285                            ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
00286                            ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
00287                            ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
00288                            ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
00289                            ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
00290                            ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
00291                            ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
00292                            ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
00293                            ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
00294                            ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
00295 
00296 /**
00297   * @}
00298   */
00299 
00300 /** @defgroup DMA_flags_definition 
00301   * @{
00302   */
00303 #define DMA1_FLAG_GL1                      ((uint32_t)0x00000001)
00304 #define DMA1_FLAG_TC1                      ((uint32_t)0x00000002)
00305 #define DMA1_FLAG_HT1                      ((uint32_t)0x00000004)
00306 #define DMA1_FLAG_TE1                      ((uint32_t)0x00000008)
00307 #define DMA1_FLAG_GL2                      ((uint32_t)0x00000010)
00308 #define DMA1_FLAG_TC2                      ((uint32_t)0x00000020)
00309 #define DMA1_FLAG_HT2                      ((uint32_t)0x00000040)
00310 #define DMA1_FLAG_TE2                      ((uint32_t)0x00000080)
00311 #define DMA1_FLAG_GL3                      ((uint32_t)0x00000100)
00312 #define DMA1_FLAG_TC3                      ((uint32_t)0x00000200)
00313 #define DMA1_FLAG_HT3                      ((uint32_t)0x00000400)
00314 #define DMA1_FLAG_TE3                      ((uint32_t)0x00000800)
00315 #define DMA1_FLAG_GL4                      ((uint32_t)0x00001000)
00316 #define DMA1_FLAG_TC4                      ((uint32_t)0x00002000)
00317 #define DMA1_FLAG_HT4                      ((uint32_t)0x00004000)
00318 #define DMA1_FLAG_TE4                      ((uint32_t)0x00008000)
00319 #define DMA1_FLAG_GL5                      ((uint32_t)0x00010000)
00320 #define DMA1_FLAG_TC5                      ((uint32_t)0x00020000)
00321 #define DMA1_FLAG_HT5                      ((uint32_t)0x00040000)
00322 #define DMA1_FLAG_TE5                      ((uint32_t)0x00080000)
00323 #define DMA1_FLAG_GL6                      ((uint32_t)0x00100000)
00324 #define DMA1_FLAG_TC6                      ((uint32_t)0x00200000)
00325 #define DMA1_FLAG_HT6                      ((uint32_t)0x00400000)
00326 #define DMA1_FLAG_TE6                      ((uint32_t)0x00800000)
00327 #define DMA1_FLAG_GL7                      ((uint32_t)0x01000000)
00328 #define DMA1_FLAG_TC7                      ((uint32_t)0x02000000)
00329 #define DMA1_FLAG_HT7                      ((uint32_t)0x04000000)
00330 #define DMA1_FLAG_TE7                      ((uint32_t)0x08000000)
00331 
00332 #define DMA2_FLAG_GL1                      ((uint32_t)0x10000001)
00333 #define DMA2_FLAG_TC1                      ((uint32_t)0x10000002)
00334 #define DMA2_FLAG_HT1                      ((uint32_t)0x10000004)
00335 #define DMA2_FLAG_TE1                      ((uint32_t)0x10000008)
00336 #define DMA2_FLAG_GL2                      ((uint32_t)0x10000010)
00337 #define DMA2_FLAG_TC2                      ((uint32_t)0x10000020)
00338 #define DMA2_FLAG_HT2                      ((uint32_t)0x10000040)
00339 #define DMA2_FLAG_TE2                      ((uint32_t)0x10000080)
00340 #define DMA2_FLAG_GL3                      ((uint32_t)0x10000100)
00341 #define DMA2_FLAG_TC3                      ((uint32_t)0x10000200)
00342 #define DMA2_FLAG_HT3                      ((uint32_t)0x10000400)
00343 #define DMA2_FLAG_TE3                      ((uint32_t)0x10000800)
00344 #define DMA2_FLAG_GL4                      ((uint32_t)0x10001000)
00345 #define DMA2_FLAG_TC4                      ((uint32_t)0x10002000)
00346 #define DMA2_FLAG_HT4                      ((uint32_t)0x10004000)
00347 #define DMA2_FLAG_TE4                      ((uint32_t)0x10008000)
00348 #define DMA2_FLAG_GL5                      ((uint32_t)0x10010000)
00349 #define DMA2_FLAG_TC5                      ((uint32_t)0x10020000)
00350 #define DMA2_FLAG_HT5                      ((uint32_t)0x10040000)
00351 #define DMA2_FLAG_TE5                      ((uint32_t)0x10080000)
00352 
00353 #define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
00354 
00355 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
00356                                ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
00357                                ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
00358                                ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
00359                                ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
00360                                ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
00361                                ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
00362                                ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
00363                                ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
00364                                ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
00365                                ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
00366                                ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
00367                                ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
00368                                ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
00369                                ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
00370                                ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
00371                                ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
00372                                ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
00373                                ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
00374                                ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
00375                                ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
00376                                ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
00377                                ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
00378                                ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
00379 /**
00380   * @}
00381   */
00382 
00383 /** @defgroup DMA_Buffer_Size 
00384   * @{
00385   */
00386 
00387 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
00388 
00389 /**
00390   * @}
00391   */
00392 
00393 /**
00394   * @}
00395   */
00396 
00397 /** @defgroup DMA_Exported_Macros
00398   * @{
00399   */
00400 
00401 /**
00402   * @}
00403   */
00404 
00405 /** @defgroup DMA_Exported_Functions
00406   * @{
00407   */
00408 
00409 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
00410 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
00411 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
00412 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
00413 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
00414 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); 
00415 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
00416 FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
00417 void DMA_ClearFlag(uint32_t DMA_FLAG);
00418 ITStatus DMA_GetITStatus(uint32_t DMA_IT);
00419 void DMA_ClearITPendingBit(uint32_t DMA_IT);
00420 
00421 #ifdef __cplusplus
00422 }
00423 #endif
00424 
00425 #endif /*__STM32F10x_DMA_H */
00426 /**
00427   * @}
00428   */
00429 
00430 /**
00431   * @}
00432   */
00433 
00434 /**
00435   * @}
00436   */
00437 
00438 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
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