stm32f10x_dma.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_dma.c
00004   * @author  MCD Application Team
00005   * @version V3.4.0
00006   * @date    10/15/2010
00007   * @brief   This file provides all the DMA firmware functions.
00008   ******************************************************************************
00009   * @copy
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
00019   */ 
00020 
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32f10x_dma.h"
00023 #include "stm32f10x_rcc.h"
00024 
00025 /** @addtogroup STM32F10x_StdPeriph_Driver
00026   * @{
00027   */
00028 
00029 /** @defgroup DMA 
00030   * @brief DMA driver modules
00031   * @{
00032   */ 
00033 
00034 /** @defgroup DMA_Private_TypesDefinitions
00035   * @{
00036   */ 
00037 /**
00038   * @}
00039   */
00040 
00041 /** @defgroup DMA_Private_Defines
00042   * @{
00043   */
00044 
00045 
00046 /* DMA1 Channelx interrupt pending bit masks */
00047 #define DMA1_Channel1_IT_Mask    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
00048 #define DMA1_Channel2_IT_Mask    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
00049 #define DMA1_Channel3_IT_Mask    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
00050 #define DMA1_Channel4_IT_Mask    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
00051 #define DMA1_Channel5_IT_Mask    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
00052 #define DMA1_Channel6_IT_Mask    ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
00053 #define DMA1_Channel7_IT_Mask    ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
00054 
00055 /* DMA2 Channelx interrupt pending bit masks */
00056 #define DMA2_Channel1_IT_Mask    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
00057 #define DMA2_Channel2_IT_Mask    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
00058 #define DMA2_Channel3_IT_Mask    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
00059 #define DMA2_Channel4_IT_Mask    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
00060 #define DMA2_Channel5_IT_Mask    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
00061 
00062 /* DMA2 FLAG mask */
00063 #define FLAG_Mask                ((uint32_t)0x10000000)
00064 
00065 /* DMA registers Masks */
00066 #define CCR_CLEAR_Mask           ((uint32_t)0xFFFF800F)
00067 
00068 /**
00069   * @}
00070   */
00071 
00072 /** @defgroup DMA_Private_Macros
00073   * @{
00074   */
00075 
00076 /**
00077   * @}
00078   */
00079 
00080 /** @defgroup DMA_Private_Variables
00081   * @{
00082   */
00083 
00084 /**
00085   * @}
00086   */
00087 
00088 /** @defgroup DMA_Private_FunctionPrototypes
00089   * @{
00090   */
00091 
00092 /**
00093   * @}
00094   */
00095 
00096 /** @defgroup DMA_Private_Functions
00097   * @{
00098   */
00099 
00100 /**
00101   * @brief  Deinitializes the DMAy Channelx registers to their default reset
00102   *   values.
00103   * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
00104   *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
00105   * @retval None
00106   */
00107 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
00108 {
00109   /* Check the parameters */
00110   assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00111   
00112   /* Disable the selected DMAy Channelx */
00113   DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
00114   
00115   /* Reset DMAy Channelx control register */
00116   DMAy_Channelx->CCR  = 0;
00117   
00118   /* Reset DMAy Channelx remaining bytes register */
00119   DMAy_Channelx->CNDTR = 0;
00120   
00121   /* Reset DMAy Channelx peripheral address register */
00122   DMAy_Channelx->CPAR  = 0;
00123   
00124   /* Reset DMAy Channelx memory address register */
00125   DMAy_Channelx->CMAR = 0;
00126   
00127   if (DMAy_Channelx == DMA1_Channel1)
00128   {
00129     /* Reset interrupt pending bits for DMA1 Channel1 */
00130     DMA1->IFCR |= DMA1_Channel1_IT_Mask;
00131   }
00132   else if (DMAy_Channelx == DMA1_Channel2)
00133   {
00134     /* Reset interrupt pending bits for DMA1 Channel2 */
00135     DMA1->IFCR |= DMA1_Channel2_IT_Mask;
00136   }
00137   else if (DMAy_Channelx == DMA1_Channel3)
00138   {
00139     /* Reset interrupt pending bits for DMA1 Channel3 */
00140     DMA1->IFCR |= DMA1_Channel3_IT_Mask;
00141   }
00142   else if (DMAy_Channelx == DMA1_Channel4)
00143   {
00144     /* Reset interrupt pending bits for DMA1 Channel4 */
00145     DMA1->IFCR |= DMA1_Channel4_IT_Mask;
00146   }
00147   else if (DMAy_Channelx == DMA1_Channel5)
00148   {
00149     /* Reset interrupt pending bits for DMA1 Channel5 */
00150     DMA1->IFCR |= DMA1_Channel5_IT_Mask;
00151   }
00152   else if (DMAy_Channelx == DMA1_Channel6)
00153   {
00154     /* Reset interrupt pending bits for DMA1 Channel6 */
00155     DMA1->IFCR |= DMA1_Channel6_IT_Mask;
00156   }
00157   else if (DMAy_Channelx == DMA1_Channel7)
00158   {
00159     /* Reset interrupt pending bits for DMA1 Channel7 */
00160     DMA1->IFCR |= DMA1_Channel7_IT_Mask;
00161   }
00162   else if (DMAy_Channelx == DMA2_Channel1)
00163   {
00164     /* Reset interrupt pending bits for DMA2 Channel1 */
00165     DMA2->IFCR |= DMA2_Channel1_IT_Mask;
00166   }
00167   else if (DMAy_Channelx == DMA2_Channel2)
00168   {
00169     /* Reset interrupt pending bits for DMA2 Channel2 */
00170     DMA2->IFCR |= DMA2_Channel2_IT_Mask;
00171   }
00172   else if (DMAy_Channelx == DMA2_Channel3)
00173   {
00174     /* Reset interrupt pending bits for DMA2 Channel3 */
00175     DMA2->IFCR |= DMA2_Channel3_IT_Mask;
00176   }
00177   else if (DMAy_Channelx == DMA2_Channel4)
00178   {
00179     /* Reset interrupt pending bits for DMA2 Channel4 */
00180     DMA2->IFCR |= DMA2_Channel4_IT_Mask;
00181   }
00182   else
00183   { 
00184     if (DMAy_Channelx == DMA2_Channel5)
00185     {
00186       /* Reset interrupt pending bits for DMA2 Channel5 */
00187       DMA2->IFCR |= DMA2_Channel5_IT_Mask;
00188     }
00189   }
00190 }
00191 
00192 /**
00193   * @brief  Initializes the DMAy Channelx according to the specified
00194   *   parameters in the DMA_InitStruct.
00195   * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
00196   *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
00197   * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
00198   *   contains the configuration information for the specified DMA Channel.
00199   * @retval None
00200   */
00201 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
00202 {
00203   uint32_t tmpreg = 0;
00204 
00205   /* Check the parameters */
00206   assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00207   assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
00208   assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
00209   assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
00210   assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));   
00211   assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
00212   assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
00213   assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
00214   assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
00215   assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
00216 
00217 /*--------------------------- DMAy Channelx CCR Configuration -----------------*/
00218   /* Get the DMAy_Channelx CCR value */
00219   tmpreg = DMAy_Channelx->CCR;
00220   /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
00221   tmpreg &= CCR_CLEAR_Mask;
00222   /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
00223   /* Set DIR bit according to DMA_DIR value */
00224   /* Set CIRC bit according to DMA_Mode value */
00225   /* Set PINC bit according to DMA_PeripheralInc value */
00226   /* Set MINC bit according to DMA_MemoryInc value */
00227   /* Set PSIZE bits according to DMA_PeripheralDataSize value */
00228   /* Set MSIZE bits according to DMA_MemoryDataSize value */
00229   /* Set PL bits according to DMA_Priority value */
00230   /* Set the MEM2MEM bit according to DMA_M2M value */
00231   tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
00232             DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
00233             DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
00234             DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
00235 
00236   /* Write to DMAy Channelx CCR */
00237   DMAy_Channelx->CCR = tmpreg;
00238 
00239 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
00240   /* Write to DMAy Channelx CNDTR */
00241   DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
00242 
00243 /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
00244   /* Write to DMAy Channelx CPAR */
00245   DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
00246 
00247 /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
00248   /* Write to DMAy Channelx CMAR */
00249   DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
00250 }
00251 
00252 /**
00253   * @brief  Fills each DMA_InitStruct member with its default value.
00254   * @param  DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
00255   *   be initialized.
00256   * @retval None
00257   */
00258 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
00259 {
00260 /*-------------- Reset DMA init structure parameters values ------------------*/
00261   /* Initialize the DMA_PeripheralBaseAddr member */
00262   DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
00263   /* Initialize the DMA_MemoryBaseAddr member */
00264   DMA_InitStruct->DMA_MemoryBaseAddr = 0;
00265   /* Initialize the DMA_DIR member */
00266   DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
00267   /* Initialize the DMA_BufferSize member */
00268   DMA_InitStruct->DMA_BufferSize = 0;
00269   /* Initialize the DMA_PeripheralInc member */
00270   DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00271   /* Initialize the DMA_MemoryInc member */
00272   DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
00273   /* Initialize the DMA_PeripheralDataSize member */
00274   DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
00275   /* Initialize the DMA_MemoryDataSize member */
00276   DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
00277   /* Initialize the DMA_Mode member */
00278   DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
00279   /* Initialize the DMA_Priority member */
00280   DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
00281   /* Initialize the DMA_M2M member */
00282   DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
00283 }
00284 
00285 /**
00286   * @brief  Enables or disables the specified DMAy Channelx.
00287   * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
00288   *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
00289   * @param  NewState: new state of the DMAy Channelx. 
00290   *   This parameter can be: ENABLE or DISABLE.
00291   * @retval None
00292   */
00293 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
00294 {
00295   /* Check the parameters */
00296   assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00297   assert_param(IS_FUNCTIONAL_STATE(NewState));
00298 
00299   if (NewState != DISABLE)
00300   {
00301     /* Enable the selected DMAy Channelx */
00302     DMAy_Channelx->CCR |= DMA_CCR1_EN;
00303   }
00304   else
00305   {
00306     /* Disable the selected DMAy Channelx */
00307     DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
00308   }
00309 }
00310 
00311 /**
00312   * @brief  Enables or disables the specified DMAy Channelx interrupts.
00313   * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
00314   *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
00315   * @param  DMA_IT: specifies the DMA interrupts sources to be enabled
00316   *   or disabled. 
00317   *   This parameter can be any combination of the following values:
00318   *     @arg DMA_IT_TC:  Transfer complete interrupt mask
00319   *     @arg DMA_IT_HT:  Half transfer interrupt mask
00320   *     @arg DMA_IT_TE:  Transfer error interrupt mask
00321   * @param  NewState: new state of the specified DMA interrupts.
00322   *   This parameter can be: ENABLE or DISABLE.
00323   * @retval None
00324   */
00325 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
00326 {
00327   /* Check the parameters */
00328   assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00329   assert_param(IS_DMA_CONFIG_IT(DMA_IT));
00330   assert_param(IS_FUNCTIONAL_STATE(NewState));
00331   if (NewState != DISABLE)
00332   {
00333     /* Enable the selected DMA interrupts */
00334     DMAy_Channelx->CCR |= DMA_IT;
00335   }
00336   else
00337   {
00338     /* Disable the selected DMA interrupts */
00339     DMAy_Channelx->CCR &= ~DMA_IT;
00340   }
00341 }
00342 
00343 /**
00344   * @brief  Sets the number of data units in the current DMAy Channelx transfer.
00345   * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
00346   *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
00347   * @param  DataNumber: The number of data units in the current DMAy Channelx
00348   *         transfer.   
00349   * @note   This function can only be used when the DMAy_Channelx is disabled.                 
00350   * @retval None.
00351   */
00352 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
00353 {
00354   /* Check the parameters */
00355   assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00356   
00357 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
00358   /* Write to DMAy Channelx CNDTR */
00359   DMAy_Channelx->CNDTR = DataNumber;  
00360 }
00361 
00362 /**
00363   * @brief  Returns the number of remaining data units in the current
00364   *   DMAy Channelx transfer.
00365   * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
00366   *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
00367   * @retval The number of remaining data units in the current DMAy Channelx
00368   *   transfer.
00369   */
00370 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
00371 {
00372   /* Check the parameters */
00373   assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00374   /* Return the number of remaining data units for DMAy Channelx */
00375   return ((uint16_t)(DMAy_Channelx->CNDTR));
00376 }
00377 
00378 /**
00379   * @brief  Checks whether the specified DMAy Channelx flag is set or not.
00380   * @param  DMA_FLAG: specifies the flag to check.
00381   *   This parameter can be one of the following values:
00382   *     @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
00383   *     @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
00384   *     @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
00385   *     @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
00386   *     @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
00387   *     @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
00388   *     @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
00389   *     @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
00390   *     @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
00391   *     @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
00392   *     @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
00393   *     @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
00394   *     @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
00395   *     @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
00396   *     @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
00397   *     @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
00398   *     @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
00399   *     @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
00400   *     @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
00401   *     @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
00402   *     @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
00403   *     @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
00404   *     @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
00405   *     @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
00406   *     @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
00407   *     @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
00408   *     @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
00409   *     @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
00410   *     @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
00411   *     @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
00412   *     @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
00413   *     @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
00414   *     @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
00415   *     @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
00416   *     @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
00417   *     @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
00418   *     @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
00419   *     @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
00420   *     @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
00421   *     @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
00422   *     @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
00423   *     @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
00424   *     @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
00425   *     @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
00426   *     @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
00427   *     @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
00428   *     @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
00429   *     @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
00430   * @retval The new state of DMA_FLAG (SET or RESET).
00431   */
00432 FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)
00433 {
00434   FlagStatus bitstatus = RESET;
00435   uint32_t tmpreg = 0;
00436   /* Check the parameters */
00437   assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
00438 
00439   /* Calculate the used DMA */
00440   if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)
00441   {
00442     /* Get DMA2 ISR register value */
00443     tmpreg = DMA2->ISR ;
00444   }
00445   else
00446   {
00447     /* Get DMA1 ISR register value */
00448     tmpreg = DMA1->ISR ;
00449   }
00450 
00451   /* Check the status of the specified DMA flag */
00452   if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
00453   {
00454     /* DMA_FLAG is set */
00455     bitstatus = SET;
00456   }
00457   else
00458   {
00459     /* DMA_FLAG is reset */
00460     bitstatus = RESET;
00461   }
00462   
00463   /* Return the DMA_FLAG status */
00464   return  bitstatus;
00465 }
00466 
00467 /**
00468   * @brief  Clears the DMAy Channelx's pending flags.
00469   * @param  DMA_FLAG: specifies the flag to clear.
00470   *   This parameter can be any combination (for the same DMA) of the following values:
00471   *     @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
00472   *     @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
00473   *     @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
00474   *     @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
00475   *     @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
00476   *     @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
00477   *     @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
00478   *     @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
00479   *     @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
00480   *     @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
00481   *     @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
00482   *     @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
00483   *     @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
00484   *     @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
00485   *     @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
00486   *     @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
00487   *     @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
00488   *     @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
00489   *     @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
00490   *     @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
00491   *     @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
00492   *     @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
00493   *     @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
00494   *     @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
00495   *     @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
00496   *     @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
00497   *     @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
00498   *     @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
00499   *     @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
00500   *     @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
00501   *     @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
00502   *     @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
00503   *     @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
00504   *     @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
00505   *     @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
00506   *     @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
00507   *     @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
00508   *     @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
00509   *     @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
00510   *     @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
00511   *     @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
00512   *     @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
00513   *     @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
00514   *     @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
00515   *     @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
00516   *     @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
00517   *     @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
00518   *     @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
00519   * @retval None
00520   */
00521 void DMA_ClearFlag(uint32_t DMA_FLAG)
00522 {
00523   /* Check the parameters */
00524   assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
00525   /* Calculate the used DMA */
00526 
00527   if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)
00528   {
00529     /* Clear the selected DMA flags */
00530     DMA2->IFCR = DMA_FLAG;
00531   }
00532   else
00533   {
00534     /* Clear the selected DMA flags */
00535     DMA1->IFCR = DMA_FLAG;
00536   }
00537 }
00538 
00539 /**
00540   * @brief  Checks whether the specified DMAy Channelx interrupt has occurred or not.
00541   * @param  DMA_IT: specifies the DMA interrupt source to check. 
00542   *   This parameter can be one of the following values:
00543   *     @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
00544   *     @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
00545   *     @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
00546   *     @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
00547   *     @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
00548   *     @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
00549   *     @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
00550   *     @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
00551   *     @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
00552   *     @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
00553   *     @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
00554   *     @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
00555   *     @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
00556   *     @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
00557   *     @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
00558   *     @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
00559   *     @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
00560   *     @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
00561   *     @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
00562   *     @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
00563   *     @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
00564   *     @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
00565   *     @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
00566   *     @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
00567   *     @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
00568   *     @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
00569   *     @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
00570   *     @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
00571   *     @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
00572   *     @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
00573   *     @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
00574   *     @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
00575   *     @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
00576   *     @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
00577   *     @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
00578   *     @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
00579   *     @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
00580   *     @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
00581   *     @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
00582   *     @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
00583   *     @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
00584   *     @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
00585   *     @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
00586   *     @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
00587   *     @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
00588   *     @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
00589   *     @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
00590   *     @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
00591   * @retval The new state of DMA_IT (SET or RESET).
00592   */
00593 ITStatus DMA_GetITStatus(uint32_t DMA_IT)
00594 {
00595   ITStatus bitstatus = RESET;
00596   uint32_t tmpreg = 0;
00597   /* Check the parameters */
00598   assert_param(IS_DMA_GET_IT(DMA_IT));
00599 
00600   /* Calculate the used DMA */
00601   if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)
00602   {
00603     /* Get DMA2 ISR register value */
00604     tmpreg = DMA2->ISR ;
00605   }
00606   else
00607   {
00608     /* Get DMA1 ISR register value */
00609     tmpreg = DMA1->ISR ;
00610   }
00611 
00612   /* Check the status of the specified DMA interrupt */
00613   if ((tmpreg & DMA_IT) != (uint32_t)RESET)
00614   {
00615     /* DMA_IT is set */
00616     bitstatus = SET;
00617   }
00618   else
00619   {
00620     /* DMA_IT is reset */
00621     bitstatus = RESET;
00622   }
00623   /* Return the DMA_IT status */
00624   return  bitstatus;
00625 }
00626 
00627 /**
00628   * @brief  Clears the DMAy Channelx’s interrupt pending bits.
00629   * @param  DMA_IT: specifies the DMA interrupt pending bit to clear.
00630   *   This parameter can be any combination (for the same DMA) of the following values:
00631   *     @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
00632   *     @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
00633   *     @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
00634   *     @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
00635   *     @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
00636   *     @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
00637   *     @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
00638   *     @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
00639   *     @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
00640   *     @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
00641   *     @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
00642   *     @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
00643   *     @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
00644   *     @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
00645   *     @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
00646   *     @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
00647   *     @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
00648   *     @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
00649   *     @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
00650   *     @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
00651   *     @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
00652   *     @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
00653   *     @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
00654   *     @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
00655   *     @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
00656   *     @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
00657   *     @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
00658   *     @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
00659   *     @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
00660   *     @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
00661   *     @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
00662   *     @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
00663   *     @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
00664   *     @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
00665   *     @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
00666   *     @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
00667   *     @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
00668   *     @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
00669   *     @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
00670   *     @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
00671   *     @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
00672   *     @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
00673   *     @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
00674   *     @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
00675   *     @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
00676   *     @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
00677   *     @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
00678   *     @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
00679   * @retval None
00680   */
00681 void DMA_ClearITPendingBit(uint32_t DMA_IT)
00682 {
00683   /* Check the parameters */
00684   assert_param(IS_DMA_CLEAR_IT(DMA_IT));
00685 
00686   /* Calculate the used DMA */
00687   if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)
00688   {
00689     /* Clear the selected DMA interrupt pending bits */
00690     DMA2->IFCR = DMA_IT;
00691   }
00692   else
00693   {
00694     /* Clear the selected DMA interrupt pending bits */
00695     DMA1->IFCR = DMA_IT;
00696   }
00697 }
00698 
00699 /**
00700   * @}
00701   */
00702 
00703 /**
00704   * @}
00705   */
00706 
00707 /**
00708   * @}
00709   */
00710 
00711 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
STM32F10x Standard Peripherals Library: Footer

 

 

 

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