stm32f10x_dac.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_dac.c
00004   * @author  MCD Application Team
00005   * @version V3.4.0
00006   * @date    10/15/2010
00007   * @brief   This file provides all the DAC firmware functions.
00008   ******************************************************************************
00009   * @copy
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
00019   */ 
00020 
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32f10x_dac.h"
00023 #include "stm32f10x_rcc.h"
00024 
00025 /** @addtogroup STM32F10x_StdPeriph_Driver
00026   * @{
00027   */
00028 
00029 /** @defgroup DAC 
00030   * @brief DAC driver modules
00031   * @{
00032   */ 
00033 
00034 /** @defgroup DAC_Private_TypesDefinitions
00035   * @{
00036   */
00037 
00038 /**
00039   * @}
00040   */
00041 
00042 /** @defgroup DAC_Private_Defines
00043   * @{
00044   */
00045 
00046 /* CR register Mask */
00047 #define CR_CLEAR_MASK              ((uint32_t)0x00000FFE)
00048 
00049 /* DAC Dual Channels SWTRIG masks */
00050 #define DUAL_SWTRIG_SET            ((uint32_t)0x00000003)
00051 #define DUAL_SWTRIG_RESET          ((uint32_t)0xFFFFFFFC)
00052 
00053 /* DHR registers offsets */
00054 #define DHR12R1_OFFSET             ((uint32_t)0x00000008)
00055 #define DHR12R2_OFFSET             ((uint32_t)0x00000014)
00056 #define DHR12RD_OFFSET             ((uint32_t)0x00000020)
00057 
00058 /* DOR register offset */
00059 #define DOR_OFFSET                 ((uint32_t)0x0000002C)
00060 /**
00061   * @}
00062   */
00063 
00064 /** @defgroup DAC_Private_Macros
00065   * @{
00066   */
00067 
00068 /**
00069   * @}
00070   */
00071 
00072 /** @defgroup DAC_Private_Variables
00073   * @{
00074   */
00075 
00076 /**
00077   * @}
00078   */
00079 
00080 /** @defgroup DAC_Private_FunctionPrototypes
00081   * @{
00082   */
00083 
00084 /**
00085   * @}
00086   */
00087 
00088 /** @defgroup DAC_Private_Functions
00089   * @{
00090   */
00091 
00092 /**
00093   * @brief  Deinitializes the DAC peripheral registers to their default reset values.
00094   * @param  None
00095   * @retval None
00096   */
00097 void DAC_DeInit(void)
00098 {
00099   /* Enable DAC reset state */
00100   RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
00101   /* Release DAC from reset state */
00102   RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
00103 }
00104 
00105 /**
00106   * @brief  Initializes the DAC peripheral according to the specified 
00107   *   parameters in the DAC_InitStruct.
00108   * @param  DAC_Channel: the selected DAC channel. 
00109   *   This parameter can be one of the following values:
00110   *     @arg DAC_Channel_1: DAC Channel1 selected
00111   *     @arg DAC_Channel_2: DAC Channel2 selected
00112   * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
00113   *   contains the configuration information for the specified DAC channel.
00114   * @retval None
00115   */
00116 void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
00117 {
00118   uint32_t tmpreg1 = 0, tmpreg2 = 0;
00119   /* Check the DAC parameters */
00120   assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
00121   assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
00122   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
00123   assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
00124 /*---------------------------- DAC CR Configuration --------------------------*/
00125   /* Get the DAC CR value */
00126   tmpreg1 = DAC->CR;
00127   /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
00128   tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
00129   /* Configure for the selected DAC channel: buffer output, trigger, wave genration,
00130      mask/amplitude for wave genration */
00131   /* Set TSELx and TENx bits according to DAC_Trigger value */
00132   /* Set WAVEx bits according to DAC_WaveGeneration value */
00133   /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ 
00134   /* Set BOFFx bit according to DAC_OutputBuffer value */   
00135   tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
00136              DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
00137   /* Calculate CR register value depending on DAC_Channel */
00138   tmpreg1 |= tmpreg2 << DAC_Channel;
00139   /* Write to DAC CR */
00140   DAC->CR = tmpreg1;
00141 }
00142 
00143 /**
00144   * @brief  Fills each DAC_InitStruct member with its default value.
00145   * @param  DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will
00146   *   be initialized.
00147   * @retval None
00148   */
00149 void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
00150 {
00151 /*--------------- Reset DAC init structure parameters values -----------------*/
00152   /* Initialize the DAC_Trigger member */
00153   DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
00154   /* Initialize the DAC_WaveGeneration member */
00155   DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
00156   /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
00157   DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
00158   /* Initialize the DAC_OutputBuffer member */
00159   DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
00160 }
00161 
00162 /**
00163   * @brief  Enables or disables the specified DAC channel.
00164   * @param  DAC_Channel: the selected DAC channel. 
00165   *   This parameter can be one of the following values:
00166   *     @arg DAC_Channel_1: DAC Channel1 selected
00167   *     @arg DAC_Channel_2: DAC Channel2 selected
00168   * @param  NewState: new state of the DAC channel. 
00169   *   This parameter can be: ENABLE or DISABLE.
00170   * @retval None
00171   */
00172 void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
00173 {
00174   /* Check the parameters */
00175   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00176   assert_param(IS_FUNCTIONAL_STATE(NewState));
00177   if (NewState != DISABLE)
00178   {
00179     /* Enable the selected DAC channel */
00180     DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
00181   }
00182   else
00183   {
00184     /* Disable the selected DAC channel */
00185     DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel);
00186   }
00187 }
00188 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00189 /**
00190   * @brief  Enables or disables the specified DAC interrupts.
00191   * @param  DAC_Channel: the selected DAC channel. 
00192   *   This parameter can be one of the following values:
00193   *     @arg DAC_Channel_1: DAC Channel1 selected
00194   *     @arg DAC_Channel_2: DAC Channel2 selected
00195   * @param  DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. 
00196   *   This parameter can be the following values:
00197   *     @arg DAC_IT_DMAUDR: DMA underrun interrupt mask                      
00198   * @param  NewState: new state of the specified DAC interrupts.
00199   *   This parameter can be: ENABLE or DISABLE.
00200   * @retval None
00201   */ 
00202 void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)  
00203 {
00204   /* Check the parameters */
00205   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00206   assert_param(IS_FUNCTIONAL_STATE(NewState));
00207   assert_param(IS_DAC_IT(DAC_IT)); 
00208 
00209   if (NewState != DISABLE)
00210   {
00211     /* Enable the selected DAC interrupts */
00212     DAC->CR |=  (DAC_IT << DAC_Channel);
00213   }
00214   else
00215   {
00216     /* Disable the selected DAC interrupts */
00217     DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
00218   }
00219 }
00220 #endif
00221 
00222 /**
00223   * @brief  Enables or disables the specified DAC channel DMA request.
00224   * @param  DAC_Channel: the selected DAC channel. 
00225   *   This parameter can be one of the following values:
00226   *     @arg DAC_Channel_1: DAC Channel1 selected
00227   *     @arg DAC_Channel_2: DAC Channel2 selected
00228   * @param  NewState: new state of the selected DAC channel DMA request.
00229   *   This parameter can be: ENABLE or DISABLE.
00230   * @retval None
00231   */
00232 void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
00233 {
00234   /* Check the parameters */
00235   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00236   assert_param(IS_FUNCTIONAL_STATE(NewState));
00237   if (NewState != DISABLE)
00238   {
00239     /* Enable the selected DAC channel DMA request */
00240     DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
00241   }
00242   else
00243   {
00244     /* Disable the selected DAC channel DMA request */
00245     DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel);
00246   }
00247 }
00248 
00249 /**
00250   * @brief  Enables or disables the selected DAC channel software trigger.
00251   * @param  DAC_Channel: the selected DAC channel. 
00252   *   This parameter can be one of the following values:
00253   *     @arg DAC_Channel_1: DAC Channel1 selected
00254   *     @arg DAC_Channel_2: DAC Channel2 selected
00255   * @param  NewState: new state of the selected DAC channel software trigger.
00256   *   This parameter can be: ENABLE or DISABLE.
00257   * @retval None
00258   */
00259 void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
00260 {
00261   /* Check the parameters */
00262   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00263   assert_param(IS_FUNCTIONAL_STATE(NewState));
00264   if (NewState != DISABLE)
00265   {
00266     /* Enable software trigger for the selected DAC channel */
00267     DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
00268   }
00269   else
00270   {
00271     /* Disable software trigger for the selected DAC channel */
00272     DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
00273   }
00274 }
00275 
00276 /**
00277   * @brief  Enables or disables simultaneously the two DAC channels software
00278   *   triggers.
00279   * @param  NewState: new state of the DAC channels software triggers.
00280   *   This parameter can be: ENABLE or DISABLE.
00281   * @retval None
00282   */
00283 void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
00284 {
00285   /* Check the parameters */
00286   assert_param(IS_FUNCTIONAL_STATE(NewState));
00287   if (NewState != DISABLE)
00288   {
00289     /* Enable software trigger for both DAC channels */
00290     DAC->SWTRIGR |= DUAL_SWTRIG_SET ;
00291   }
00292   else
00293   {
00294     /* Disable software trigger for both DAC channels */
00295     DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
00296   }
00297 }
00298 
00299 /**
00300   * @brief  Enables or disables the selected DAC channel wave generation.
00301   * @param  DAC_Channel: the selected DAC channel. 
00302   *   This parameter can be one of the following values:
00303   *     @arg DAC_Channel_1: DAC Channel1 selected
00304   *     @arg DAC_Channel_2: DAC Channel2 selected
00305   * @param  DAC_Wave: Specifies the wave type to enable or disable.
00306   *   This parameter can be one of the following values:
00307   *     @arg DAC_Wave_Noise: noise wave generation
00308   *     @arg DAC_Wave_Triangle: triangle wave generation
00309   * @param  NewState: new state of the selected DAC channel wave generation.
00310   *   This parameter can be: ENABLE or DISABLE.
00311   * @retval None
00312   */
00313 void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
00314 {
00315   /* Check the parameters */
00316   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00317   assert_param(IS_DAC_WAVE(DAC_Wave)); 
00318   assert_param(IS_FUNCTIONAL_STATE(NewState));
00319   if (NewState != DISABLE)
00320   {
00321     /* Enable the selected wave generation for the selected DAC channel */
00322     DAC->CR |= DAC_Wave << DAC_Channel;
00323   }
00324   else
00325   {
00326     /* Disable the selected wave generation for the selected DAC channel */
00327     DAC->CR &= ~(DAC_Wave << DAC_Channel);
00328   }
00329 }
00330 
00331 /**
00332   * @brief  Set the specified data holding register value for DAC channel1.
00333   * @param  DAC_Align: Specifies the data alignement for DAC channel1.
00334   *   This parameter can be one of the following values:
00335   *     @arg DAC_Align_8b_R: 8bit right data alignement selected
00336   *     @arg DAC_Align_12b_L: 12bit left data alignement selected
00337   *     @arg DAC_Align_12b_R: 12bit right data alignement selected
00338   * @param  Data : Data to be loaded in the selected data holding register.
00339   * @retval None
00340   */
00341 void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
00342 {  
00343   __IO uint32_t tmp = 0;
00344   
00345   /* Check the parameters */
00346   assert_param(IS_DAC_ALIGN(DAC_Align));
00347   assert_param(IS_DAC_DATA(Data));
00348   
00349   tmp = (uint32_t)DAC_BASE; 
00350   tmp += DHR12R1_OFFSET + DAC_Align;
00351 
00352   /* Set the DAC channel1 selected data holding register */
00353   *(__IO uint32_t *) tmp = Data;
00354 }
00355 
00356 /**
00357   * @brief  Set the specified data holding register value for DAC channel2.
00358   * @param  DAC_Align: Specifies the data alignement for DAC channel2.
00359   *   This parameter can be one of the following values:
00360   *     @arg DAC_Align_8b_R: 8bit right data alignement selected
00361   *     @arg DAC_Align_12b_L: 12bit left data alignement selected
00362   *     @arg DAC_Align_12b_R: 12bit right data alignement selected
00363   * @param  Data : Data to be loaded in the selected data holding register.
00364   * @retval None
00365   */
00366 void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
00367 {
00368   __IO uint32_t tmp = 0;
00369 
00370   /* Check the parameters */
00371   assert_param(IS_DAC_ALIGN(DAC_Align));
00372   assert_param(IS_DAC_DATA(Data));
00373   
00374   tmp = (uint32_t)DAC_BASE;
00375   tmp += DHR12R2_OFFSET + DAC_Align;
00376 
00377   /* Set the DAC channel2 selected data holding register */
00378   *(__IO uint32_t *)tmp = Data;
00379 }
00380 
00381 /**
00382   * @brief  Set the specified data holding register value for dual channel
00383   *   DAC.
00384   * @param  DAC_Align: Specifies the data alignement for dual channel DAC.
00385   *   This parameter can be one of the following values:
00386   *     @arg DAC_Align_8b_R: 8bit right data alignement selected
00387   *     @arg DAC_Align_12b_L: 12bit left data alignement selected
00388   *     @arg DAC_Align_12b_R: 12bit right data alignement selected
00389   * @param  Data2: Data for DAC Channel2 to be loaded in the selected data 
00390   *   holding register.
00391   * @param  Data1: Data for DAC Channel1 to be loaded in the selected data 
00392   *   holding register.
00393   * @retval None
00394   */
00395 void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
00396 {
00397   uint32_t data = 0, tmp = 0;
00398   
00399   /* Check the parameters */
00400   assert_param(IS_DAC_ALIGN(DAC_Align));
00401   assert_param(IS_DAC_DATA(Data1));
00402   assert_param(IS_DAC_DATA(Data2));
00403   
00404   /* Calculate and set dual DAC data holding register value */
00405   if (DAC_Align == DAC_Align_8b_R)
00406   {
00407     data = ((uint32_t)Data2 << 8) | Data1; 
00408   }
00409   else
00410   {
00411     data = ((uint32_t)Data2 << 16) | Data1;
00412   }
00413   
00414   tmp = (uint32_t)DAC_BASE;
00415   tmp += DHR12RD_OFFSET + DAC_Align;
00416 
00417   /* Set the dual DAC selected data holding register */
00418   *(__IO uint32_t *)tmp = data;
00419 }
00420 
00421 /**
00422   * @brief  Returns the last data output value of the selected DAC cahnnel.
00423   * @param  DAC_Channel: the selected DAC channel. 
00424   *   This parameter can be one of the following values:
00425   *     @arg DAC_Channel_1: DAC Channel1 selected
00426   *     @arg DAC_Channel_2: DAC Channel2 selected
00427   * @retval The selected DAC channel data output value.
00428   */
00429 uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
00430 {
00431   __IO uint32_t tmp = 0;
00432   
00433   /* Check the parameters */
00434   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00435   
00436   tmp = (uint32_t) DAC_BASE ;
00437   tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
00438   
00439   /* Returns the DAC channel data output register value */
00440   return (uint16_t) (*(__IO uint32_t*) tmp);
00441 }
00442 
00443 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00444 /**
00445   * @brief  Checks whether the specified DAC flag is set or not.
00446   * @param  DAC_Channel: thee selected DAC channel. 
00447   *   This parameter can be one of the following values:
00448   *     @arg DAC_Channel_1: DAC Channel1 selected
00449   *     @arg DAC_Channel_2: DAC Channel2 selected
00450   * @param  DAC_FLAG: specifies the flag to check. 
00451   *   This parameter can be only of the following value:
00452   *     @arg DAC_FLAG_DMAUDR: DMA underrun flag                                                 
00453   * @retval The new state of DAC_FLAG (SET or RESET).
00454   */
00455 FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
00456 {
00457   FlagStatus bitstatus = RESET;
00458   /* Check the parameters */
00459   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00460   assert_param(IS_DAC_FLAG(DAC_FLAG));
00461 
00462   /* Check the status of the specified DAC flag */
00463   if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
00464   {
00465     /* DAC_FLAG is set */
00466     bitstatus = SET;
00467   }
00468   else
00469   {
00470     /* DAC_FLAG is reset */
00471     bitstatus = RESET;
00472   }
00473   /* Return the DAC_FLAG status */
00474   return  bitstatus;
00475 }
00476 
00477 /**
00478   * @brief  Clears the DAC channelx's pending flags.
00479   * @param  DAC_Channel: the selected DAC channel. 
00480   *   This parameter can be one of the following values:
00481   *     @arg DAC_Channel_1: DAC Channel1 selected
00482   *     @arg DAC_Channel_2: DAC Channel2 selected
00483   * @param  DAC_FLAG: specifies the flag to clear. 
00484   *   This parameter can be of the following value:
00485   *     @arg DAC_FLAG_DMAUDR: DMA underrun flag                           
00486   * @retval None
00487   */
00488 void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
00489 {
00490   /* Check the parameters */
00491   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00492   assert_param(IS_DAC_FLAG(DAC_FLAG));
00493 
00494   /* Clear the selected DAC flags */
00495   DAC->SR = (DAC_FLAG << DAC_Channel);
00496 }
00497 
00498 /**
00499   * @brief  Checks whether the specified DAC interrupt has occurred or not.
00500   * @param  DAC_Channel: the selected DAC channel. 
00501   *   This parameter can be one of the following values:
00502   *     @arg DAC_Channel_1: DAC Channel1 selected
00503   *     @arg DAC_Channel_2: DAC Channel2 selected
00504   * @param  DAC_IT: specifies the DAC interrupt source to check. 
00505   *   This parameter can be the following values:
00506   *     @arg DAC_IT_DMAUDR: DMA underrun interrupt mask                       
00507   * @retval The new state of DAC_IT (SET or RESET).
00508   */
00509 ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
00510 {
00511   ITStatus bitstatus = RESET;
00512   uint32_t enablestatus = 0;
00513   
00514   /* Check the parameters */
00515   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00516   assert_param(IS_DAC_IT(DAC_IT));
00517 
00518   /* Get the DAC_IT enable bit status */
00519   enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
00520   
00521   /* Check the status of the specified DAC interrupt */
00522   if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
00523   {
00524     /* DAC_IT is set */
00525     bitstatus = SET;
00526   }
00527   else
00528   {
00529     /* DAC_IT is reset */
00530     bitstatus = RESET;
00531   }
00532   /* Return the DAC_IT status */
00533   return  bitstatus;
00534 }
00535 
00536 /**
00537   * @brief  Clears the DAC channelx’s interrupt pending bits.
00538   * @param  DAC_Channel: the selected DAC channel. 
00539   *   This parameter can be one of the following values:
00540   *     @arg DAC_Channel_1: DAC Channel1 selected
00541   *     @arg DAC_Channel_2: DAC Channel2 selected
00542   * @param  DAC_IT: specifies the DAC interrupt pending bit to clear.
00543   *   This parameter can be the following values:
00544   *     @arg DAC_IT_DMAUDR: DMA underrun interrupt mask                         
00545   * @retval None
00546   */
00547 void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
00548 {
00549   /* Check the parameters */
00550   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00551   assert_param(IS_DAC_IT(DAC_IT)); 
00552 
00553   /* Clear the selected DAC interrupt pending bits */
00554   DAC->SR = (DAC_IT << DAC_Channel);
00555 }
00556 #endif
00557 
00558 /**
00559   * @}
00560   */
00561 
00562 /**
00563   * @}
00564   */
00565 
00566 /**
00567   * @}
00568   */
00569 
00570 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
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