stm32f10x_cec.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_cec.c
00004   * @author  MCD Application Team
00005   * @version V3.4.0
00006   * @date    10/15/2010
00007   * @brief   This file provides all the CEC firmware functions.
00008   ******************************************************************************
00009   * @copy
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
00019   */ 
00020 
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32f10x_cec.h"
00023 #include "stm32f10x_rcc.h"
00024 
00025 /** @addtogroup STM32F10x_StdPeriph_Driver
00026   * @{
00027   */
00028 
00029 /** @defgroup CEC 
00030   * @brief CEC driver modules
00031   * @{
00032   */
00033 
00034 /** @defgroup CEC_Private_TypesDefinitions
00035   * @{
00036   */
00037 
00038 /**
00039   * @}
00040   */
00041 
00042 
00043 /** @defgroup CEC_Private_Defines
00044   * @{
00045   */ 
00046 
00047 /* ------------ CEC registers bit address in the alias region ----------- */
00048 #define CEC_OFFSET                (CEC_BASE - PERIPH_BASE)
00049 
00050 /* --- CFGR Register ---*/
00051 
00052 /* Alias word address of PE bit */
00053 #define CFGR_OFFSET                 (CEC_OFFSET + 0x00)
00054 #define PE_BitNumber                0x00
00055 #define CFGR_PE_BB                  (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))
00056 
00057 /* Alias word address of IE bit */
00058 #define IE_BitNumber                0x01
00059 #define CFGR_IE_BB                  (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))
00060 
00061 /* --- CSR Register ---*/
00062 
00063 /* Alias word address of TSOM bit */
00064 #define CSR_OFFSET                  (CEC_OFFSET + 0x10)
00065 #define TSOM_BitNumber              0x00
00066 #define CSR_TSOM_BB                 (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
00067 
00068 /* Alias word address of TEOM bit */
00069 #define TEOM_BitNumber              0x01
00070 #define CSR_TEOM_BB                 (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
00071   
00072 #define CFGR_CLEAR_Mask            (uint8_t)(0xF3)        /* CFGR register Mask */
00073 #define FLAG_Mask                  ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */
00074  
00075 /**
00076   * @}
00077   */ 
00078 
00079 
00080 /** @defgroup CEC_Private_Macros
00081   * @{
00082   */ 
00083 
00084 /**
00085   * @}
00086   */ 
00087 
00088 
00089 /** @defgroup CEC_Private_Variables
00090   * @{
00091   */ 
00092 
00093 /**
00094   * @}
00095   */ 
00096 
00097 
00098 /** @defgroup CEC_Private_FunctionPrototypes
00099   * @{
00100   */
00101  
00102 /**
00103   * @}
00104   */ 
00105 
00106 
00107 /** @defgroup CEC_Private_Functions
00108   * @{
00109   */ 
00110 
00111 /**
00112   * @brief  Deinitializes the CEC peripheral registers to their default reset 
00113   *         values.
00114   * @param  None
00115   * @retval None
00116   */
00117 void CEC_DeInit(void)
00118 {
00119   /* Enable CEC reset state */
00120   RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);  
00121   /* Release CEC from reset state */
00122   RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); 
00123 }
00124 
00125 
00126 /**
00127   * @brief  Initializes the CEC peripheral according to the specified 
00128   *         parameters in the CEC_InitStruct.
00129   * @param  CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
00130   *         contains the configuration information for the specified
00131   *         CEC peripheral.
00132   * @retval None
00133   */
00134 void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
00135 {
00136   uint16_t tmpreg = 0;
00137  
00138   /* Check the parameters */
00139   assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); 
00140   assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));
00141      
00142   /*---------------------------- CEC CFGR Configuration -----------------*/
00143   /* Get the CEC CFGR value */
00144   tmpreg = CEC->CFGR;
00145   
00146   /* Clear BTEM and BPEM bits */
00147   tmpreg &= CFGR_CLEAR_Mask;
00148   
00149   /* Configure CEC: Bit Timing Error and Bit Period Error */
00150   tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);
00151 
00152   /* Write to CEC CFGR  register*/
00153   CEC->CFGR = tmpreg;
00154   
00155 }
00156 
00157 /**
00158   * @brief  Enables or disables the specified CEC peripheral.
00159   * @param  NewState: new state of the CEC peripheral. 
00160   *     This parameter can be: ENABLE or DISABLE.
00161   * @retval None
00162   */
00163 void CEC_Cmd(FunctionalState NewState)
00164 {
00165   /* Check the parameters */
00166   assert_param(IS_FUNCTIONAL_STATE(NewState));
00167 
00168   *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;
00169 
00170   if(NewState == DISABLE)
00171   {
00172     /* Wait until the PE bit is cleared by hardware (Idle Line detected) */
00173     while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)
00174     {
00175     }  
00176   }  
00177 }
00178 
00179 /**
00180   * @brief  Enables or disables the CEC interrupt.
00181   * @param  NewState: new state of the CEC interrupt.
00182   *   This parameter can be: ENABLE or DISABLE.
00183   * @retval None
00184   */
00185 void CEC_ITConfig(FunctionalState NewState)
00186 {
00187   /* Check the parameters */
00188   assert_param(IS_FUNCTIONAL_STATE(NewState));
00189 
00190   *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;
00191 }
00192 
00193 /**
00194   * @brief  Defines the Own Address of the CEC device.
00195   * @param  CEC_OwnAddress: The CEC own address
00196   * @retval None
00197   */
00198 void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
00199 {
00200   /* Check the parameters */
00201   assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
00202 
00203   /* Set the CEC own address */
00204   CEC->OAR = CEC_OwnAddress;
00205 }
00206 
00207 /**
00208   * @brief  Sets the CEC prescaler value.
00209   * @param  CEC_Prescaler: CEC prescaler new value
00210   * @retval None
00211   */
00212 void CEC_SetPrescaler(uint16_t CEC_Prescaler)
00213 {
00214   /* Check the parameters */
00215   assert_param(IS_CEC_PRESCALER(CEC_Prescaler));
00216 
00217   /* Set the  Prescaler value*/
00218   CEC->PRES = CEC_Prescaler;
00219 }
00220 
00221 /**
00222   * @brief  Transmits single data through the CEC peripheral.
00223   * @param  Data: the data to transmit.
00224   * @retval None
00225   */
00226 void CEC_SendDataByte(uint8_t Data)
00227 {  
00228   /* Transmit Data */
00229   CEC->TXD = Data ;
00230 }
00231 
00232 
00233 /**
00234   * @brief  Returns the most recent received data by the CEC peripheral.
00235   * @param  None
00236   * @retval The received data.
00237   */
00238 uint8_t CEC_ReceiveDataByte(void)
00239 {
00240   /* Receive Data */
00241   return (uint8_t)(CEC->RXD);
00242 }
00243 
00244 /**
00245   * @brief  Starts a new message.
00246   * @param  None
00247   * @retval None
00248   */
00249 void CEC_StartOfMessage(void)
00250 {  
00251   /* Starts of new message */
00252   *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;
00253 }
00254 
00255 /**
00256   * @brief  Transmits message with or without an EOM bit.
00257   * @param  NewState: new state of the CEC Tx End Of Message. 
00258   *     This parameter can be: ENABLE or DISABLE.
00259   * @retval None
00260   */
00261 void CEC_EndOfMessageCmd(FunctionalState NewState)
00262 {   
00263   /* Check the parameters */
00264   assert_param(IS_FUNCTIONAL_STATE(NewState));
00265   
00266   /* The data byte will be transmitted with or without an EOM bit*/
00267   *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;
00268 }
00269 
00270 /**
00271   * @brief  Gets the CEC flag status
00272   * @param  CEC_FLAG: specifies the CEC flag to check. 
00273   *   This parameter can be one of the following values:
00274   *     @arg CEC_FLAG_BTE: Bit Timing Error
00275   *     @arg CEC_FLAG_BPE: Bit Period Error
00276   *     @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
00277   *     @arg CEC_FLAG_SBE: Start Bit Error
00278   *     @arg CEC_FLAG_ACKE: Block Acknowledge Error
00279   *     @arg CEC_FLAG_LINE: Line Error
00280   *     @arg CEC_FLAG_TBTFE: Tx Block Transfer Finsihed Error
00281   *     @arg CEC_FLAG_TEOM: Tx End Of Message 
00282   *     @arg CEC_FLAG_TERR: Tx Error
00283   *     @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
00284   *     @arg CEC_FLAG_RSOM: Rx Start Of Message
00285   *     @arg CEC_FLAG_REOM: Rx End Of Message
00286   *     @arg CEC_FLAG_RERR: Rx Error
00287   *     @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
00288   * @retval The new state of CEC_FLAG (SET or RESET)
00289   */
00290 FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) 
00291 {
00292   FlagStatus bitstatus = RESET;
00293   uint32_t cecreg = 0, cecbase = 0;
00294   
00295   /* Check the parameters */
00296   assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
00297  
00298   /* Get the CEC peripheral base address */
00299   cecbase = (uint32_t)(CEC_BASE);
00300   
00301   /* Read flag register index */
00302   cecreg = CEC_FLAG >> 28;
00303   
00304   /* Get bit[23:0] of the flag */
00305   CEC_FLAG &= FLAG_Mask;
00306   
00307   if(cecreg != 0)
00308   {
00309     /* Flag in CEC ESR Register */
00310     CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);
00311     
00312     /* Get the CEC ESR register address */
00313     cecbase += 0xC;
00314   }
00315   else
00316   {
00317     /* Get the CEC CSR register address */
00318     cecbase += 0x10;
00319   }
00320   
00321   if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)
00322   {
00323     /* CEC_FLAG is set */
00324     bitstatus = SET;
00325   }
00326   else
00327   {
00328     /* CEC_FLAG is reset */
00329     bitstatus = RESET;
00330   }
00331   
00332   /* Return the CEC_FLAG status */
00333   return  bitstatus;
00334 }
00335 
00336 /**
00337   * @brief  Clears the CEC's pending flags.
00338   * @param  CEC_FLAG: specifies the flag to clear. 
00339   *   This parameter can be any combination of the following values:
00340   *     @arg CEC_FLAG_TERR: Tx Error
00341   *     @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
00342   *     @arg CEC_FLAG_RSOM: Rx Start Of Message
00343   *     @arg CEC_FLAG_REOM: Rx End Of Message
00344   *     @arg CEC_FLAG_RERR: Rx Error
00345   *     @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
00346   * @retval None
00347   */
00348 void CEC_ClearFlag(uint32_t CEC_FLAG)
00349 { 
00350   uint32_t tmp = 0x0;
00351   
00352   /* Check the parameters */
00353   assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
00354 
00355   tmp = CEC->CSR & 0x2;
00356        
00357   /* Clear the selected CEC flags */
00358   CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);
00359 }
00360 
00361 /**
00362   * @brief  Checks whether the specified CEC interrupt has occurred or not.
00363   * @param  CEC_IT: specifies the CEC interrupt source to check. 
00364   *   This parameter can be one of the following values:
00365   *     @arg CEC_IT_TERR: Tx Error
00366   *     @arg CEC_IT_TBTF: Tx Block Transfer Finished
00367   *     @arg CEC_IT_RERR: Rx Error
00368   *     @arg CEC_IT_RBTF: Rx Block Transfer Finished
00369   * @retval The new state of CEC_IT (SET or RESET).
00370   */
00371 ITStatus CEC_GetITStatus(uint8_t CEC_IT)
00372 {
00373   ITStatus bitstatus = RESET;
00374   uint32_t enablestatus = 0;
00375   
00376   /* Check the parameters */
00377    assert_param(IS_CEC_GET_IT(CEC_IT));
00378    
00379   /* Get the CEC IT enable bit status */
00380   enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;
00381   
00382   /* Check the status of the specified CEC interrupt */
00383   if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)
00384   {
00385     /* CEC_IT is set */
00386     bitstatus = SET;
00387   }
00388   else
00389   {
00390     /* CEC_IT is reset */
00391     bitstatus = RESET;
00392   }
00393   /* Return the CEC_IT status */
00394   return  bitstatus;
00395 }
00396 
00397 /**
00398   * @brief  Clears the CEC's interrupt pending bits.
00399   * @param  CEC_IT: specifies the CEC interrupt pending bit to clear.
00400   *   This parameter can be any combination of the following values:
00401   *     @arg CEC_IT_TERR: Tx Error
00402   *     @arg CEC_IT_TBTF: Tx Block Transfer Finished
00403   *     @arg CEC_IT_RERR: Rx Error
00404   *     @arg CEC_IT_RBTF: Rx Block Transfer Finished
00405   * @retval None
00406   */
00407 void CEC_ClearITPendingBit(uint16_t CEC_IT)
00408 {
00409   uint32_t tmp = 0x0;
00410   
00411   /* Check the parameters */
00412   assert_param(IS_CEC_GET_IT(CEC_IT));
00413   
00414   tmp = CEC->CSR & 0x2;
00415   
00416   /* Clear the selected CEC interrupt pending bits */
00417   CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);
00418 }
00419 
00420 /**
00421   * @}
00422   */ 
00423 
00424 /**
00425   * @}
00426   */ 
00427 
00428 /**
00429   * @}
00430   */ 
00431 
00432 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
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