stm32f10x.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x.h
00004   * @author  MCD Application Team
00005   * @version V3.4.0
00006   * @date    10/15/2010
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
00008   *          This file contains all the peripheral register's definitions, bits 
00009   *          definitions and memory mapping for STM32F10x Connectivity line, 
00010   *          High density, High density value line, Medium density, 
00011   *          Medium density Value line, Low density, Low density Value line 
00012   *          and XL-density devices.
00013   ******************************************************************************     
00014   *
00015   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00016   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00017   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00018   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00019   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00020   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025 
00026 /** @addtogroup CMSIS
00027   * @{
00028   */
00029 
00030 /** @addtogroup stm32f10x
00031   * @{
00032   */
00033     
00034 #ifndef __STM32F10x_H
00035 #define __STM32F10x_H
00036 
00037 #ifdef __cplusplus
00038  extern "C" {
00039 #endif 
00040   
00041 /** @addtogroup Library_configuration_section
00042   * @{
00043   */
00044   
00045 /* Uncomment the line below according to the target STM32 device used in your
00046    application 
00047   */
00048 
00049 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) 
00050   /* #define STM32F10X_LD */     /*!< STM32F10X_LD: STM32 Low density devices */
00051   /* #define STM32F10X_LD_VL */  /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */  
00052   /* #define STM32F10X_MD */     /*!< STM32F10X_MD: STM32 Medium density devices */
00053   /* #define STM32F10X_MD_VL */  /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */  
00054   /* #define STM32F10X_HD */     /*!< STM32F10X_HD: STM32 High density devices */
00055   /* #define STM32F10X_HD_VL */  /*!< STM32F10X_HD_VL: STM32 High density value line devices */  
00056   /* #define STM32F10X_XL */     /*!< STM32F10X_XL: STM32 XL-density devices */
00057   /* #define STM32F10X_CL */     /*!< STM32F10X_CL: STM32 Connectivity line devices */
00058 #endif
00059 /*  Tip: To avoid modifying this file each time you need to switch between these
00060         devices, you can define the device in your toolchain compiler preprocessor.
00061 
00062  - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
00063    where the Flash memory density ranges between 16 and 32 Kbytes.
00064  - Low-density value line devices are STM32F100xx microcontrollers where the Flash
00065    memory density ranges between 16 and 32 Kbytes.
00066  - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
00067    where the Flash memory density ranges between 64 and 128 Kbytes.
00068  - Medium-density value line devices are STM32F100xx microcontrollers where the 
00069    Flash memory density ranges between 64 and 128 Kbytes.   
00070  - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
00071    the Flash memory density ranges between 256 and 512 Kbytes.
00072  - High-density value line devices are STM32F100xx microcontrollers where the 
00073    Flash memory density ranges between 256 and 512 Kbytes.   
00074  - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
00075    the Flash memory density ranges between 512 and 1024 Kbytes.
00076  - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
00077   */
00078 
00079 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
00080  #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)"
00081 #endif
00082 
00083 #if !defined  USE_STDPERIPH_DRIVER
00084 /**
00085  * @brief Comment the line below if you will not use the peripherals drivers.
00086    In this case, these drivers will not be included and the application code will 
00087    be based on direct access to peripherals registers 
00088    */
00089   /*#define USE_STDPERIPH_DRIVER*/
00090 #endif
00091 
00092 /**
00093  * @brief In the following line adjust the value of External High Speed oscillator (HSE)
00094    used in your application 
00095    
00096    Tip: To avoid modifying this file each time you need to use different HSE, you
00097         can define the HSE value in your toolchain compiler preprocessor.
00098   */           
00099 #if !defined  HSE_VALUE
00100  #ifdef STM32F10X_CL   
00101   #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
00102  #else 
00103   #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
00104  #endif /* STM32F10X_CL */
00105 #endif /* HSE_VALUE */
00106 
00107 
00108 /**
00109  * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
00110    Timeout value 
00111    */
00112 #define HSE_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSE start up */
00113 
00114 #define HSI_VALUE    ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
00115 
00116 /**
00117  * @brief STM32F10x Standard Peripheral Library version number
00118    */
00119 #define __STM32F10X_STDPERIPH_VERSION_MAIN   (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */
00120 #define __STM32F10X_STDPERIPH_VERSION_SUB1   (0x04) /*!< [15:8]  STM32F10x Standard Peripheral Library sub1 version */
00121 #define __STM32F10X_STDPERIPH_VERSION_SUB2   (0x00) /*!< [7:0]  STM32F10x Standard Peripheral Library sub2 version */
00122 #define __STM32F10X_STDPERIPH_VERSION       ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\
00123                                              | (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\
00124                                              | __STM32F10X_STDPERIPH_VERSION_SUB2)
00125 
00126 /**
00127   * @}
00128   */
00129 
00130 /** @addtogroup Configuration_section_for_CMSIS
00131   * @{
00132   */
00133 
00134 /**
00135  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
00136  */
00137 #ifdef STM32F10X_XL
00138  #define __MPU_PRESENT             1 /*!< STM32 XL-density devices provide an MPU */
00139 #else
00140  #define __MPU_PRESENT             0 /*!< Other STM32 devices does not provide an MPU */
00141 #endif /* STM32F10X_XL */
00142 #define __NVIC_PRIO_BITS          4 /*!< STM32 uses 4 Bits for the Priority Levels    */
00143 #define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used */
00144 
00145 /**
00146  * @brief STM32F10x Interrupt Number Definition, according to the selected device 
00147  *        in @ref Library_configuration_section 
00148  */
00149 typedef enum IRQn
00150 {
00151 /******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
00152   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */
00153   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt              */
00154   BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                      */
00155   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                    */
00156   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                       */
00157   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */
00158   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                       */
00159   SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                   */
00160 
00161 /******  STM32 specific Interrupt Numbers *********************************************************/
00162   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                            */
00163   PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt            */
00164   TAMPER_IRQn                 = 2,      /*!< Tamper Interrupt                                     */
00165   RTC_IRQn                    = 3,      /*!< RTC global Interrupt                                 */
00166   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                               */
00167   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                 */
00168   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                 */
00169   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                 */
00170   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                 */
00171   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                 */
00172   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                 */
00173   DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                      */
00174   DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                      */
00175   DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                      */
00176   DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                      */
00177   DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                      */
00178   DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                      */
00179   DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                      */
00180 
00181 #ifdef STM32F10X_LD
00182   ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
00183   USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
00184   USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
00185   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
00186   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
00187   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
00188   TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
00189   TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
00190   TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
00191   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
00192   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
00193   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
00194   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
00195   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
00196   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
00197   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
00198   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
00199   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
00200   RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
00201   USBWakeUp_IRQn              = 42      /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */    
00202 #endif /* STM32F10X_LD */  
00203 
00204 #ifdef STM32F10X_LD_VL
00205   ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */
00206   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
00207   TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */
00208   TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */
00209   TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */
00210   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
00211   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
00212   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
00213   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
00214   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
00215   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
00216   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
00217   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
00218   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
00219   RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
00220   CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */
00221   TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */
00222   TIM7_IRQn                   = 55      /*!< TIM7 Interrupt                                       */       
00223 #endif /* STM32F10X_LD_VL */
00224 
00225 #ifdef STM32F10X_MD
00226   ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
00227   USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
00228   USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
00229   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
00230   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
00231   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
00232   TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
00233   TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
00234   TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
00235   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
00236   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
00237   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
00238   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
00239   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
00240   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
00241   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
00242   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
00243   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
00244   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
00245   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
00246   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
00247   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
00248   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
00249   RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
00250   USBWakeUp_IRQn              = 42      /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */  
00251 #endif /* STM32F10X_MD */  
00252 
00253 #ifdef STM32F10X_MD_VL
00254   ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */
00255   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
00256   TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */
00257   TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */
00258   TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */
00259   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
00260   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
00261   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
00262   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
00263   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
00264   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
00265   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
00266   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
00267   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
00268   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
00269   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
00270   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
00271   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
00272   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
00273   RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
00274   CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */
00275   TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */
00276   TIM7_IRQn                   = 55      /*!< TIM7 Interrupt                                       */       
00277 #endif /* STM32F10X_MD_VL */
00278 
00279 #ifdef STM32F10X_HD
00280   ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
00281   USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
00282   USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
00283   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
00284   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
00285   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
00286   TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
00287   TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
00288   TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
00289   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
00290   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
00291   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
00292   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
00293   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
00294   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
00295   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
00296   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
00297   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
00298   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
00299   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
00300   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
00301   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
00302   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
00303   RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
00304   USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
00305   TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                 */
00306   TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                */
00307   TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt               */
00308   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                       */
00309   ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
00310   FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                */
00311   SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
00312   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
00313   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
00314   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
00315   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
00316   TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */
00317   TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */
00318   DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
00319   DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
00320   DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
00321   DMA2_Channel4_5_IRQn        = 59      /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
00322 #endif /* STM32F10X_HD */  
00323 
00324 #ifdef STM32F10X_HD_VL
00325   ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */
00326   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
00327   TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */
00328   TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */
00329   TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */
00330   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
00331   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
00332   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
00333   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
00334   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
00335   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
00336   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
00337   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
00338   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
00339   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
00340   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
00341   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
00342   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
00343   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
00344   RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
00345   CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */
00346   TIM12_IRQn                  = 43,     /*!< TIM12 global Interrupt                               */
00347   TIM13_IRQn                  = 44,     /*!< TIM13 global Interrupt                               */
00348   TIM14_IRQn                  = 45,     /*!< TIM14 global Interrupt                               */
00349   FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                */
00350   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
00351   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
00352   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
00353   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */  
00354   TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */
00355   TIM7_IRQn                   = 55,     /*!< TIM7 Interrupt                                       */  
00356   DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
00357   DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
00358   DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
00359   DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
00360   DMA2_Channel5_IRQn          = 60      /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is 
00361                                              mapped at postion 60 only if the MISC_REMAP bit in 
00362                                              the AFIO_MAPR2 register is set)                      */       
00363 #endif /* STM32F10X_HD_VL */
00364 
00365 #ifdef STM32F10X_XL
00366   ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
00367   USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
00368   USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
00369   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
00370   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
00371   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
00372   TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break Interrupt and TIM9 global Interrupt       */
00373   TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global Interrupt     */
00374   TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
00375   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
00376   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
00377   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
00378   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
00379   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
00380   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
00381   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
00382   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
00383   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
00384   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
00385   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
00386   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
00387   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
00388   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
00389   RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
00390   USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
00391   TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global Interrupt      */
00392   TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global Interrupt     */
00393   TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
00394   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                       */
00395   ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
00396   FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                */
00397   SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
00398   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
00399   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
00400   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
00401   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
00402   TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */
00403   TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */
00404   DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
00405   DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
00406   DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
00407   DMA2_Channel4_5_IRQn        = 59      /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
00408 #endif /* STM32F10X_XL */  
00409 
00410 #ifdef STM32F10X_CL
00411   ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
00412   CAN1_TX_IRQn                = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
00413   CAN1_RX0_IRQn               = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
00414   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
00415   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
00416   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
00417   TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
00418   TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
00419   TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
00420   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
00421   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
00422   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
00423   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
00424   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
00425   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
00426   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
00427   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
00428   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
00429   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
00430   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
00431   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
00432   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
00433   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
00434   RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
00435   OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */
00436   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
00437   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
00438   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
00439   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
00440   TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */
00441   TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */
00442   DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
00443   DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
00444   DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
00445   DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                      */
00446   DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                      */
00447   ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                            */
00448   ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt          */
00449   CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                    */
00450   CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                   */
00451   CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                   */
00452   CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                   */
00453   OTG_FS_IRQn                 = 67      /*!< USB OTG FS global Interrupt                          */
00454 #endif /* STM32F10X_CL */     
00455 } IRQn_Type;
00456 
00457 /**
00458   * @}
00459   */
00460 
00461 #include "core_cm3.h"
00462 #include "system_stm32f10x.h"
00463 #include <stdint.h>
00464 
00465 /** @addtogroup Exported_types
00466   * @{
00467   */  
00468 
00469 /*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
00470 typedef int32_t  s32;
00471 typedef int16_t s16;
00472 typedef int8_t  s8;
00473 
00474 typedef const int32_t sc32;  /*!< Read Only */
00475 typedef const int16_t sc16;  /*!< Read Only */
00476 typedef const int8_t sc8;   /*!< Read Only */
00477 
00478 typedef __IO int32_t  vs32;
00479 typedef __IO int16_t  vs16;
00480 typedef __IO int8_t   vs8;
00481 
00482 typedef __I int32_t vsc32;  /*!< Read Only */
00483 typedef __I int16_t vsc16;  /*!< Read Only */
00484 typedef __I int8_t vsc8;   /*!< Read Only */
00485 
00486 typedef uint32_t  u32;
00487 typedef uint16_t u16;
00488 typedef uint8_t  u8;
00489 
00490 typedef const uint32_t uc32;  /*!< Read Only */
00491 typedef const uint16_t uc16;  /*!< Read Only */
00492 typedef const uint8_t uc8;   /*!< Read Only */
00493 
00494 typedef __IO uint32_t  vu32;
00495 typedef __IO uint16_t vu16;
00496 typedef __IO uint8_t  vu8;
00497 
00498 typedef __I uint32_t vuc32;  /*!< Read Only */
00499 typedef __I uint16_t vuc16;  /*!< Read Only */
00500 typedef __I uint8_t vuc8;   /*!< Read Only */
00501 
00502 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
00503 
00504 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
00505 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
00506 
00507 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
00508 
00509 /*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */
00510 #define HSEStartUp_TimeOut   HSE_STARTUP_TIMEOUT
00511 #define HSE_Value            HSE_VALUE
00512 #define HSI_Value            HSI_VALUE
00513 /**
00514   * @}
00515   */
00516 
00517 /** @addtogroup Peripheral_registers_structures
00518   * @{
00519   */   
00520 
00521 /** 
00522   * @brief Analog to Digital Converter  
00523   */
00524 
00525 typedef struct
00526 {
00527   __IO uint32_t SR;
00528   __IO uint32_t CR1;
00529   __IO uint32_t CR2;
00530   __IO uint32_t SMPR1;
00531   __IO uint32_t SMPR2;
00532   __IO uint32_t JOFR1;
00533   __IO uint32_t JOFR2;
00534   __IO uint32_t JOFR3;
00535   __IO uint32_t JOFR4;
00536   __IO uint32_t HTR;
00537   __IO uint32_t LTR;
00538   __IO uint32_t SQR1;
00539   __IO uint32_t SQR2;
00540   __IO uint32_t SQR3;
00541   __IO uint32_t JSQR;
00542   __IO uint32_t JDR1;
00543   __IO uint32_t JDR2;
00544   __IO uint32_t JDR3;
00545   __IO uint32_t JDR4;
00546   __IO uint32_t DR;
00547 } ADC_TypeDef;
00548 
00549 /** 
00550   * @brief Backup Registers  
00551   */
00552 
00553 typedef struct
00554 {
00555   uint32_t  RESERVED0;
00556   __IO uint16_t DR1;
00557   uint16_t  RESERVED1;
00558   __IO uint16_t DR2;
00559   uint16_t  RESERVED2;
00560   __IO uint16_t DR3;
00561   uint16_t  RESERVED3;
00562   __IO uint16_t DR4;
00563   uint16_t  RESERVED4;
00564   __IO uint16_t DR5;
00565   uint16_t  RESERVED5;
00566   __IO uint16_t DR6;
00567   uint16_t  RESERVED6;
00568   __IO uint16_t DR7;
00569   uint16_t  RESERVED7;
00570   __IO uint16_t DR8;
00571   uint16_t  RESERVED8;
00572   __IO uint16_t DR9;
00573   uint16_t  RESERVED9;
00574   __IO uint16_t DR10;
00575   uint16_t  RESERVED10; 
00576   __IO uint16_t RTCCR;
00577   uint16_t  RESERVED11;
00578   __IO uint16_t CR;
00579   uint16_t  RESERVED12;
00580   __IO uint16_t CSR;
00581   uint16_t  RESERVED13[5];
00582   __IO uint16_t DR11;
00583   uint16_t  RESERVED14;
00584   __IO uint16_t DR12;
00585   uint16_t  RESERVED15;
00586   __IO uint16_t DR13;
00587   uint16_t  RESERVED16;
00588   __IO uint16_t DR14;
00589   uint16_t  RESERVED17;
00590   __IO uint16_t DR15;
00591   uint16_t  RESERVED18;
00592   __IO uint16_t DR16;
00593   uint16_t  RESERVED19;
00594   __IO uint16_t DR17;
00595   uint16_t  RESERVED20;
00596   __IO uint16_t DR18;
00597   uint16_t  RESERVED21;
00598   __IO uint16_t DR19;
00599   uint16_t  RESERVED22;
00600   __IO uint16_t DR20;
00601   uint16_t  RESERVED23;
00602   __IO uint16_t DR21;
00603   uint16_t  RESERVED24;
00604   __IO uint16_t DR22;
00605   uint16_t  RESERVED25;
00606   __IO uint16_t DR23;
00607   uint16_t  RESERVED26;
00608   __IO uint16_t DR24;
00609   uint16_t  RESERVED27;
00610   __IO uint16_t DR25;
00611   uint16_t  RESERVED28;
00612   __IO uint16_t DR26;
00613   uint16_t  RESERVED29;
00614   __IO uint16_t DR27;
00615   uint16_t  RESERVED30;
00616   __IO uint16_t DR28;
00617   uint16_t  RESERVED31;
00618   __IO uint16_t DR29;
00619   uint16_t  RESERVED32;
00620   __IO uint16_t DR30;
00621   uint16_t  RESERVED33; 
00622   __IO uint16_t DR31;
00623   uint16_t  RESERVED34;
00624   __IO uint16_t DR32;
00625   uint16_t  RESERVED35;
00626   __IO uint16_t DR33;
00627   uint16_t  RESERVED36;
00628   __IO uint16_t DR34;
00629   uint16_t  RESERVED37;
00630   __IO uint16_t DR35;
00631   uint16_t  RESERVED38;
00632   __IO uint16_t DR36;
00633   uint16_t  RESERVED39;
00634   __IO uint16_t DR37;
00635   uint16_t  RESERVED40;
00636   __IO uint16_t DR38;
00637   uint16_t  RESERVED41;
00638   __IO uint16_t DR39;
00639   uint16_t  RESERVED42;
00640   __IO uint16_t DR40;
00641   uint16_t  RESERVED43;
00642   __IO uint16_t DR41;
00643   uint16_t  RESERVED44;
00644   __IO uint16_t DR42;
00645   uint16_t  RESERVED45;    
00646 } BKP_TypeDef;
00647   
00648 /** 
00649   * @brief Controller Area Network TxMailBox 
00650   */
00651 
00652 typedef struct
00653 {
00654   __IO uint32_t TIR;
00655   __IO uint32_t TDTR;
00656   __IO uint32_t TDLR;
00657   __IO uint32_t TDHR;
00658 } CAN_TxMailBox_TypeDef;
00659 
00660 /** 
00661   * @brief Controller Area Network FIFOMailBox 
00662   */
00663   
00664 typedef struct
00665 {
00666   __IO uint32_t RIR;
00667   __IO uint32_t RDTR;
00668   __IO uint32_t RDLR;
00669   __IO uint32_t RDHR;
00670 } CAN_FIFOMailBox_TypeDef;
00671 
00672 /** 
00673   * @brief Controller Area Network FilterRegister 
00674   */
00675   
00676 typedef struct
00677 {
00678   __IO uint32_t FR1;
00679   __IO uint32_t FR2;
00680 } CAN_FilterRegister_TypeDef;
00681 
00682 /** 
00683   * @brief Controller Area Network 
00684   */
00685   
00686 typedef struct
00687 {
00688   __IO uint32_t MCR;
00689   __IO uint32_t MSR;
00690   __IO uint32_t TSR;
00691   __IO uint32_t RF0R;
00692   __IO uint32_t RF1R;
00693   __IO uint32_t IER;
00694   __IO uint32_t ESR;
00695   __IO uint32_t BTR;
00696   uint32_t  RESERVED0[88];
00697   CAN_TxMailBox_TypeDef sTxMailBox[3];
00698   CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
00699   uint32_t  RESERVED1[12];
00700   __IO uint32_t FMR;
00701   __IO uint32_t FM1R;
00702   uint32_t  RESERVED2;
00703   __IO uint32_t FS1R;
00704   uint32_t  RESERVED3;
00705   __IO uint32_t FFA1R;
00706   uint32_t  RESERVED4;
00707   __IO uint32_t FA1R;
00708   uint32_t  RESERVED5[8];
00709 #ifndef STM32F10X_CL
00710   CAN_FilterRegister_TypeDef sFilterRegister[14];
00711 #else
00712   CAN_FilterRegister_TypeDef sFilterRegister[28];
00713 #endif /* STM32F10X_CL */  
00714 } CAN_TypeDef;
00715 
00716 /** 
00717   * @brief Consumer Electronics Control (CEC)
00718   */
00719 typedef struct
00720 {
00721   __IO uint32_t CFGR;
00722   __IO uint32_t OAR;
00723   __IO uint32_t PRES;
00724   __IO uint32_t ESR;
00725   __IO uint32_t CSR;
00726   __IO uint32_t TXD;
00727   __IO uint32_t RXD;  
00728 } CEC_TypeDef;
00729 
00730 /** 
00731   * @brief CRC calculation unit 
00732   */
00733 
00734 typedef struct
00735 {
00736   __IO uint32_t DR;
00737   __IO uint8_t  IDR;
00738   uint8_t   RESERVED0;
00739   uint16_t  RESERVED1;
00740   __IO uint32_t CR;
00741 } CRC_TypeDef;
00742 
00743 /** 
00744   * @brief Digital to Analog Converter
00745   */
00746 
00747 typedef struct
00748 {
00749   __IO uint32_t CR;
00750   __IO uint32_t SWTRIGR;
00751   __IO uint32_t DHR12R1;
00752   __IO uint32_t DHR12L1;
00753   __IO uint32_t DHR8R1;
00754   __IO uint32_t DHR12R2;
00755   __IO uint32_t DHR12L2;
00756   __IO uint32_t DHR8R2;
00757   __IO uint32_t DHR12RD;
00758   __IO uint32_t DHR12LD;
00759   __IO uint32_t DHR8RD;
00760   __IO uint32_t DOR1;
00761   __IO uint32_t DOR2;
00762 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00763   __IO uint32_t SR;
00764 #endif
00765 } DAC_TypeDef;
00766 
00767 /** 
00768   * @brief Debug MCU
00769   */
00770 
00771 typedef struct
00772 {
00773   __IO uint32_t IDCODE;
00774   __IO uint32_t CR;     
00775 }DBGMCU_TypeDef;
00776 
00777 /** 
00778   * @brief DMA Controller
00779   */
00780 
00781 typedef struct
00782 {
00783   __IO uint32_t CCR;
00784   __IO uint32_t CNDTR;
00785   __IO uint32_t CPAR;
00786   __IO uint32_t CMAR;
00787 } DMA_Channel_TypeDef;
00788 
00789 typedef struct
00790 {
00791   __IO uint32_t ISR;
00792   __IO uint32_t IFCR;
00793 } DMA_TypeDef;
00794 
00795 /** 
00796   * @brief Ethernet MAC
00797   */
00798 
00799 typedef struct
00800 {
00801   __IO uint32_t MACCR;
00802   __IO uint32_t MACFFR;
00803   __IO uint32_t MACHTHR;
00804   __IO uint32_t MACHTLR;
00805   __IO uint32_t MACMIIAR;
00806   __IO uint32_t MACMIIDR;
00807   __IO uint32_t MACFCR;
00808   __IO uint32_t MACVLANTR;             /*    8 */
00809        uint32_t RESERVED0[2];
00810   __IO uint32_t MACRWUFFR;             /*   11 */
00811   __IO uint32_t MACPMTCSR;
00812        uint32_t RESERVED1[2];
00813   __IO uint32_t MACSR;                 /*   15 */
00814   __IO uint32_t MACIMR;
00815   __IO uint32_t MACA0HR;
00816   __IO uint32_t MACA0LR;
00817   __IO uint32_t MACA1HR;
00818   __IO uint32_t MACA1LR;
00819   __IO uint32_t MACA2HR;
00820   __IO uint32_t MACA2LR;
00821   __IO uint32_t MACA3HR;
00822   __IO uint32_t MACA3LR;               /*   24 */
00823        uint32_t RESERVED2[40];
00824   __IO uint32_t MMCCR;                 /*   65 */
00825   __IO uint32_t MMCRIR;
00826   __IO uint32_t MMCTIR;
00827   __IO uint32_t MMCRIMR;
00828   __IO uint32_t MMCTIMR;               /*   69 */
00829        uint32_t RESERVED3[14];
00830   __IO uint32_t MMCTGFSCCR;            /*   84 */
00831   __IO uint32_t MMCTGFMSCCR;
00832        uint32_t RESERVED4[5];
00833   __IO uint32_t MMCTGFCR;
00834        uint32_t RESERVED5[10];
00835   __IO uint32_t MMCRFCECR;
00836   __IO uint32_t MMCRFAECR;
00837        uint32_t RESERVED6[10];
00838   __IO uint32_t MMCRGUFCR;
00839        uint32_t RESERVED7[334];
00840   __IO uint32_t PTPTSCR;
00841   __IO uint32_t PTPSSIR;
00842   __IO uint32_t PTPTSHR;
00843   __IO uint32_t PTPTSLR;
00844   __IO uint32_t PTPTSHUR;
00845   __IO uint32_t PTPTSLUR;
00846   __IO uint32_t PTPTSAR;
00847   __IO uint32_t PTPTTHR;
00848   __IO uint32_t PTPTTLR;
00849        uint32_t RESERVED8[567];
00850   __IO uint32_t DMABMR;
00851   __IO uint32_t DMATPDR;
00852   __IO uint32_t DMARPDR;
00853   __IO uint32_t DMARDLAR;
00854   __IO uint32_t DMATDLAR;
00855   __IO uint32_t DMASR;
00856   __IO uint32_t DMAOMR;
00857   __IO uint32_t DMAIER;
00858   __IO uint32_t DMAMFBOCR;
00859        uint32_t RESERVED9[9];
00860   __IO uint32_t DMACHTDR;
00861   __IO uint32_t DMACHRDR;
00862   __IO uint32_t DMACHTBAR;
00863   __IO uint32_t DMACHRBAR;
00864 } ETH_TypeDef;
00865 
00866 /** 
00867   * @brief External Interrupt/Event Controller
00868   */
00869 
00870 typedef struct
00871 {
00872   __IO uint32_t IMR;
00873   __IO uint32_t EMR;
00874   __IO uint32_t RTSR;
00875   __IO uint32_t FTSR;
00876   __IO uint32_t SWIER;
00877   __IO uint32_t PR;
00878 } EXTI_TypeDef;
00879 
00880 /** 
00881   * @brief FLASH Registers
00882   */
00883 
00884 typedef struct
00885 {
00886   __IO uint32_t ACR;
00887   __IO uint32_t KEYR;
00888   __IO uint32_t OPTKEYR;
00889   __IO uint32_t SR;
00890   __IO uint32_t CR;
00891   __IO uint32_t AR;
00892   __IO uint32_t RESERVED;
00893   __IO uint32_t OBR;
00894   __IO uint32_t WRPR;
00895 #ifdef STM32F10X_XL
00896   uint32_t RESERVED1[8]; 
00897   __IO uint32_t KEYR2;
00898   uint32_t RESERVED2;   
00899   __IO uint32_t SR2;
00900   __IO uint32_t CR2;
00901   __IO uint32_t AR2; 
00902 #endif /* STM32F10X_XL */  
00903 } FLASH_TypeDef;
00904 
00905 /** 
00906   * @brief Option Bytes Registers
00907   */
00908   
00909 typedef struct
00910 {
00911   __IO uint16_t RDP;
00912   __IO uint16_t USER;
00913   __IO uint16_t Data0;
00914   __IO uint16_t Data1;
00915   __IO uint16_t WRP0;
00916   __IO uint16_t WRP1;
00917   __IO uint16_t WRP2;
00918   __IO uint16_t WRP3;
00919 } OB_TypeDef;
00920 
00921 /** 
00922   * @brief Flexible Static Memory Controller
00923   */
00924 
00925 typedef struct
00926 {
00927   __IO uint32_t BTCR[8];   
00928 } FSMC_Bank1_TypeDef; 
00929 
00930 /** 
00931   * @brief Flexible Static Memory Controller Bank1E
00932   */
00933   
00934 typedef struct
00935 {
00936   __IO uint32_t BWTR[7];
00937 } FSMC_Bank1E_TypeDef;
00938 
00939 /** 
00940   * @brief Flexible Static Memory Controller Bank2
00941   */
00942   
00943 typedef struct
00944 {
00945   __IO uint32_t PCR2;
00946   __IO uint32_t SR2;
00947   __IO uint32_t PMEM2;
00948   __IO uint32_t PATT2;
00949   uint32_t  RESERVED0;   
00950   __IO uint32_t ECCR2; 
00951 } FSMC_Bank2_TypeDef;  
00952 
00953 /** 
00954   * @brief Flexible Static Memory Controller Bank3
00955   */
00956   
00957 typedef struct
00958 {
00959   __IO uint32_t PCR3;
00960   __IO uint32_t SR3;
00961   __IO uint32_t PMEM3;
00962   __IO uint32_t PATT3;
00963   uint32_t  RESERVED0;   
00964   __IO uint32_t ECCR3; 
00965 } FSMC_Bank3_TypeDef; 
00966 
00967 /** 
00968   * @brief Flexible Static Memory Controller Bank4
00969   */
00970   
00971 typedef struct
00972 {
00973   __IO uint32_t PCR4;
00974   __IO uint32_t SR4;
00975   __IO uint32_t PMEM4;
00976   __IO uint32_t PATT4;
00977   __IO uint32_t PIO4; 
00978 } FSMC_Bank4_TypeDef; 
00979 
00980 /** 
00981   * @brief General Purpose I/O
00982   */
00983 
00984 typedef struct
00985 {
00986   __IO uint32_t CRL;
00987   __IO uint32_t CRH;
00988   __IO uint32_t IDR;
00989   __IO uint32_t ODR;
00990   __IO uint32_t BSRR;
00991   __IO uint32_t BRR;
00992   __IO uint32_t LCKR;
00993 } GPIO_TypeDef;
00994 
00995 /** 
00996   * @brief Alternate Function I/O
00997   */
00998 
00999 typedef struct
01000 {
01001   __IO uint32_t EVCR;
01002   __IO uint32_t MAPR;
01003   __IO uint32_t EXTICR[4];
01004   uint32_t RESERVED0;
01005   __IO uint32_t MAPR2;  
01006 } AFIO_TypeDef;
01007 /** 
01008   * @brief Inter-integrated Circuit Interface
01009   */
01010 
01011 typedef struct
01012 {
01013   __IO uint16_t CR1;
01014   uint16_t  RESERVED0;
01015   __IO uint16_t CR2;
01016   uint16_t  RESERVED1;
01017   __IO uint16_t OAR1;
01018   uint16_t  RESERVED2;
01019   __IO uint16_t OAR2;
01020   uint16_t  RESERVED3;
01021   __IO uint16_t DR;
01022   uint16_t  RESERVED4;
01023   __IO uint16_t SR1;
01024   uint16_t  RESERVED5;
01025   __IO uint16_t SR2;
01026   uint16_t  RESERVED6;
01027   __IO uint16_t CCR;
01028   uint16_t  RESERVED7;
01029   __IO uint16_t TRISE;
01030   uint16_t  RESERVED8;
01031 } I2C_TypeDef;
01032 
01033 /** 
01034   * @brief Independent WATCHDOG
01035   */
01036 
01037 typedef struct
01038 {
01039   __IO uint32_t KR;
01040   __IO uint32_t PR;
01041   __IO uint32_t RLR;
01042   __IO uint32_t SR;
01043 } IWDG_TypeDef;
01044 
01045 /** 
01046   * @brief Power Control
01047   */
01048 
01049 typedef struct
01050 {
01051   __IO uint32_t CR;
01052   __IO uint32_t CSR;
01053 } PWR_TypeDef;
01054 
01055 /** 
01056   * @brief Reset and Clock Control
01057   */
01058 
01059 typedef struct
01060 {
01061   __IO uint32_t CR;
01062   __IO uint32_t CFGR;
01063   __IO uint32_t CIR;
01064   __IO uint32_t APB2RSTR;
01065   __IO uint32_t APB1RSTR;
01066   __IO uint32_t AHBENR;
01067   __IO uint32_t APB2ENR;
01068   __IO uint32_t APB1ENR;
01069   __IO uint32_t BDCR;
01070   __IO uint32_t CSR;
01071 
01072 #ifdef STM32F10X_CL  
01073   __IO uint32_t AHBRSTR;
01074   __IO uint32_t CFGR2;
01075 #endif /* STM32F10X_CL */ 
01076 
01077 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)   
01078   uint32_t RESERVED0;
01079   __IO uint32_t CFGR2;
01080 #endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ 
01081 } RCC_TypeDef;
01082 
01083 /** 
01084   * @brief Real-Time Clock
01085   */
01086 
01087 typedef struct
01088 {
01089   __IO uint16_t CRH;
01090   uint16_t  RESERVED0;
01091   __IO uint16_t CRL;
01092   uint16_t  RESERVED1;
01093   __IO uint16_t PRLH;
01094   uint16_t  RESERVED2;
01095   __IO uint16_t PRLL;
01096   uint16_t  RESERVED3;
01097   __IO uint16_t DIVH;
01098   uint16_t  RESERVED4;
01099   __IO uint16_t DIVL;
01100   uint16_t  RESERVED5;
01101   __IO uint16_t CNTH;
01102   uint16_t  RESERVED6;
01103   __IO uint16_t CNTL;
01104   uint16_t  RESERVED7;
01105   __IO uint16_t ALRH;
01106   uint16_t  RESERVED8;
01107   __IO uint16_t ALRL;
01108   uint16_t  RESERVED9;
01109 } RTC_TypeDef;
01110 
01111 /** 
01112   * @brief SD host Interface
01113   */
01114 
01115 typedef struct
01116 {
01117   __IO uint32_t POWER;
01118   __IO uint32_t CLKCR;
01119   __IO uint32_t ARG;
01120   __IO uint32_t CMD;
01121   __I uint32_t RESPCMD;
01122   __I uint32_t RESP1;
01123   __I uint32_t RESP2;
01124   __I uint32_t RESP3;
01125   __I uint32_t RESP4;
01126   __IO uint32_t DTIMER;
01127   __IO uint32_t DLEN;
01128   __IO uint32_t DCTRL;
01129   __I uint32_t DCOUNT;
01130   __I uint32_t STA;
01131   __IO uint32_t ICR;
01132   __IO uint32_t MASK;
01133   uint32_t  RESERVED0[2];
01134   __I uint32_t FIFOCNT;
01135   uint32_t  RESERVED1[13];
01136   __IO uint32_t FIFO;
01137 } SDIO_TypeDef;
01138 
01139 /** 
01140   * @brief Serial Peripheral Interface
01141   */
01142 
01143 typedef struct
01144 {
01145   __IO uint16_t CR1;
01146   uint16_t  RESERVED0;
01147   __IO uint16_t CR2;
01148   uint16_t  RESERVED1;
01149   __IO uint16_t SR;
01150   uint16_t  RESERVED2;
01151   __IO uint16_t DR;
01152   uint16_t  RESERVED3;
01153   __IO uint16_t CRCPR;
01154   uint16_t  RESERVED4;
01155   __IO uint16_t RXCRCR;
01156   uint16_t  RESERVED5;
01157   __IO uint16_t TXCRCR;
01158   uint16_t  RESERVED6;
01159   __IO uint16_t I2SCFGR;
01160   uint16_t  RESERVED7;
01161   __IO uint16_t I2SPR;
01162   uint16_t  RESERVED8;  
01163 } SPI_TypeDef;
01164 
01165 /** 
01166   * @brief TIM
01167   */
01168 
01169 typedef struct
01170 {
01171   __IO uint16_t CR1;
01172   uint16_t  RESERVED0;
01173   __IO uint16_t CR2;
01174   uint16_t  RESERVED1;
01175   __IO uint16_t SMCR;
01176   uint16_t  RESERVED2;
01177   __IO uint16_t DIER;
01178   uint16_t  RESERVED3;
01179   __IO uint16_t SR;
01180   uint16_t  RESERVED4;
01181   __IO uint16_t EGR;
01182   uint16_t  RESERVED5;
01183   __IO uint16_t CCMR1;
01184   uint16_t  RESERVED6;
01185   __IO uint16_t CCMR2;
01186   uint16_t  RESERVED7;
01187   __IO uint16_t CCER;
01188   uint16_t  RESERVED8;
01189   __IO uint16_t CNT;
01190   uint16_t  RESERVED9;
01191   __IO uint16_t PSC;
01192   uint16_t  RESERVED10;
01193   __IO uint16_t ARR;
01194   uint16_t  RESERVED11;
01195   __IO uint16_t RCR;
01196   uint16_t  RESERVED12;
01197   __IO uint16_t CCR1;
01198   uint16_t  RESERVED13;
01199   __IO uint16_t CCR2;
01200   uint16_t  RESERVED14;
01201   __IO uint16_t CCR3;
01202   uint16_t  RESERVED15;
01203   __IO uint16_t CCR4;
01204   uint16_t  RESERVED16;
01205   __IO uint16_t BDTR;
01206   uint16_t  RESERVED17;
01207   __IO uint16_t DCR;
01208   uint16_t  RESERVED18;
01209   __IO uint16_t DMAR;
01210   uint16_t  RESERVED19;
01211 } TIM_TypeDef;
01212 
01213 /** 
01214   * @brief Universal Synchronous Asynchronous Receiver Transmitter
01215   */
01216  
01217 typedef struct
01218 {
01219   __IO uint16_t SR;
01220   uint16_t  RESERVED0;
01221   __IO uint16_t DR;
01222   uint16_t  RESERVED1;
01223   __IO uint16_t BRR;
01224   uint16_t  RESERVED2;
01225   __IO uint16_t CR1;
01226   uint16_t  RESERVED3;
01227   __IO uint16_t CR2;
01228   uint16_t  RESERVED4;
01229   __IO uint16_t CR3;
01230   uint16_t  RESERVED5;
01231   __IO uint16_t GTPR;
01232   uint16_t  RESERVED6;
01233 } USART_TypeDef;
01234 
01235 /** 
01236   * @brief Window WATCHDOG
01237   */
01238 
01239 typedef struct
01240 {
01241   __IO uint32_t CR;
01242   __IO uint32_t CFR;
01243   __IO uint32_t SR;
01244 } WWDG_TypeDef;
01245 
01246 /**
01247   * @}
01248   */
01249   
01250 /** @addtogroup Peripheral_memory_map
01251   * @{
01252   */
01253 
01254 
01255 #define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
01256 #define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
01257 #define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
01258 
01259 #define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
01260 #define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
01261 
01262 #define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address */
01263 
01264 /*!< Peripheral memory map */
01265 #define APB1PERIPH_BASE       PERIPH_BASE
01266 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
01267 #define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)
01268 
01269 #define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
01270 #define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
01271 #define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
01272 #define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
01273 #define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
01274 #define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
01275 #define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
01276 #define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
01277 #define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
01278 #define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
01279 #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
01280 #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
01281 #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
01282 #define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
01283 #define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
01284 #define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
01285 #define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
01286 #define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
01287 #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
01288 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
01289 #define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
01290 #define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
01291 #define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)
01292 #define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
01293 #define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
01294 #define CEC_BASE              (APB1PERIPH_BASE + 0x7800)
01295 
01296 #define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)
01297 #define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
01298 #define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)
01299 #define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)
01300 #define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)
01301 #define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)
01302 #define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)
01303 #define GPIOF_BASE            (APB2PERIPH_BASE + 0x1C00)
01304 #define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000)
01305 #define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
01306 #define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)
01307 #define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)
01308 #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
01309 #define TIM8_BASE             (APB2PERIPH_BASE + 0x3400)
01310 #define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
01311 #define ADC3_BASE             (APB2PERIPH_BASE + 0x3C00)
01312 #define TIM15_BASE            (APB2PERIPH_BASE + 0x4000)
01313 #define TIM16_BASE            (APB2PERIPH_BASE + 0x4400)
01314 #define TIM17_BASE            (APB2PERIPH_BASE + 0x4800)
01315 #define TIM9_BASE             (APB2PERIPH_BASE + 0x4C00)
01316 #define TIM10_BASE            (APB2PERIPH_BASE + 0x5000)
01317 #define TIM11_BASE            (APB2PERIPH_BASE + 0x5400)
01318 
01319 #define SDIO_BASE             (PERIPH_BASE + 0x18000)
01320 
01321 #define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)
01322 #define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)
01323 #define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)
01324 #define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)
01325 #define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)
01326 #define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)
01327 #define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)
01328 #define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)
01329 #define DMA2_BASE             (AHBPERIPH_BASE + 0x0400)
01330 #define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x0408)
01331 #define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x041C)
01332 #define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x0430)
01333 #define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x0444)
01334 #define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x0458)
01335 #define RCC_BASE              (AHBPERIPH_BASE + 0x1000)
01336 #define CRC_BASE              (AHBPERIPH_BASE + 0x3000)
01337 
01338 #define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
01339 #define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */
01340 
01341 #define ETH_BASE              (AHBPERIPH_BASE + 0x8000)
01342 #define ETH_MAC_BASE          (ETH_BASE)
01343 #define ETH_MMC_BASE          (ETH_BASE + 0x0100)
01344 #define ETH_PTP_BASE          (ETH_BASE + 0x0700)
01345 #define ETH_DMA_BASE          (ETH_BASE + 0x1000)
01346 
01347 #define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
01348 #define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
01349 #define FSMC_Bank2_R_BASE     (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */
01350 #define FSMC_Bank3_R_BASE     (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */
01351 #define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
01352 
01353 #define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
01354 
01355 /**
01356   * @}
01357   */
01358   
01359 /** @addtogroup Peripheral_declaration
01360   * @{
01361   */  
01362 
01363 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
01364 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
01365 #define TIM4                ((TIM_TypeDef *) TIM4_BASE)
01366 #define TIM5                ((TIM_TypeDef *) TIM5_BASE)
01367 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
01368 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
01369 #define TIM12               ((TIM_TypeDef *) TIM12_BASE)
01370 #define TIM13               ((TIM_TypeDef *) TIM13_BASE)
01371 #define TIM14               ((TIM_TypeDef *) TIM14_BASE)
01372 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
01373 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
01374 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
01375 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
01376 #define SPI3                ((SPI_TypeDef *) SPI3_BASE)
01377 #define USART2              ((USART_TypeDef *) USART2_BASE)
01378 #define USART3              ((USART_TypeDef *) USART3_BASE)
01379 #define UART4               ((USART_TypeDef *) UART4_BASE)
01380 #define UART5               ((USART_TypeDef *) UART5_BASE)
01381 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
01382 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
01383 #define CAN1                ((CAN_TypeDef *) CAN1_BASE)
01384 #define CAN2                ((CAN_TypeDef *) CAN2_BASE)
01385 #define BKP                 ((BKP_TypeDef *) BKP_BASE)
01386 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
01387 #define DAC                 ((DAC_TypeDef *) DAC_BASE)
01388 #define CEC                 ((CEC_TypeDef *) CEC_BASE)
01389 #define AFIO                ((AFIO_TypeDef *) AFIO_BASE)
01390 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
01391 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
01392 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
01393 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
01394 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
01395 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
01396 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
01397 #define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
01398 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
01399 #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
01400 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
01401 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
01402 #define TIM8                ((TIM_TypeDef *) TIM8_BASE)
01403 #define USART1              ((USART_TypeDef *) USART1_BASE)
01404 #define ADC3                ((ADC_TypeDef *) ADC3_BASE)
01405 #define TIM15               ((TIM_TypeDef *) TIM15_BASE)
01406 #define TIM16               ((TIM_TypeDef *) TIM16_BASE)
01407 #define TIM17               ((TIM_TypeDef *) TIM17_BASE)
01408 #define TIM9                ((TIM_TypeDef *) TIM9_BASE)
01409 #define TIM10               ((TIM_TypeDef *) TIM10_BASE)
01410 #define TIM11               ((TIM_TypeDef *) TIM11_BASE)
01411 #define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
01412 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
01413 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
01414 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
01415 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
01416 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
01417 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
01418 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
01419 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
01420 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
01421 #define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
01422 #define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
01423 #define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
01424 #define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
01425 #define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
01426 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
01427 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
01428 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
01429 #define OB                  ((OB_TypeDef *) OB_BASE) 
01430 #define ETH                 ((ETH_TypeDef *) ETH_BASE)
01431 #define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
01432 #define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
01433 #define FSMC_Bank2          ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
01434 #define FSMC_Bank3          ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
01435 #define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
01436 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
01437 
01438 /**
01439   * @}
01440   */
01441 
01442 /** @addtogroup Exported_constants
01443   * @{
01444   */
01445   
01446   /** @addtogroup Peripheral_Registers_Bits_Definition
01447   * @{
01448   */
01449     
01450 /******************************************************************************/
01451 /*                         Peripheral Registers_Bits_Definition               */
01452 /******************************************************************************/
01453 
01454 /******************************************************************************/
01455 /*                                                                            */
01456 /*                          CRC calculation unit                              */
01457 /*                                                                            */
01458 /******************************************************************************/
01459 
01460 /*******************  Bit definition for CRC_DR register  *********************/
01461 #define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
01462 
01463 
01464 /*******************  Bit definition for CRC_IDR register  ********************/
01465 #define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
01466 
01467 
01468 /********************  Bit definition for CRC_CR register  ********************/
01469 #define  CRC_CR_RESET                        ((uint8_t)0x01)        /*!< RESET bit */
01470 
01471 /******************************************************************************/
01472 /*                                                                            */
01473 /*                             Power Control                                  */
01474 /*                                                                            */
01475 /******************************************************************************/
01476 
01477 /********************  Bit definition for PWR_CR register  ********************/
01478 #define  PWR_CR_LPDS                         ((uint16_t)0x0001)     /*!< Low-Power Deepsleep */
01479 #define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
01480 #define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
01481 #define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
01482 #define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
01483 
01484 #define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
01485 #define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
01486 #define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
01487 #define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
01488 
01489 /*!< PVD level configuration */
01490 #define  PWR_CR_PLS_2V2                      ((uint16_t)0x0000)     /*!< PVD level 2.2V */
01491 #define  PWR_CR_PLS_2V3                      ((uint16_t)0x0020)     /*!< PVD level 2.3V */
01492 #define  PWR_CR_PLS_2V4                      ((uint16_t)0x0040)     /*!< PVD level 2.4V */
01493 #define  PWR_CR_PLS_2V5                      ((uint16_t)0x0060)     /*!< PVD level 2.5V */
01494 #define  PWR_CR_PLS_2V6                      ((uint16_t)0x0080)     /*!< PVD level 2.6V */
01495 #define  PWR_CR_PLS_2V7                      ((uint16_t)0x00A0)     /*!< PVD level 2.7V */
01496 #define  PWR_CR_PLS_2V8                      ((uint16_t)0x00C0)     /*!< PVD level 2.8V */
01497 #define  PWR_CR_PLS_2V9                      ((uint16_t)0x00E0)     /*!< PVD level 2.9V */
01498 
01499 #define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
01500 
01501 
01502 /*******************  Bit definition for PWR_CSR register  ********************/
01503 #define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
01504 #define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
01505 #define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
01506 #define  PWR_CSR_EWUP                        ((uint16_t)0x0100)     /*!< Enable WKUP pin */
01507 
01508 /******************************************************************************/
01509 /*                                                                            */
01510 /*                            Backup registers                                */
01511 /*                                                                            */
01512 /******************************************************************************/
01513 
01514 /*******************  Bit definition for BKP_DR1 register  ********************/
01515 #define  BKP_DR1_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
01516 
01517 /*******************  Bit definition for BKP_DR2 register  ********************/
01518 #define  BKP_DR2_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
01519 
01520 /*******************  Bit definition for BKP_DR3 register  ********************/
01521 #define  BKP_DR3_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
01522 
01523 /*******************  Bit definition for BKP_DR4 register  ********************/
01524 #define  BKP_DR4_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
01525 
01526 /*******************  Bit definition for BKP_DR5 register  ********************/
01527 #define  BKP_DR5_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
01528 
01529 /*******************  Bit definition for BKP_DR6 register  ********************/
01530 #define  BKP_DR6_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
01531 
01532 /*******************  Bit definition for BKP_DR7 register  ********************/
01533 #define  BKP_DR7_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
01534 
01535 /*******************  Bit definition for BKP_DR8 register  ********************/
01536 #define  BKP_DR8_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
01537 
01538 /*******************  Bit definition for BKP_DR9 register  ********************/
01539 #define  BKP_DR9_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
01540 
01541 /*******************  Bit definition for BKP_DR10 register  *******************/
01542 #define  BKP_DR10_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01543 
01544 /*******************  Bit definition for BKP_DR11 register  *******************/
01545 #define  BKP_DR11_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01546 
01547 /*******************  Bit definition for BKP_DR12 register  *******************/
01548 #define  BKP_DR12_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01549 
01550 /*******************  Bit definition for BKP_DR13 register  *******************/
01551 #define  BKP_DR13_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01552 
01553 /*******************  Bit definition for BKP_DR14 register  *******************/
01554 #define  BKP_DR14_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01555 
01556 /*******************  Bit definition for BKP_DR15 register  *******************/
01557 #define  BKP_DR15_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01558 
01559 /*******************  Bit definition for BKP_DR16 register  *******************/
01560 #define  BKP_DR16_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01561 
01562 /*******************  Bit definition for BKP_DR17 register  *******************/
01563 #define  BKP_DR17_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01564 
01565 /******************  Bit definition for BKP_DR18 register  ********************/
01566 #define  BKP_DR18_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01567 
01568 /*******************  Bit definition for BKP_DR19 register  *******************/
01569 #define  BKP_DR19_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01570 
01571 /*******************  Bit definition for BKP_DR20 register  *******************/
01572 #define  BKP_DR20_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01573 
01574 /*******************  Bit definition for BKP_DR21 register  *******************/
01575 #define  BKP_DR21_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01576 
01577 /*******************  Bit definition for BKP_DR22 register  *******************/
01578 #define  BKP_DR22_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01579 
01580 /*******************  Bit definition for BKP_DR23 register  *******************/
01581 #define  BKP_DR23_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01582 
01583 /*******************  Bit definition for BKP_DR24 register  *******************/
01584 #define  BKP_DR24_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01585 
01586 /*******************  Bit definition for BKP_DR25 register  *******************/
01587 #define  BKP_DR25_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01588 
01589 /*******************  Bit definition for BKP_DR26 register  *******************/
01590 #define  BKP_DR26_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01591 
01592 /*******************  Bit definition for BKP_DR27 register  *******************/
01593 #define  BKP_DR27_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01594 
01595 /*******************  Bit definition for BKP_DR28 register  *******************/
01596 #define  BKP_DR28_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01597 
01598 /*******************  Bit definition for BKP_DR29 register  *******************/
01599 #define  BKP_DR29_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01600 
01601 /*******************  Bit definition for BKP_DR30 register  *******************/
01602 #define  BKP_DR30_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01603 
01604 /*******************  Bit definition for BKP_DR31 register  *******************/
01605 #define  BKP_DR31_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01606 
01607 /*******************  Bit definition for BKP_DR32 register  *******************/
01608 #define  BKP_DR32_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01609 
01610 /*******************  Bit definition for BKP_DR33 register  *******************/
01611 #define  BKP_DR33_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01612 
01613 /*******************  Bit definition for BKP_DR34 register  *******************/
01614 #define  BKP_DR34_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01615 
01616 /*******************  Bit definition for BKP_DR35 register  *******************/
01617 #define  BKP_DR35_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01618 
01619 /*******************  Bit definition for BKP_DR36 register  *******************/
01620 #define  BKP_DR36_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01621 
01622 /*******************  Bit definition for BKP_DR37 register  *******************/
01623 #define  BKP_DR37_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01624 
01625 /*******************  Bit definition for BKP_DR38 register  *******************/
01626 #define  BKP_DR38_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01627 
01628 /*******************  Bit definition for BKP_DR39 register  *******************/
01629 #define  BKP_DR39_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01630 
01631 /*******************  Bit definition for BKP_DR40 register  *******************/
01632 #define  BKP_DR40_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01633 
01634 /*******************  Bit definition for BKP_DR41 register  *******************/
01635 #define  BKP_DR41_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01636 
01637 /*******************  Bit definition for BKP_DR42 register  *******************/
01638 #define  BKP_DR42_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01639 
01640 /******************  Bit definition for BKP_RTCCR register  *******************/
01641 #define  BKP_RTCCR_CAL                       ((uint16_t)0x007F)     /*!< Calibration value */
01642 #define  BKP_RTCCR_CCO                       ((uint16_t)0x0080)     /*!< Calibration Clock Output */
01643 #define  BKP_RTCCR_ASOE                      ((uint16_t)0x0100)     /*!< Alarm or Second Output Enable */
01644 #define  BKP_RTCCR_ASOS                      ((uint16_t)0x0200)     /*!< Alarm or Second Output Selection */
01645 
01646 /********************  Bit definition for BKP_CR register  ********************/
01647 #define  BKP_CR_TPE                          ((uint8_t)0x01)        /*!< TAMPER pin enable */
01648 #define  BKP_CR_TPAL                         ((uint8_t)0x02)        /*!< TAMPER pin active level */
01649 
01650 /*******************  Bit definition for BKP_CSR register  ********************/
01651 #define  BKP_CSR_CTE                         ((uint16_t)0x0001)     /*!< Clear Tamper event */
01652 #define  BKP_CSR_CTI                         ((uint16_t)0x0002)     /*!< Clear Tamper Interrupt */
01653 #define  BKP_CSR_TPIE                        ((uint16_t)0x0004)     /*!< TAMPER Pin interrupt enable */
01654 #define  BKP_CSR_TEF                         ((uint16_t)0x0100)     /*!< Tamper Event Flag */
01655 #define  BKP_CSR_TIF                         ((uint16_t)0x0200)     /*!< Tamper Interrupt Flag */
01656 
01657 /******************************************************************************/
01658 /*                                                                            */
01659 /*                         Reset and Clock Control                            */
01660 /*                                                                            */
01661 /******************************************************************************/
01662 
01663 /********************  Bit definition for RCC_CR register  ********************/
01664 #define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
01665 #define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
01666 #define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)        /*!< Internal High Speed clock trimming */
01667 #define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)        /*!< Internal High Speed clock Calibration */
01668 #define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
01669 #define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
01670 #define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
01671 #define  RCC_CR_CSSON                        ((uint32_t)0x00080000)        /*!< Clock Security System enable */
01672 #define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
01673 #define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
01674 
01675 #ifdef STM32F10X_CL
01676  #define  RCC_CR_PLL2ON                       ((uint32_t)0x04000000)        /*!< PLL2 enable */
01677  #define  RCC_CR_PLL2RDY                      ((uint32_t)0x08000000)        /*!< PLL2 clock ready flag */
01678  #define  RCC_CR_PLL3ON                       ((uint32_t)0x10000000)        /*!< PLL3 enable */
01679  #define  RCC_CR_PLL3RDY                      ((uint32_t)0x20000000)        /*!< PLL3 clock ready flag */
01680 #endif /* STM32F10X_CL */
01681 
01682 /*******************  Bit definition for RCC_CFGR register  *******************/
01683 /*!< SW configuration */
01684 #define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
01685 #define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
01686 #define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
01687 
01688 #define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
01689 #define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
01690 #define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
01691 
01692 /*!< SWS configuration */
01693 #define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
01694 #define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
01695 #define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
01696 
01697 #define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
01698 #define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
01699 #define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
01700 
01701 /*!< HPRE configuration */
01702 #define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
01703 #define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
01704 #define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
01705 #define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
01706 #define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
01707 
01708 #define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
01709 #define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
01710 #define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
01711 #define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
01712 #define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
01713 #define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
01714 #define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
01715 #define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
01716 #define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
01717 
01718 /*!< PPRE1 configuration */
01719 #define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */
01720 #define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
01721 #define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
01722 #define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */
01723 
01724 #define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
01725 #define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
01726 #define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
01727 #define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
01728 #define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
01729 
01730 /*!< PPRE2 configuration */
01731 #define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */
01732 #define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
01733 #define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
01734 #define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */
01735 
01736 #define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
01737 #define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */
01738 #define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */
01739 #define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */
01740 #define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */
01741 
01742 /*!< ADCPPRE configuration */
01743 #define  RCC_CFGR_ADCPRE                     ((uint32_t)0x0000C000)        /*!< ADCPRE[1:0] bits (ADC prescaler) */
01744 #define  RCC_CFGR_ADCPRE_0                   ((uint32_t)0x00004000)        /*!< Bit 0 */
01745 #define  RCC_CFGR_ADCPRE_1                   ((uint32_t)0x00008000)        /*!< Bit 1 */
01746 
01747 #define  RCC_CFGR_ADCPRE_DIV2                ((uint32_t)0x00000000)        /*!< PCLK2 divided by 2 */
01748 #define  RCC_CFGR_ADCPRE_DIV4                ((uint32_t)0x00004000)        /*!< PCLK2 divided by 4 */
01749 #define  RCC_CFGR_ADCPRE_DIV6                ((uint32_t)0x00008000)        /*!< PCLK2 divided by 6 */
01750 #define  RCC_CFGR_ADCPRE_DIV8                ((uint32_t)0x0000C000)        /*!< PCLK2 divided by 8 */
01751 
01752 #define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
01753 
01754 #define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
01755 
01756 /*!< PLLMUL configuration */
01757 #define  RCC_CFGR_PLLMULL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
01758 #define  RCC_CFGR_PLLMULL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
01759 #define  RCC_CFGR_PLLMULL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
01760 #define  RCC_CFGR_PLLMULL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
01761 #define  RCC_CFGR_PLLMULL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
01762 
01763 #ifdef STM32F10X_CL
01764  #define  RCC_CFGR_PLLSRC_HSI_Div2           ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
01765  #define  RCC_CFGR_PLLSRC_PREDIV1            ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */
01766 
01767  #define  RCC_CFGR_PLLXTPRE_PREDIV1          ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
01768  #define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2     ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
01769 
01770  #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock * 4 */
01771  #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock * 5 */
01772  #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock * 6 */
01773  #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock * 7 */
01774  #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock * 8 */
01775  #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock * 9 */
01776  #define  RCC_CFGR_PLLMULL6_5                ((uint32_t)0x00340000)        /*!< PLL input clock * 6.5 */
01777  
01778  #define  RCC_CFGR_OTGFSPRE                  ((uint32_t)0x00400000)        /*!< USB OTG FS prescaler */
01779  
01780 /*!< MCO configuration */
01781  #define  RCC_CFGR_MCO                       ((uint32_t)0x0F000000)        /*!< MCO[3:0] bits (Microcontroller Clock Output) */
01782  #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */
01783  #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */
01784  #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */
01785  #define  RCC_CFGR_MCO_3                     ((uint32_t)0x08000000)        /*!< Bit 3 */
01786 
01787  #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */
01788  #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
01789  #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
01790  #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source */
01791  #define  RCC_CFGR_MCO_PLLCLK_Div2           ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
01792  #define  RCC_CFGR_MCO_PLL2CLK               ((uint32_t)0x08000000)        /*!< PLL2 clock selected as MCO source*/
01793  #define  RCC_CFGR_MCO_PLL3CLK_Div2          ((uint32_t)0x09000000)        /*!< PLL3 clock divided by 2 selected as MCO source*/
01794  #define  RCC_CFGR_MCO_Ext_HSE               ((uint32_t)0x0A000000)        /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
01795  #define  RCC_CFGR_MCO_PLL3CLK               ((uint32_t)0x0B000000)        /*!< PLL3 clock selected as MCO source */
01796 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
01797  #define  RCC_CFGR_PLLSRC_HSI_Div2           ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
01798  #define  RCC_CFGR_PLLSRC_PREDIV1            ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */
01799 
01800  #define  RCC_CFGR_PLLXTPRE_PREDIV1          ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
01801  #define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2     ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
01802 
01803  #define  RCC_CFGR_PLLMULL2                  ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
01804  #define  RCC_CFGR_PLLMULL3                  ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
01805  #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
01806  #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
01807  #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
01808  #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
01809  #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
01810  #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
01811  #define  RCC_CFGR_PLLMULL10                 ((uint32_t)0x00200000)        /*!< PLL input clock10 */
01812  #define  RCC_CFGR_PLLMULL11                 ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
01813  #define  RCC_CFGR_PLLMULL12                 ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
01814  #define  RCC_CFGR_PLLMULL13                 ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
01815  #define  RCC_CFGR_PLLMULL14                 ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
01816  #define  RCC_CFGR_PLLMULL15                 ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
01817  #define  RCC_CFGR_PLLMULL16                 ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
01818 
01819 /*!< MCO configuration */
01820  #define  RCC_CFGR_MCO                       ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
01821  #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */
01822  #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */
01823  #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */
01824 
01825  #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */
01826  #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
01827  #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
01828  #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
01829  #define  RCC_CFGR_MCO_PLL                   ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
01830 #else
01831  #define  RCC_CFGR_PLLSRC_HSI_Div2           ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
01832  #define  RCC_CFGR_PLLSRC_HSE                ((uint32_t)0x00010000)        /*!< HSE clock selected as PLL entry clock source */
01833 
01834  #define  RCC_CFGR_PLLXTPRE_HSE              ((uint32_t)0x00000000)        /*!< HSE clock not divided for PLL entry */
01835  #define  RCC_CFGR_PLLXTPRE_HSE_Div2         ((uint32_t)0x00020000)        /*!< HSE clock divided by 2 for PLL entry */
01836 
01837  #define  RCC_CFGR_PLLMULL2                  ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
01838  #define  RCC_CFGR_PLLMULL3                  ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
01839  #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
01840  #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
01841  #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
01842  #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
01843  #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
01844  #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
01845  #define  RCC_CFGR_PLLMULL10                 ((uint32_t)0x00200000)        /*!< PLL input clock10 */
01846  #define  RCC_CFGR_PLLMULL11                 ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
01847  #define  RCC_CFGR_PLLMULL12                 ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
01848  #define  RCC_CFGR_PLLMULL13                 ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
01849  #define  RCC_CFGR_PLLMULL14                 ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
01850  #define  RCC_CFGR_PLLMULL15                 ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
01851  #define  RCC_CFGR_PLLMULL16                 ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
01852  #define  RCC_CFGR_USBPRE                    ((uint32_t)0x00400000)        /*!< USB Device prescaler */
01853 
01854 /*!< MCO configuration */
01855  #define  RCC_CFGR_MCO                       ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
01856  #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */
01857  #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */
01858  #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */
01859 
01860  #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */
01861  #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
01862  #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
01863  #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
01864  #define  RCC_CFGR_MCO_PLL                   ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
01865 #endif /* STM32F10X_CL */
01866 
01867 /*!<******************  Bit definition for RCC_CIR register  ********************/
01868 #define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
01869 #define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
01870 #define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
01871 #define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
01872 #define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
01873 #define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
01874 #define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
01875 #define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
01876 #define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
01877 #define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
01878 #define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
01879 #define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
01880 #define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
01881 #define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
01882 #define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
01883 #define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
01884 #define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
01885 
01886 #ifdef STM32F10X_CL
01887  #define  RCC_CIR_PLL2RDYF                    ((uint32_t)0x00000020)        /*!< PLL2 Ready Interrupt flag */
01888  #define  RCC_CIR_PLL3RDYF                    ((uint32_t)0x00000040)        /*!< PLL3 Ready Interrupt flag */
01889  #define  RCC_CIR_PLL2RDYIE                   ((uint32_t)0x00002000)        /*!< PLL2 Ready Interrupt Enable */
01890  #define  RCC_CIR_PLL3RDYIE                   ((uint32_t)0x00004000)        /*!< PLL3 Ready Interrupt Enable */
01891  #define  RCC_CIR_PLL2RDYC                    ((uint32_t)0x00200000)        /*!< PLL2 Ready Interrupt Clear */
01892  #define  RCC_CIR_PLL3RDYC                    ((uint32_t)0x00400000)        /*!< PLL3 Ready Interrupt Clear */
01893 #endif /* STM32F10X_CL */
01894 
01895 /*****************  Bit definition for RCC_APB2RSTR register  *****************/
01896 #define  RCC_APB2RSTR_AFIORST                ((uint32_t)0x00000001)        /*!< Alternate Function I/O reset */
01897 #define  RCC_APB2RSTR_IOPARST                ((uint32_t)0x00000004)        /*!< I/O port A reset */
01898 #define  RCC_APB2RSTR_IOPBRST                ((uint32_t)0x00000008)        /*!< I/O port B reset */
01899 #define  RCC_APB2RSTR_IOPCRST                ((uint32_t)0x00000010)        /*!< I/O port C reset */
01900 #define  RCC_APB2RSTR_IOPDRST                ((uint32_t)0x00000020)        /*!< I/O port D reset */
01901 #define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC 1 interface reset */
01902 
01903 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
01904 #define  RCC_APB2RSTR_ADC2RST                ((uint32_t)0x00000400)        /*!< ADC 2 interface reset */
01905 #endif
01906 
01907 #define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000800)        /*!< TIM1 Timer reset */
01908 #define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI 1 reset */
01909 #define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 reset */
01910 
01911 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
01912 #define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 Timer reset */
01913 #define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 Timer reset */
01914 #define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 Timer reset */
01915 #endif
01916 
01917 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
01918  #define  RCC_APB2RSTR_IOPERST               ((uint32_t)0x00000040)        /*!< I/O port E reset */
01919 #endif /* STM32F10X_LD && STM32F10X_LD_VL */
01920 
01921 #if defined (STM32F10X_HD) || defined (STM32F10X_XL)
01922  #define  RCC_APB2RSTR_IOPFRST               ((uint32_t)0x00000080)        /*!< I/O port F reset */
01923  #define  RCC_APB2RSTR_IOPGRST               ((uint32_t)0x00000100)        /*!< I/O port G reset */
01924  #define  RCC_APB2RSTR_TIM8RST               ((uint32_t)0x00002000)        /*!< TIM8 Timer reset */
01925  #define  RCC_APB2RSTR_ADC3RST               ((uint32_t)0x00008000)        /*!< ADC3 interface reset */
01926 #endif
01927 
01928 #if defined (STM32F10X_HD_VL)
01929  #define  RCC_APB2RSTR_IOPFRST               ((uint32_t)0x00000080)        /*!< I/O port F reset */
01930  #define  RCC_APB2RSTR_IOPGRST               ((uint32_t)0x00000100)        /*!< I/O port G reset */
01931 #endif
01932 
01933 #ifdef STM32F10X_XL
01934  #define  RCC_APB2RSTR_TIM9RST               ((uint32_t)0x00080000)         /*!< TIM9 Timer reset */
01935  #define  RCC_APB2RSTR_TIM10RST              ((uint32_t)0x00100000)         /*!< TIM10 Timer reset */
01936  #define  RCC_APB2RSTR_TIM11RST              ((uint32_t)0x00200000)         /*!< TIM11 Timer reset */
01937 #endif /* STM32F10X_XL */
01938 
01939 /*****************  Bit definition for RCC_APB1RSTR register  *****************/
01940 #define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 reset */
01941 #define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 reset */
01942 #define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog reset */
01943 #define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 reset */
01944 #define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 reset */
01945 
01946 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
01947 #define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)        /*!< CAN1 reset */
01948 #endif
01949 
01950 #define  RCC_APB1RSTR_BKPRST                 ((uint32_t)0x08000000)        /*!< Backup interface reset */
01951 #define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< Power interface reset */
01952 
01953 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
01954  #define  RCC_APB1RSTR_TIM4RST               ((uint32_t)0x00000004)        /*!< Timer 4 reset */
01955  #define  RCC_APB1RSTR_SPI2RST               ((uint32_t)0x00004000)        /*!< SPI 2 reset */
01956  #define  RCC_APB1RSTR_USART3RST             ((uint32_t)0x00040000)        /*!< RUSART 3 reset */
01957  #define  RCC_APB1RSTR_I2C2RST               ((uint32_t)0x00400000)        /*!< I2C 2 reset */
01958 #endif /* STM32F10X_LD && STM32F10X_LD_VL */
01959 
01960 #if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined  (STM32F10X_XL)
01961  #define  RCC_APB1RSTR_USBRST                ((uint32_t)0x00800000)        /*!< USB Device reset */
01962 #endif
01963 
01964 #if defined (STM32F10X_HD) || defined  (STM32F10X_CL) || defined  (STM32F10X_XL)
01965  #define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */
01966  #define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
01967  #define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
01968  #define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI 3 reset */
01969  #define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)        /*!< UART 4 reset */
01970  #define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)        /*!< UART 5 reset */
01971  #define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */
01972 #endif
01973 
01974 #if defined (STM32F10X_LD_VL) || defined  (STM32F10X_MD_VL) || defined  (STM32F10X_HD_VL)
01975  #define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
01976  #define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
01977  #define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */
01978  #define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x40000000)        /*!< CEC interface reset */ 
01979 #endif
01980 
01981 #if defined  (STM32F10X_HD_VL)
01982  #define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */
01983  #define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)        /*!< TIM12 Timer reset */
01984  #define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)        /*!< TIM13 Timer reset */
01985  #define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)        /*!< TIM14 Timer reset */
01986  #define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI 3 reset */ 
01987  #define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)        /*!< UART 4 reset */
01988  #define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)        /*!< UART 5 reset */ 
01989 #endif
01990 
01991 #ifdef STM32F10X_CL
01992  #define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000)        /*!< CAN2 reset */
01993 #endif /* STM32F10X_CL */
01994 
01995 #ifdef STM32F10X_XL
01996  #define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)         /*!< TIM12 Timer reset */
01997  #define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)         /*!< TIM13 Timer reset */
01998  #define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)         /*!< TIM14 Timer reset */
01999 #endif /* STM32F10X_XL */
02000 
02001 /******************  Bit definition for RCC_AHBENR register  ******************/
02002 #define  RCC_AHBENR_DMA1EN                   ((uint16_t)0x0001)            /*!< DMA1 clock enable */
02003 #define  RCC_AHBENR_SRAMEN                   ((uint16_t)0x0004)            /*!< SRAM interface clock enable */
02004 #define  RCC_AHBENR_FLITFEN                  ((uint16_t)0x0010)            /*!< FLITF clock enable */
02005 #define  RCC_AHBENR_CRCEN                    ((uint16_t)0x0040)            /*!< CRC clock enable */
02006 
02007 #if defined (STM32F10X_HD) || defined  (STM32F10X_CL) || defined  (STM32F10X_HD_VL)
02008  #define  RCC_AHBENR_DMA2EN                  ((uint16_t)0x0002)            /*!< DMA2 clock enable */
02009 #endif
02010 
02011 #if defined (STM32F10X_HD) || defined (STM32F10X_XL)
02012  #define  RCC_AHBENR_FSMCEN                  ((uint16_t)0x0100)            /*!< FSMC clock enable */
02013  #define  RCC_AHBENR_SDIOEN                  ((uint16_t)0x0400)            /*!< SDIO clock enable */
02014 #endif
02015 
02016 #if defined (STM32F10X_HD_VL)
02017  #define  RCC_AHBENR_FSMCEN                  ((uint16_t)0x0100)            /*!< FSMC clock enable */
02018 #endif
02019 
02020 #ifdef STM32F10X_CL
02021  #define  RCC_AHBENR_OTGFSEN                 ((uint32_t)0x00001000)         /*!< USB OTG FS clock enable */
02022  #define  RCC_AHBENR_ETHMACEN                ((uint32_t)0x00004000)         /*!< ETHERNET MAC clock enable */
02023  #define  RCC_AHBENR_ETHMACTXEN              ((uint32_t)0x00008000)         /*!< ETHERNET MAC Tx clock enable */
02024  #define  RCC_AHBENR_ETHMACRXEN              ((uint32_t)0x00010000)         /*!< ETHERNET MAC Rx clock enable */
02025 #endif /* STM32F10X_CL */
02026 
02027 /******************  Bit definition for RCC_APB2ENR register  *****************/
02028 #define  RCC_APB2ENR_AFIOEN                  ((uint32_t)0x00000001)         /*!< Alternate Function I/O clock enable */
02029 #define  RCC_APB2ENR_IOPAEN                  ((uint32_t)0x00000004)         /*!< I/O port A clock enable */
02030 #define  RCC_APB2ENR_IOPBEN                  ((uint32_t)0x00000008)         /*!< I/O port B clock enable */
02031 #define  RCC_APB2ENR_IOPCEN                  ((uint32_t)0x00000010)         /*!< I/O port C clock enable */
02032 #define  RCC_APB2ENR_IOPDEN                  ((uint32_t)0x00000020)         /*!< I/O port D clock enable */
02033 #define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)         /*!< ADC 1 interface clock enable */
02034 
02035 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
02036 #define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000400)         /*!< ADC 2 interface clock enable */
02037 #endif
02038 
02039 #define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)         /*!< TIM1 Timer clock enable */
02040 #define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)         /*!< SPI 1 clock enable */
02041 #define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)         /*!< USART1 clock enable */
02042 
02043 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
02044 #define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)         /*!< TIM15 Timer clock enable */
02045 #define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)         /*!< TIM16 Timer clock enable */
02046 #define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)         /*!< TIM17 Timer clock enable */
02047 #endif
02048 
02049 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
02050  #define  RCC_APB2ENR_IOPEEN                 ((uint32_t)0x00000040)         /*!< I/O port E clock enable */
02051 #endif /* STM32F10X_LD && STM32F10X_LD_VL */
02052 
02053 #if defined (STM32F10X_HD) || defined (STM32F10X_XL)
02054  #define  RCC_APB2ENR_IOPFEN                 ((uint32_t)0x00000080)         /*!< I/O port F clock enable */
02055  #define  RCC_APB2ENR_IOPGEN                 ((uint32_t)0x00000100)         /*!< I/O port G clock enable */
02056  #define  RCC_APB2ENR_TIM8EN                 ((uint32_t)0x00002000)         /*!< TIM8 Timer clock enable */
02057  #define  RCC_APB2ENR_ADC3EN                 ((uint32_t)0x00008000)         /*!< DMA1 clock enable */
02058 #endif
02059 
02060 #if defined (STM32F10X_HD_VL)
02061  #define  RCC_APB2ENR_IOPFEN                 ((uint32_t)0x00000080)         /*!< I/O port F clock enable */
02062  #define  RCC_APB2ENR_IOPGEN                 ((uint32_t)0x00000100)         /*!< I/O port G clock enable */
02063 #endif
02064 
02065 #ifdef STM32F10X_XL
02066  #define  RCC_APB2ENR_TIM9EN                 ((uint32_t)0x00080000)         /*!< TIM9 Timer clock enable  */
02067  #define  RCC_APB2ENR_TIM10EN                ((uint32_t)0x00100000)         /*!< TIM10 Timer clock enable  */
02068  #define  RCC_APB2ENR_TIM11EN                ((uint32_t)0x00200000)         /*!< TIM11 Timer clock enable */
02069 #endif
02070 
02071 /*****************  Bit definition for RCC_APB1ENR register  ******************/
02072 #define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled*/
02073 #define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
02074 #define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
02075 #define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART 2 clock enable */
02076 #define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C 1 clock enable */
02077 
02078 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
02079 #define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)        /*!< CAN1 clock enable */
02080 #endif
02081 
02082 #define  RCC_APB1ENR_BKPEN                   ((uint32_t)0x08000000)        /*!< Backup interface clock enable */
02083 #define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< Power interface clock enable */
02084 
02085 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
02086  #define  RCC_APB1ENR_TIM4EN                 ((uint32_t)0x00000004)        /*!< Timer 4 clock enable */
02087  #define  RCC_APB1ENR_SPI2EN                 ((uint32_t)0x00004000)        /*!< SPI 2 clock enable */
02088  #define  RCC_APB1ENR_USART3EN               ((uint32_t)0x00040000)        /*!< USART 3 clock enable */
02089  #define  RCC_APB1ENR_I2C2EN                 ((uint32_t)0x00400000)        /*!< I2C 2 clock enable */
02090 #endif /* STM32F10X_LD && STM32F10X_LD_VL */
02091 
02092 #if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined  (STM32F10X_LD)
02093  #define  RCC_APB1ENR_USBEN                  ((uint32_t)0x00800000)        /*!< USB Device clock enable */
02094 #endif
02095 
02096 #if defined (STM32F10X_HD) || defined  (STM32F10X_CL)
02097  #define  RCC_APB1ENR_TIM5EN                 ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
02098  #define  RCC_APB1ENR_TIM6EN                 ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
02099  #define  RCC_APB1ENR_TIM7EN                 ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
02100  #define  RCC_APB1ENR_SPI3EN                 ((uint32_t)0x00008000)        /*!< SPI 3 clock enable */
02101  #define  RCC_APB1ENR_UART4EN                ((uint32_t)0x00080000)        /*!< UART 4 clock enable */
02102  #define  RCC_APB1ENR_UART5EN                ((uint32_t)0x00100000)        /*!< UART 5 clock enable */
02103  #define  RCC_APB1ENR_DACEN                  ((uint32_t)0x20000000)        /*!< DAC interface clock enable */
02104 #endif
02105 
02106 #if defined (STM32F10X_LD_VL) || defined  (STM32F10X_MD_VL) || defined  (STM32F10X_HD_VL)
02107  #define  RCC_APB1ENR_TIM6EN                 ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
02108  #define  RCC_APB1ENR_TIM7EN                 ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
02109  #define  RCC_APB1ENR_DACEN                  ((uint32_t)0x20000000)        /*!< DAC interface clock enable */
02110  #define  RCC_APB1ENR_CECEN                  ((uint32_t)0x40000000)        /*!< CEC interface clock enable */ 
02111 #endif
02112 
02113 #ifdef STM32F10X_HD_VL
02114  #define  RCC_APB1ENR_TIM5EN                 ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
02115  #define  RCC_APB1ENR_TIM12EN                ((uint32_t)0x00000040)         /*!< TIM12 Timer clock enable  */
02116  #define  RCC_APB1ENR_TIM13EN                ((uint32_t)0x00000080)         /*!< TIM13 Timer clock enable  */
02117  #define  RCC_APB1ENR_TIM14EN                ((uint32_t)0x00000100)         /*!< TIM14 Timer clock enable */
02118  #define  RCC_APB1ENR_SPI3EN                 ((uint32_t)0x00008000)        /*!< SPI 3 clock enable */
02119  #define  RCC_APB1ENR_UART4EN                ((uint32_t)0x00080000)        /*!< UART 4 clock enable */
02120  #define  RCC_APB1ENR_UART5EN                ((uint32_t)0x00100000)        /*!< UART 5 clock enable */ 
02121 #endif /* STM32F10X_HD_VL */
02122 
02123 #ifdef STM32F10X_CL
02124  #define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000)        /*!< CAN2 clock enable */
02125 #endif /* STM32F10X_CL */
02126 
02127 #ifdef STM32F10X_XL
02128  #define  RCC_APB1ENR_TIM12EN                ((uint32_t)0x00000040)         /*!< TIM12 Timer clock enable  */
02129  #define  RCC_APB1ENR_TIM13EN                ((uint32_t)0x00000080)         /*!< TIM13 Timer clock enable  */
02130  #define  RCC_APB1ENR_TIM14EN                ((uint32_t)0x00000100)         /*!< TIM14 Timer clock enable */
02131 #endif /* STM32F10X_XL */
02132 
02133 /*******************  Bit definition for RCC_BDCR register  *******************/
02134 #define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
02135 #define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
02136 #define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
02137 
02138 #define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
02139 #define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
02140 #define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
02141 
02142 /*!< RTC congiguration */
02143 #define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
02144 #define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
02145 #define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
02146 #define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 128 used as RTC clock */
02147 
02148 #define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
02149 #define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
02150 
02151 /*******************  Bit definition for RCC_CSR register  ********************/  
02152 #define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
02153 #define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
02154 #define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
02155 #define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
02156 #define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
02157 #define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
02158 #define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
02159 #define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
02160 #define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
02161 
02162 #ifdef STM32F10X_CL
02163 /*******************  Bit definition for RCC_AHBRSTR register  ****************/
02164  #define  RCC_AHBRSTR_OTGFSRST               ((uint32_t)0x00001000)         /*!< USB OTG FS reset */
02165  #define  RCC_AHBRSTR_ETHMACRST              ((uint32_t)0x00004000)         /*!< ETHERNET MAC reset */
02166 
02167 /*******************  Bit definition for RCC_CFGR2 register  ******************/
02168 /*!< PREDIV1 configuration */
02169  #define  RCC_CFGR2_PREDIV1                  ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
02170  #define  RCC_CFGR2_PREDIV1_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
02171  #define  RCC_CFGR2_PREDIV1_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
02172  #define  RCC_CFGR2_PREDIV1_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
02173  #define  RCC_CFGR2_PREDIV1_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
02174 
02175  #define  RCC_CFGR2_PREDIV1_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
02176  #define  RCC_CFGR2_PREDIV1_DIV2             ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
02177  #define  RCC_CFGR2_PREDIV1_DIV3             ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
02178  #define  RCC_CFGR2_PREDIV1_DIV4             ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
02179  #define  RCC_CFGR2_PREDIV1_DIV5             ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
02180  #define  RCC_CFGR2_PREDIV1_DIV6             ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
02181  #define  RCC_CFGR2_PREDIV1_DIV7             ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
02182  #define  RCC_CFGR2_PREDIV1_DIV8             ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
02183  #define  RCC_CFGR2_PREDIV1_DIV9             ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
02184  #define  RCC_CFGR2_PREDIV1_DIV10            ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
02185  #define  RCC_CFGR2_PREDIV1_DIV11            ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
02186  #define  RCC_CFGR2_PREDIV1_DIV12            ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
02187  #define  RCC_CFGR2_PREDIV1_DIV13            ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
02188  #define  RCC_CFGR2_PREDIV1_DIV14            ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
02189  #define  RCC_CFGR2_PREDIV1_DIV15            ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
02190  #define  RCC_CFGR2_PREDIV1_DIV16            ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
02191 
02192 /*!< PREDIV2 configuration */
02193  #define  RCC_CFGR2_PREDIV2                  ((uint32_t)0x000000F0)        /*!< PREDIV2[3:0] bits */
02194  #define  RCC_CFGR2_PREDIV2_0                ((uint32_t)0x00000010)        /*!< Bit 0 */
02195  #define  RCC_CFGR2_PREDIV2_1                ((uint32_t)0x00000020)        /*!< Bit 1 */
02196  #define  RCC_CFGR2_PREDIV2_2                ((uint32_t)0x00000040)        /*!< Bit 2 */
02197  #define  RCC_CFGR2_PREDIV2_3                ((uint32_t)0x00000080)        /*!< Bit 3 */
02198 
02199  #define  RCC_CFGR2_PREDIV2_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV2 input clock not divided */
02200  #define  RCC_CFGR2_PREDIV2_DIV2             ((uint32_t)0x00000010)        /*!< PREDIV2 input clock divided by 2 */
02201  #define  RCC_CFGR2_PREDIV2_DIV3             ((uint32_t)0x00000020)        /*!< PREDIV2 input clock divided by 3 */
02202  #define  RCC_CFGR2_PREDIV2_DIV4             ((uint32_t)0x00000030)        /*!< PREDIV2 input clock divided by 4 */
02203  #define  RCC_CFGR2_PREDIV2_DIV5             ((uint32_t)0x00000040)        /*!< PREDIV2 input clock divided by 5 */
02204  #define  RCC_CFGR2_PREDIV2_DIV6             ((uint32_t)0x00000050)        /*!< PREDIV2 input clock divided by 6 */
02205  #define  RCC_CFGR2_PREDIV2_DIV7             ((uint32_t)0x00000060)        /*!< PREDIV2 input clock divided by 7 */
02206  #define  RCC_CFGR2_PREDIV2_DIV8             ((uint32_t)0x00000070)        /*!< PREDIV2 input clock divided by 8 */
02207  #define  RCC_CFGR2_PREDIV2_DIV9             ((uint32_t)0x00000080)        /*!< PREDIV2 input clock divided by 9 */
02208  #define  RCC_CFGR2_PREDIV2_DIV10            ((uint32_t)0x00000090)        /*!< PREDIV2 input clock divided by 10 */
02209  #define  RCC_CFGR2_PREDIV2_DIV11            ((uint32_t)0x000000A0)        /*!< PREDIV2 input clock divided by 11 */
02210  #define  RCC_CFGR2_PREDIV2_DIV12            ((uint32_t)0x000000B0)        /*!< PREDIV2 input clock divided by 12 */
02211  #define  RCC_CFGR2_PREDIV2_DIV13            ((uint32_t)0x000000C0)        /*!< PREDIV2 input clock divided by 13 */
02212  #define  RCC_CFGR2_PREDIV2_DIV14            ((uint32_t)0x000000D0)        /*!< PREDIV2 input clock divided by 14 */
02213  #define  RCC_CFGR2_PREDIV2_DIV15            ((uint32_t)0x000000E0)        /*!< PREDIV2 input clock divided by 15 */
02214  #define  RCC_CFGR2_PREDIV2_DIV16            ((uint32_t)0x000000F0)        /*!< PREDIV2 input clock divided by 16 */
02215 
02216 /*!< PLL2MUL configuration */
02217  #define  RCC_CFGR2_PLL2MUL                  ((uint32_t)0x00000F00)        /*!< PLL2MUL[3:0] bits */
02218  #define  RCC_CFGR2_PLL2MUL_0                ((uint32_t)0x00000100)        /*!< Bit 0 */
02219  #define  RCC_CFGR2_PLL2MUL_1                ((uint32_t)0x00000200)        /*!< Bit 1 */
02220  #define  RCC_CFGR2_PLL2MUL_2                ((uint32_t)0x00000400)        /*!< Bit 2 */
02221  #define  RCC_CFGR2_PLL2MUL_3                ((uint32_t)0x00000800)        /*!< Bit 3 */
02222 
02223  #define  RCC_CFGR2_PLL2MUL8                 ((uint32_t)0x00000600)        /*!< PLL2 input clock * 8 */
02224  #define  RCC_CFGR2_PLL2MUL9                 ((uint32_t)0x00000700)        /*!< PLL2 input clock * 9 */
02225  #define  RCC_CFGR2_PLL2MUL10                ((uint32_t)0x00000800)        /*!< PLL2 input clock * 10 */
02226  #define  RCC_CFGR2_PLL2MUL11                ((uint32_t)0x00000900)        /*!< PLL2 input clock * 11 */
02227  #define  RCC_CFGR2_PLL2MUL12                ((uint32_t)0x00000A00)        /*!< PLL2 input clock * 12 */
02228  #define  RCC_CFGR2_PLL2MUL13                ((uint32_t)0x00000B00)        /*!< PLL2 input clock * 13 */
02229  #define  RCC_CFGR2_PLL2MUL14                ((uint32_t)0x00000C00)        /*!< PLL2 input clock * 14 */
02230  #define  RCC_CFGR2_PLL2MUL16                ((uint32_t)0x00000E00)        /*!< PLL2 input clock * 16 */
02231  #define  RCC_CFGR2_PLL2MUL20                ((uint32_t)0x00000F00)        /*!< PLL2 input clock * 20 */
02232 
02233 /*!< PLL3MUL configuration */
02234  #define  RCC_CFGR2_PLL3MUL                  ((uint32_t)0x0000F000)        /*!< PLL3MUL[3:0] bits */
02235  #define  RCC_CFGR2_PLL3MUL_0                ((uint32_t)0x00001000)        /*!< Bit 0 */
02236  #define  RCC_CFGR2_PLL3MUL_1                ((uint32_t)0x00002000)        /*!< Bit 1 */
02237  #define  RCC_CFGR2_PLL3MUL_2                ((uint32_t)0x00004000)        /*!< Bit 2 */
02238  #define  RCC_CFGR2_PLL3MUL_3                ((uint32_t)0x00008000)        /*!< Bit 3 */
02239 
02240  #define  RCC_CFGR2_PLL3MUL8                 ((uint32_t)0x00006000)        /*!< PLL3 input clock * 8 */
02241  #define  RCC_CFGR2_PLL3MUL9                 ((uint32_t)0x00007000)        /*!< PLL3 input clock * 9 */
02242  #define  RCC_CFGR2_PLL3MUL10                ((uint32_t)0x00008000)        /*!< PLL3 input clock * 10 */
02243  #define  RCC_CFGR2_PLL3MUL11                ((uint32_t)0x00009000)        /*!< PLL3 input clock * 11 */
02244  #define  RCC_CFGR2_PLL3MUL12                ((uint32_t)0x0000A000)        /*!< PLL3 input clock * 12 */
02245  #define  RCC_CFGR2_PLL3MUL13                ((uint32_t)0x0000B000)        /*!< PLL3 input clock * 13 */
02246  #define  RCC_CFGR2_PLL3MUL14                ((uint32_t)0x0000C000)        /*!< PLL3 input clock * 14 */
02247  #define  RCC_CFGR2_PLL3MUL16                ((uint32_t)0x0000E000)        /*!< PLL3 input clock * 16 */
02248  #define  RCC_CFGR2_PLL3MUL20                ((uint32_t)0x0000F000)        /*!< PLL3 input clock * 20 */
02249 
02250  #define  RCC_CFGR2_PREDIV1SRC               ((uint32_t)0x00010000)        /*!< PREDIV1 entry clock source */
02251  #define  RCC_CFGR2_PREDIV1SRC_PLL2          ((uint32_t)0x00010000)        /*!< PLL2 selected as PREDIV1 entry clock source */
02252  #define  RCC_CFGR2_PREDIV1SRC_HSE           ((uint32_t)0x00000000)        /*!< HSE selected as PREDIV1 entry clock source */
02253  #define  RCC_CFGR2_I2S2SRC                  ((uint32_t)0x00020000)        /*!< I2S2 entry clock source */
02254  #define  RCC_CFGR2_I2S3SRC                  ((uint32_t)0x00040000)        /*!< I2S3 clock source */
02255 #endif /* STM32F10X_CL */
02256 
02257 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
02258 /*******************  Bit definition for RCC_CFGR2 register  ******************/
02259 /*!< PREDIV1 configuration */
02260  #define  RCC_CFGR2_PREDIV1                  ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
02261  #define  RCC_CFGR2_PREDIV1_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
02262  #define  RCC_CFGR2_PREDIV1_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
02263  #define  RCC_CFGR2_PREDIV1_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
02264  #define  RCC_CFGR2_PREDIV1_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
02265 
02266  #define  RCC_CFGR2_PREDIV1_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
02267  #define  RCC_CFGR2_PREDIV1_DIV2             ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
02268  #define  RCC_CFGR2_PREDIV1_DIV3             ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
02269  #define  RCC_CFGR2_PREDIV1_DIV4             ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
02270  #define  RCC_CFGR2_PREDIV1_DIV5             ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
02271  #define  RCC_CFGR2_PREDIV1_DIV6             ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
02272  #define  RCC_CFGR2_PREDIV1_DIV7             ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
02273  #define  RCC_CFGR2_PREDIV1_DIV8             ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
02274  #define  RCC_CFGR2_PREDIV1_DIV9             ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
02275  #define  RCC_CFGR2_PREDIV1_DIV10            ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
02276  #define  RCC_CFGR2_PREDIV1_DIV11            ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
02277  #define  RCC_CFGR2_PREDIV1_DIV12            ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
02278  #define  RCC_CFGR2_PREDIV1_DIV13            ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
02279  #define  RCC_CFGR2_PREDIV1_DIV14            ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
02280  #define  RCC_CFGR2_PREDIV1_DIV15            ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
02281  #define  RCC_CFGR2_PREDIV1_DIV16            ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
02282 #endif
02283  
02284 /******************************************************************************/
02285 /*                                                                            */
02286 /*                General Purpose and Alternate Function I/O                  */
02287 /*                                                                            */
02288 /******************************************************************************/
02289 
02290 /*******************  Bit definition for GPIO_CRL register  *******************/
02291 #define  GPIO_CRL_MODE                       ((uint32_t)0x33333333)        /*!< Port x mode bits */
02292 
02293 #define  GPIO_CRL_MODE0                      ((uint32_t)0x00000003)        /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
02294 #define  GPIO_CRL_MODE0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
02295 #define  GPIO_CRL_MODE0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
02296 
02297 #define  GPIO_CRL_MODE1                      ((uint32_t)0x00000030)        /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
02298 #define  GPIO_CRL_MODE1_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
02299 #define  GPIO_CRL_MODE1_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
02300 
02301 #define  GPIO_CRL_MODE2                      ((uint32_t)0x00000300)        /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
02302 #define  GPIO_CRL_MODE2_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
02303 #define  GPIO_CRL_MODE2_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
02304 
02305 #define  GPIO_CRL_MODE3                      ((uint32_t)0x00003000)        /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
02306 #define  GPIO_CRL_MODE3_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
02307 #define  GPIO_CRL_MODE3_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
02308 
02309 #define  GPIO_CRL_MODE4                      ((uint32_t)0x00030000)        /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
02310 #define  GPIO_CRL_MODE4_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */
02311 #define  GPIO_CRL_MODE4_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */
02312 
02313 #define  GPIO_CRL_MODE5                      ((uint32_t)0x00300000)        /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
02314 #define  GPIO_CRL_MODE5_0                    ((uint32_t)0x00100000)        /*!< Bit 0 */
02315 #define  GPIO_CRL_MODE5_1                    ((uint32_t)0x00200000)        /*!< Bit 1 */
02316 
02317 #define  GPIO_CRL_MODE6                      ((uint32_t)0x03000000)        /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
02318 #define  GPIO_CRL_MODE6_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
02319 #define  GPIO_CRL_MODE6_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
02320 
02321 #define  GPIO_CRL_MODE7                      ((uint32_t)0x30000000)        /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
02322 #define  GPIO_CRL_MODE7_0                    ((uint32_t)0x10000000)        /*!< Bit 0 */
02323 #define  GPIO_CRL_MODE7_1                    ((uint32_t)0x20000000)        /*!< Bit 1 */
02324 
02325 #define  GPIO_CRL_CNF                        ((uint32_t)0xCCCCCCCC)        /*!< Port x configuration bits */
02326 
02327 #define  GPIO_CRL_CNF0                       ((uint32_t)0x0000000C)        /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
02328 #define  GPIO_CRL_CNF0_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */
02329 #define  GPIO_CRL_CNF0_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */
02330 
02331 #define  GPIO_CRL_CNF1                       ((uint32_t)0x000000C0)        /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
02332 #define  GPIO_CRL_CNF1_0                     ((uint32_t)0x00000040)        /*!< Bit 0 */
02333 #define  GPIO_CRL_CNF1_1                     ((uint32_t)0x00000080)        /*!< Bit 1 */
02334 
02335 #define  GPIO_CRL_CNF2                       ((uint32_t)0x00000C00)        /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
02336 #define  GPIO_CRL_CNF2_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
02337 #define  GPIO_CRL_CNF2_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
02338 
02339 #define  GPIO_CRL_CNF3                       ((uint32_t)0x0000C000)        /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
02340 #define  GPIO_CRL_CNF3_0                     ((uint32_t)0x00004000)        /*!< Bit 0 */
02341 #define  GPIO_CRL_CNF3_1                     ((uint32_t)0x00008000)        /*!< Bit 1 */
02342 
02343 #define  GPIO_CRL_CNF4                       ((uint32_t)0x000C0000)        /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
02344 #define  GPIO_CRL_CNF4_0                     ((uint32_t)0x00040000)        /*!< Bit 0 */
02345 #define  GPIO_CRL_CNF4_1                     ((uint32_t)0x00080000)        /*!< Bit 1 */
02346 
02347 #define  GPIO_CRL_CNF5                       ((uint32_t)0x00C00000)        /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
02348 #define  GPIO_CRL_CNF5_0                     ((uint32_t)0x00400000)        /*!< Bit 0 */
02349 #define  GPIO_CRL_CNF5_1                     ((uint32_t)0x00800000)        /*!< Bit 1 */
02350 
02351 #define  GPIO_CRL_CNF6                       ((uint32_t)0x0C000000)        /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
02352 #define  GPIO_CRL_CNF6_0                     ((uint32_t)0x04000000)        /*!< Bit 0 */
02353 #define  GPIO_CRL_CNF6_1                     ((uint32_t)0x08000000)        /*!< Bit 1 */
02354 
02355 #define  GPIO_CRL_CNF7                       ((uint32_t)0xC0000000)        /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
02356 #define  GPIO_CRL_CNF7_0                     ((uint32_t)0x40000000)        /*!< Bit 0 */
02357 #define  GPIO_CRL_CNF7_1                     ((uint32_t)0x80000000)        /*!< Bit 1 */
02358 
02359 /*******************  Bit definition for GPIO_CRH register  *******************/
02360 #define  GPIO_CRH_MODE                       ((uint32_t)0x33333333)        /*!< Port x mode bits */
02361 
02362 #define  GPIO_CRH_MODE8                      ((uint32_t)0x00000003)        /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
02363 #define  GPIO_CRH_MODE8_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
02364 #define  GPIO_CRH_MODE8_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
02365 
02366 #define  GPIO_CRH_MODE9                      ((uint32_t)0x00000030)        /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
02367 #define  GPIO_CRH_MODE9_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
02368 #define  GPIO_CRH_MODE9_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
02369 
02370 #define  GPIO_CRH_MODE10                     ((uint32_t)0x00000300)        /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
02371 #define  GPIO_CRH_MODE10_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
02372 #define  GPIO_CRH_MODE10_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
02373 
02374 #define  GPIO_CRH_MODE11                     ((uint32_t)0x00003000)        /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
02375 #define  GPIO_CRH_MODE11_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
02376 #define  GPIO_CRH_MODE11_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
02377 
02378 #define  GPIO_CRH_MODE12                     ((uint32_t)0x00030000)        /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
02379 #define  GPIO_CRH_MODE12_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
02380 #define  GPIO_CRH_MODE12_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
02381 
02382 #define  GPIO_CRH_MODE13                     ((uint32_t)0x00300000)        /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
02383 #define  GPIO_CRH_MODE13_0                   ((uint32_t)0x00100000)        /*!< Bit 0 */
02384 #define  GPIO_CRH_MODE13_1                   ((uint32_t)0x00200000)        /*!< Bit 1 */
02385 
02386 #define  GPIO_CRH_MODE14                     ((uint32_t)0x03000000)        /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
02387 #define  GPIO_CRH_MODE14_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
02388 #define  GPIO_CRH_MODE14_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
02389 
02390 #define  GPIO_CRH_MODE15                     ((uint32_t)0x30000000)        /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
02391 #define  GPIO_CRH_MODE15_0                   ((uint32_t)0x10000000)        /*!< Bit 0 */
02392 #define  GPIO_CRH_MODE15_1                   ((uint32_t)0x20000000)        /*!< Bit 1 */
02393 
02394 #define  GPIO_CRH_CNF                        ((uint32_t)0xCCCCCCCC)        /*!< Port x configuration bits */
02395 
02396 #define  GPIO_CRH_CNF8                       ((uint32_t)0x0000000C)        /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
02397 #define  GPIO_CRH_CNF8_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */
02398 #define  GPIO_CRH_CNF8_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */
02399 
02400 #define  GPIO_CRH_CNF9                       ((uint32_t)0x000000C0)        /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
02401 #define  GPIO_CRH_CNF9_0                     ((uint32_t)0x00000040)        /*!< Bit 0 */
02402 #define  GPIO_CRH_CNF9_1                     ((uint32_t)0x00000080)        /*!< Bit 1 */
02403 
02404 #define  GPIO_CRH_CNF10                      ((uint32_t)0x00000C00)        /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
02405 #define  GPIO_CRH_CNF10_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */
02406 #define  GPIO_CRH_CNF10_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */
02407 
02408 #define  GPIO_CRH_CNF11                      ((uint32_t)0x0000C000)        /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
02409 #define  GPIO_CRH_CNF11_0                    ((uint32_t)0x00004000)        /*!< Bit 0 */
02410 #define  GPIO_CRH_CNF11_1                    ((uint32_t)0x00008000)        /*!< Bit 1 */
02411 
02412 #define  GPIO_CRH_CNF12                      ((uint32_t)0x000C0000)        /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
02413 #define  GPIO_CRH_CNF12_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
02414 #define  GPIO_CRH_CNF12_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
02415 
02416 #define  GPIO_CRH_CNF13                      ((uint32_t)0x00C00000)        /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
02417 #define  GPIO_CRH_CNF13_0                    ((uint32_t)0x00400000)        /*!< Bit 0 */
02418 #define  GPIO_CRH_CNF13_1                    ((uint32_t)0x00800000)        /*!< Bit 1 */
02419 
02420 #define  GPIO_CRH_CNF14                      ((uint32_t)0x0C000000)        /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
02421 #define  GPIO_CRH_CNF14_0                    ((uint32_t)0x04000000)        /*!< Bit 0 */
02422 #define  GPIO_CRH_CNF14_1                    ((uint32_t)0x08000000)        /*!< Bit 1 */
02423 
02424 #define  GPIO_CRH_CNF15                      ((uint32_t)0xC0000000)        /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
02425 #define  GPIO_CRH_CNF15_0                    ((uint32_t)0x40000000)        /*!< Bit 0 */
02426 #define  GPIO_CRH_CNF15_1                    ((uint32_t)0x80000000)        /*!< Bit 1 */
02427 
02428 /*!<******************  Bit definition for GPIO_IDR register  *******************/
02429 #define GPIO_IDR_IDR0                        ((uint16_t)0x0001)            /*!< Port input data, bit 0 */
02430 #define GPIO_IDR_IDR1                        ((uint16_t)0x0002)            /*!< Port input data, bit 1 */
02431 #define GPIO_IDR_IDR2                        ((uint16_t)0x0004)            /*!< Port input data, bit 2 */
02432 #define GPIO_IDR_IDR3                        ((uint16_t)0x0008)            /*!< Port input data, bit 3 */
02433 #define GPIO_IDR_IDR4                        ((uint16_t)0x0010)            /*!< Port input data, bit 4 */
02434 #define GPIO_IDR_IDR5                        ((uint16_t)0x0020)            /*!< Port input data, bit 5 */
02435 #define GPIO_IDR_IDR6                        ((uint16_t)0x0040)            /*!< Port input data, bit 6 */
02436 #define GPIO_IDR_IDR7                        ((uint16_t)0x0080)            /*!< Port input data, bit 7 */
02437 #define GPIO_IDR_IDR8                        ((uint16_t)0x0100)            /*!< Port input data, bit 8 */
02438 #define GPIO_IDR_IDR9                        ((uint16_t)0x0200)            /*!< Port input data, bit 9 */
02439 #define GPIO_IDR_IDR10                       ((uint16_t)0x0400)            /*!< Port input data, bit 10 */
02440 #define GPIO_IDR_IDR11                       ((uint16_t)0x0800)            /*!< Port input data, bit 11 */
02441 #define GPIO_IDR_IDR12                       ((uint16_t)0x1000)            /*!< Port input data, bit 12 */
02442 #define GPIO_IDR_IDR13                       ((uint16_t)0x2000)            /*!< Port input data, bit 13 */
02443 #define GPIO_IDR_IDR14                       ((uint16_t)0x4000)            /*!< Port input data, bit 14 */
02444 #define GPIO_IDR_IDR15                       ((uint16_t)0x8000)            /*!< Port input data, bit 15 */
02445 
02446 /*******************  Bit definition for GPIO_ODR register  *******************/
02447 #define GPIO_ODR_ODR0                        ((uint16_t)0x0001)            /*!< Port output data, bit 0 */
02448 #define GPIO_ODR_ODR1                        ((uint16_t)0x0002)            /*!< Port output data, bit 1 */
02449 #define GPIO_ODR_ODR2                        ((uint16_t)0x0004)            /*!< Port output data, bit 2 */
02450 #define GPIO_ODR_ODR3                        ((uint16_t)0x0008)            /*!< Port output data, bit 3 */
02451 #define GPIO_ODR_ODR4                        ((uint16_t)0x0010)            /*!< Port output data, bit 4 */
02452 #define GPIO_ODR_ODR5                        ((uint16_t)0x0020)            /*!< Port output data, bit 5 */
02453 #define GPIO_ODR_ODR6                        ((uint16_t)0x0040)            /*!< Port output data, bit 6 */
02454 #define GPIO_ODR_ODR7                        ((uint16_t)0x0080)            /*!< Port output data, bit 7 */
02455 #define GPIO_ODR_ODR8                        ((uint16_t)0x0100)            /*!< Port output data, bit 8 */
02456 #define GPIO_ODR_ODR9                        ((uint16_t)0x0200)            /*!< Port output data, bit 9 */
02457 #define GPIO_ODR_ODR10                       ((uint16_t)0x0400)            /*!< Port output data, bit 10 */
02458 #define GPIO_ODR_ODR11                       ((uint16_t)0x0800)            /*!< Port output data, bit 11 */
02459 #define GPIO_ODR_ODR12                       ((uint16_t)0x1000)            /*!< Port output data, bit 12 */
02460 #define GPIO_ODR_ODR13                       ((uint16_t)0x2000)            /*!< Port output data, bit 13 */
02461 #define GPIO_ODR_ODR14                       ((uint16_t)0x4000)            /*!< Port output data, bit 14 */
02462 #define GPIO_ODR_ODR15                       ((uint16_t)0x8000)            /*!< Port output data, bit 15 */
02463 
02464 /******************  Bit definition for GPIO_BSRR register  *******************/
02465 #define GPIO_BSRR_BS0                        ((uint32_t)0x00000001)        /*!< Port x Set bit 0 */
02466 #define GPIO_BSRR_BS1                        ((uint32_t)0x00000002)        /*!< Port x Set bit 1 */
02467 #define GPIO_BSRR_BS2                        ((uint32_t)0x00000004)        /*!< Port x Set bit 2 */
02468 #define GPIO_BSRR_BS3                        ((uint32_t)0x00000008)        /*!< Port x Set bit 3 */
02469 #define GPIO_BSRR_BS4                        ((uint32_t)0x00000010)        /*!< Port x Set bit 4 */
02470 #define GPIO_BSRR_BS5                        ((uint32_t)0x00000020)        /*!< Port x Set bit 5 */
02471 #define GPIO_BSRR_BS6                        ((uint32_t)0x00000040)        /*!< Port x Set bit 6 */
02472 #define GPIO_BSRR_BS7                        ((uint32_t)0x00000080)        /*!< Port x Set bit 7 */
02473 #define GPIO_BSRR_BS8                        ((uint32_t)0x00000100)        /*!< Port x Set bit 8 */
02474 #define GPIO_BSRR_BS9                        ((uint32_t)0x00000200)        /*!< Port x Set bit 9 */
02475 #define GPIO_BSRR_BS10                       ((uint32_t)0x00000400)        /*!< Port x Set bit 10 */
02476 #define GPIO_BSRR_BS11                       ((uint32_t)0x00000800)        /*!< Port x Set bit 11 */
02477 #define GPIO_BSRR_BS12                       ((uint32_t)0x00001000)        /*!< Port x Set bit 12 */
02478 #define GPIO_BSRR_BS13                       ((uint32_t)0x00002000)        /*!< Port x Set bit 13 */
02479 #define GPIO_BSRR_BS14                       ((uint32_t)0x00004000)        /*!< Port x Set bit 14 */
02480 #define GPIO_BSRR_BS15                       ((uint32_t)0x00008000)        /*!< Port x Set bit 15 */
02481 
02482 #define GPIO_BSRR_BR0                        ((uint32_t)0x00010000)        /*!< Port x Reset bit 0 */
02483 #define GPIO_BSRR_BR1                        ((uint32_t)0x00020000)        /*!< Port x Reset bit 1 */
02484 #define GPIO_BSRR_BR2                        ((uint32_t)0x00040000)        /*!< Port x Reset bit 2 */
02485 #define GPIO_BSRR_BR3                        ((uint32_t)0x00080000)        /*!< Port x Reset bit 3 */
02486 #define GPIO_BSRR_BR4                        ((uint32_t)0x00100000)        /*!< Port x Reset bit 4 */
02487 #define GPIO_BSRR_BR5                        ((uint32_t)0x00200000)        /*!< Port x Reset bit 5 */
02488 #define GPIO_BSRR_BR6                        ((uint32_t)0x00400000)        /*!< Port x Reset bit 6 */
02489 #define GPIO_BSRR_BR7                        ((uint32_t)0x00800000)        /*!< Port x Reset bit 7 */
02490 #define GPIO_BSRR_BR8                        ((uint32_t)0x01000000)        /*!< Port x Reset bit 8 */
02491 #define GPIO_BSRR_BR9                        ((uint32_t)0x02000000)        /*!< Port x Reset bit 9 */
02492 #define GPIO_BSRR_BR10                       ((uint32_t)0x04000000)        /*!< Port x Reset bit 10 */
02493 #define GPIO_BSRR_BR11                       ((uint32_t)0x08000000)        /*!< Port x Reset bit 11 */
02494 #define GPIO_BSRR_BR12                       ((uint32_t)0x10000000)        /*!< Port x Reset bit 12 */
02495 #define GPIO_BSRR_BR13                       ((uint32_t)0x20000000)        /*!< Port x Reset bit 13 */
02496 #define GPIO_BSRR_BR14                       ((uint32_t)0x40000000)        /*!< Port x Reset bit 14 */
02497 #define GPIO_BSRR_BR15                       ((uint32_t)0x80000000)        /*!< Port x Reset bit 15 */
02498 
02499 /*******************  Bit definition for GPIO_BRR register  *******************/
02500 #define GPIO_BRR_BR0                         ((uint16_t)0x0001)            /*!< Port x Reset bit 0 */
02501 #define GPIO_BRR_BR1                         ((uint16_t)0x0002)            /*!< Port x Reset bit 1 */
02502 #define GPIO_BRR_BR2                         ((uint16_t)0x0004)            /*!< Port x Reset bit 2 */
02503 #define GPIO_BRR_BR3                         ((uint16_t)0x0008)            /*!< Port x Reset bit 3 */
02504 #define GPIO_BRR_BR4                         ((uint16_t)0x0010)            /*!< Port x Reset bit 4 */
02505 #define GPIO_BRR_BR5                         ((uint16_t)0x0020)            /*!< Port x Reset bit 5 */
02506 #define GPIO_BRR_BR6                         ((uint16_t)0x0040)            /*!< Port x Reset bit 6 */
02507 #define GPIO_BRR_BR7                         ((uint16_t)0x0080)            /*!< Port x Reset bit 7 */
02508 #define GPIO_BRR_BR8                         ((uint16_t)0x0100)            /*!< Port x Reset bit 8 */
02509 #define GPIO_BRR_BR9                         ((uint16_t)0x0200)            /*!< Port x Reset bit 9 */
02510 #define GPIO_BRR_BR10                        ((uint16_t)0x0400)            /*!< Port x Reset bit 10 */
02511 #define GPIO_BRR_BR11                        ((uint16_t)0x0800)            /*!< Port x Reset bit 11 */
02512 #define GPIO_BRR_BR12                        ((uint16_t)0x1000)            /*!< Port x Reset bit 12 */
02513 #define GPIO_BRR_BR13                        ((uint16_t)0x2000)            /*!< Port x Reset bit 13 */
02514 #define GPIO_BRR_BR14                        ((uint16_t)0x4000)            /*!< Port x Reset bit 14 */
02515 #define GPIO_BRR_BR15                        ((uint16_t)0x8000)            /*!< Port x Reset bit 15 */
02516 
02517 /******************  Bit definition for GPIO_LCKR register  *******************/
02518 #define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001)        /*!< Port x Lock bit 0 */
02519 #define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002)        /*!< Port x Lock bit 1 */
02520 #define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004)        /*!< Port x Lock bit 2 */
02521 #define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008)        /*!< Port x Lock bit 3 */
02522 #define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010)        /*!< Port x Lock bit 4 */
02523 #define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020)        /*!< Port x Lock bit 5 */
02524 #define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040)        /*!< Port x Lock bit 6 */
02525 #define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080)        /*!< Port x Lock bit 7 */
02526 #define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100)        /*!< Port x Lock bit 8 */
02527 #define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200)        /*!< Port x Lock bit 9 */
02528 #define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400)        /*!< Port x Lock bit 10 */
02529 #define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800)        /*!< Port x Lock bit 11 */
02530 #define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000)        /*!< Port x Lock bit 12 */
02531 #define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000)        /*!< Port x Lock bit 13 */
02532 #define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000)        /*!< Port x Lock bit 14 */
02533 #define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000)        /*!< Port x Lock bit 15 */
02534 #define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000)        /*!< Lock key */
02535 
02536 /*----------------------------------------------------------------------------*/
02537 
02538 /******************  Bit definition for AFIO_EVCR register  *******************/
02539 #define AFIO_EVCR_PIN                        ((uint8_t)0x0F)               /*!< PIN[3:0] bits (Pin selection) */
02540 #define AFIO_EVCR_PIN_0                      ((uint8_t)0x01)               /*!< Bit 0 */
02541 #define AFIO_EVCR_PIN_1                      ((uint8_t)0x02)               /*!< Bit 1 */
02542 #define AFIO_EVCR_PIN_2                      ((uint8_t)0x04)               /*!< Bit 2 */
02543 #define AFIO_EVCR_PIN_3                      ((uint8_t)0x08)               /*!< Bit 3 */
02544 
02545 /*!< PIN configuration */
02546 #define AFIO_EVCR_PIN_PX0                    ((uint8_t)0x00)               /*!< Pin 0 selected */
02547 #define AFIO_EVCR_PIN_PX1                    ((uint8_t)0x01)               /*!< Pin 1 selected */
02548 #define AFIO_EVCR_PIN_PX2                    ((uint8_t)0x02)               /*!< Pin 2 selected */
02549 #define AFIO_EVCR_PIN_PX3                    ((uint8_t)0x03)               /*!< Pin 3 selected */
02550 #define AFIO_EVCR_PIN_PX4                    ((uint8_t)0x04)               /*!< Pin 4 selected */
02551 #define AFIO_EVCR_PIN_PX5                    ((uint8_t)0x05)               /*!< Pin 5 selected */
02552 #define AFIO_EVCR_PIN_PX6                    ((uint8_t)0x06)               /*!< Pin 6 selected */
02553 #define AFIO_EVCR_PIN_PX7                    ((uint8_t)0x07)               /*!< Pin 7 selected */
02554 #define AFIO_EVCR_PIN_PX8                    ((uint8_t)0x08)               /*!< Pin 8 selected */
02555 #define AFIO_EVCR_PIN_PX9                    ((uint8_t)0x09)               /*!< Pin 9 selected */
02556 #define AFIO_EVCR_PIN_PX10                   ((uint8_t)0x0A)               /*!< Pin 10 selected */
02557 #define AFIO_EVCR_PIN_PX11                   ((uint8_t)0x0B)               /*!< Pin 11 selected */
02558 #define AFIO_EVCR_PIN_PX12                   ((uint8_t)0x0C)               /*!< Pin 12 selected */
02559 #define AFIO_EVCR_PIN_PX13                   ((uint8_t)0x0D)               /*!< Pin 13 selected */
02560 #define AFIO_EVCR_PIN_PX14                   ((uint8_t)0x0E)               /*!< Pin 14 selected */
02561 #define AFIO_EVCR_PIN_PX15                   ((uint8_t)0x0F)               /*!< Pin 15 selected */
02562 
02563 #define AFIO_EVCR_PORT                       ((uint8_t)0x70)               /*!< PORT[2:0] bits (Port selection) */
02564 #define AFIO_EVCR_PORT_0                     ((uint8_t)0x10)               /*!< Bit 0 */
02565 #define AFIO_EVCR_PORT_1                     ((uint8_t)0x20)               /*!< Bit 1 */
02566 #define AFIO_EVCR_PORT_2                     ((uint8_t)0x40)               /*!< Bit 2 */
02567 
02568 /*!< PORT configuration */
02569 #define AFIO_EVCR_PORT_PA                    ((uint8_t)0x00)               /*!< Port A selected */
02570 #define AFIO_EVCR_PORT_PB                    ((uint8_t)0x10)               /*!< Port B selected */
02571 #define AFIO_EVCR_PORT_PC                    ((uint8_t)0x20)               /*!< Port C selected */
02572 #define AFIO_EVCR_PORT_PD                    ((uint8_t)0x30)               /*!< Port D selected */
02573 #define AFIO_EVCR_PORT_PE                    ((uint8_t)0x40)               /*!< Port E selected */
02574 
02575 #define AFIO_EVCR_EVOE                       ((uint8_t)0x80)               /*!< Event Output Enable */
02576 
02577 /******************  Bit definition for AFIO_MAPR register  *******************/
02578 #define AFIO_MAPR_SPI1_REMAP                 ((uint32_t)0x00000001)        /*!< SPI1 remapping */
02579 #define AFIO_MAPR_I2C1_REMAP                 ((uint32_t)0x00000002)        /*!< I2C1 remapping */
02580 #define AFIO_MAPR_USART1_REMAP               ((uint32_t)0x00000004)        /*!< USART1 remapping */
02581 #define AFIO_MAPR_USART2_REMAP               ((uint32_t)0x00000008)        /*!< USART2 remapping */
02582 
02583 #define AFIO_MAPR_USART3_REMAP               ((uint32_t)0x00000030)        /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
02584 #define AFIO_MAPR_USART3_REMAP_0             ((uint32_t)0x00000010)        /*!< Bit 0 */
02585 #define AFIO_MAPR_USART3_REMAP_1             ((uint32_t)0x00000020)        /*!< Bit 1 */
02586 
02587 /* USART3_REMAP configuration */
02588 #define AFIO_MAPR_USART3_REMAP_NOREMAP       ((uint32_t)0x00000000)        /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
02589 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  ((uint32_t)0x00000010)        /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
02590 #define AFIO_MAPR_USART3_REMAP_FULLREMAP     ((uint32_t)0x00000030)        /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
02591 
02592 #define AFIO_MAPR_TIM1_REMAP                 ((uint32_t)0x000000C0)        /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
02593 #define AFIO_MAPR_TIM1_REMAP_0               ((uint32_t)0x00000040)        /*!< Bit 0 */
02594 #define AFIO_MAPR_TIM1_REMAP_1               ((uint32_t)0x00000080)        /*!< Bit 1 */
02595 
02596 /*!< TIM1_REMAP configuration */
02597 #define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
02598 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    ((uint32_t)0x00000040)        /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
02599 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP       ((uint32_t)0x000000C0)        /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
02600 
02601 #define AFIO_MAPR_TIM2_REMAP                 ((uint32_t)0x00000300)        /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
02602 #define AFIO_MAPR_TIM2_REMAP_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
02603 #define AFIO_MAPR_TIM2_REMAP_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
02604 
02605 /*!< TIM2_REMAP configuration */
02606 #define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
02607 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   ((uint32_t)0x00000100)        /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
02608 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2   ((uint32_t)0x00000200)        /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
02609 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP       ((uint32_t)0x00000300)        /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
02610 
02611 #define AFIO_MAPR_TIM3_REMAP                 ((uint32_t)0x00000C00)        /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
02612 #define AFIO_MAPR_TIM3_REMAP_0               ((uint32_t)0x00000400)        /*!< Bit 0 */
02613 #define AFIO_MAPR_TIM3_REMAP_1               ((uint32_t)0x00000800)        /*!< Bit 1 */
02614 
02615 /*!< TIM3_REMAP configuration */
02616 #define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
02617 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    ((uint32_t)0x00000800)        /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
02618 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP       ((uint32_t)0x00000C00)        /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
02619 
02620 #define AFIO_MAPR_TIM4_REMAP                 ((uint32_t)0x00001000)        /*!< TIM4_REMAP bit (TIM4 remapping) */
02621 
02622 #define AFIO_MAPR_CAN_REMAP                  ((uint32_t)0x00006000)        /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
02623 #define AFIO_MAPR_CAN_REMAP_0                ((uint32_t)0x00002000)        /*!< Bit 0 */
02624 #define AFIO_MAPR_CAN_REMAP_1                ((uint32_t)0x00004000)        /*!< Bit 1 */
02625 
02626 /*!< CAN_REMAP configuration */
02627 #define AFIO_MAPR_CAN_REMAP_REMAP1           ((uint32_t)0x00000000)        /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
02628 #define AFIO_MAPR_CAN_REMAP_REMAP2           ((uint32_t)0x00004000)        /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
02629 #define AFIO_MAPR_CAN_REMAP_REMAP3           ((uint32_t)0x00006000)        /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
02630 
02631 #define AFIO_MAPR_PD01_REMAP                 ((uint32_t)0x00008000)        /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
02632 #define AFIO_MAPR_TIM5CH4_IREMAP             ((uint32_t)0x00010000)        /*!< TIM5 Channel4 Internal Remap */
02633 #define AFIO_MAPR_ADC1_ETRGINJ_REMAP         ((uint32_t)0x00020000)        /*!< ADC 1 External Trigger Injected Conversion remapping */
02634 #define AFIO_MAPR_ADC1_ETRGREG_REMAP         ((uint32_t)0x00040000)        /*!< ADC 1 External Trigger Regular Conversion remapping */
02635 #define AFIO_MAPR_ADC2_ETRGINJ_REMAP         ((uint32_t)0x00080000)        /*!< ADC 2 External Trigger Injected Conversion remapping */
02636 #define AFIO_MAPR_ADC2_ETRGREG_REMAP         ((uint32_t)0x00100000)        /*!< ADC 2 External Trigger Regular Conversion remapping */
02637 
02638 /*!< SWJ_CFG configuration */
02639 #define AFIO_MAPR_SWJ_CFG                    ((uint32_t)0x07000000)        /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
02640 #define AFIO_MAPR_SWJ_CFG_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
02641 #define AFIO_MAPR_SWJ_CFG_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
02642 #define AFIO_MAPR_SWJ_CFG_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
02643 
02644 #define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)        /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
02645 #define AFIO_MAPR_SWJ_CFG_NOJNTRST           ((uint32_t)0x01000000)        /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
02646 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE        ((uint32_t)0x02000000)        /*!< JTAG-DP Disabled and SW-DP Enabled */
02647 #define AFIO_MAPR_SWJ_CFG_DISABLE            ((uint32_t)0x04000000)        /*!< JTAG-DP Disabled and SW-DP Disabled */
02648 
02649 #ifdef STM32F10X_CL
02650 /*!< ETH_REMAP configuration */
02651  #define AFIO_MAPR_ETH_REMAP                  ((uint32_t)0x00200000)        /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */
02652 
02653 /*!< CAN2_REMAP configuration */
02654  #define AFIO_MAPR_CAN2_REMAP                 ((uint32_t)0x00400000)        /*!< CAN2_REMAP bit (CAN2 I/O remapping) */
02655 
02656 /*!< MII_RMII_SEL configuration */
02657  #define AFIO_MAPR_MII_RMII_SEL               ((uint32_t)0x00800000)        /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */
02658 
02659 /*!< SPI3_REMAP configuration */
02660  #define AFIO_MAPR_SPI3_REMAP                 ((uint32_t)0x10000000)        /*!< SPI3_REMAP bit (SPI3 remapping) */
02661 
02662 /*!< TIM2ITR1_IREMAP configuration */
02663  #define AFIO_MAPR_TIM2ITR1_IREMAP            ((uint32_t)0x20000000)        /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */
02664 
02665 /*!< PTP_PPS_REMAP configuration */
02666  #define AFIO_MAPR_PTP_PPS_REMAP              ((uint32_t)0x20000000)        /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */
02667 #endif
02668 
02669 /*****************  Bit definition for AFIO_EXTICR1 register  *****************/
02670 #define AFIO_EXTICR1_EXTI0                   ((uint16_t)0x000F)            /*!< EXTI 0 configuration */
02671 #define AFIO_EXTICR1_EXTI1                   ((uint16_t)0x00F0)            /*!< EXTI 1 configuration */
02672 #define AFIO_EXTICR1_EXTI2                   ((uint16_t)0x0F00)            /*!< EXTI 2 configuration */
02673 #define AFIO_EXTICR1_EXTI3                   ((uint16_t)0xF000)            /*!< EXTI 3 configuration */
02674 
02675 /*!< EXTI0 configuration */
02676 #define AFIO_EXTICR1_EXTI0_PA                ((uint16_t)0x0000)            /*!< PA[0] pin */
02677 #define AFIO_EXTICR1_EXTI0_PB                ((uint16_t)0x0001)            /*!< PB[0] pin */
02678 #define AFIO_EXTICR1_EXTI0_PC                ((uint16_t)0x0002)            /*!< PC[0] pin */
02679 #define AFIO_EXTICR1_EXTI0_PD                ((uint16_t)0x0003)            /*!< PD[0] pin */
02680 #define AFIO_EXTICR1_EXTI0_PE                ((uint16_t)0x0004)            /*!< PE[0] pin */
02681 #define AFIO_EXTICR1_EXTI0_PF                ((uint16_t)0x0005)            /*!< PF[0] pin */
02682 #define AFIO_EXTICR1_EXTI0_PG                ((uint16_t)0x0006)            /*!< PG[0] pin */
02683 
02684 /*!< EXTI1 configuration */
02685 #define AFIO_EXTICR1_EXTI1_PA                ((uint16_t)0x0000)            /*!< PA[1] pin */
02686 #define AFIO_EXTICR1_EXTI1_PB                ((uint16_t)0x0010)            /*!< PB[1] pin */
02687 #define AFIO_EXTICR1_EXTI1_PC                ((uint16_t)0x0020)            /*!< PC[1] pin */
02688 #define AFIO_EXTICR1_EXTI1_PD                ((uint16_t)0x0030)            /*!< PD[1] pin */
02689 #define AFIO_EXTICR1_EXTI1_PE                ((uint16_t)0x0040)            /*!< PE[1] pin */
02690 #define AFIO_EXTICR1_EXTI1_PF                ((uint16_t)0x0050)            /*!< PF[1] pin */
02691 #define AFIO_EXTICR1_EXTI1_PG                ((uint16_t)0x0060)            /*!< PG[1] pin */
02692 
02693 /*!< EXTI2 configuration */  
02694 #define AFIO_EXTICR1_EXTI2_PA                ((uint16_t)0x0000)            /*!< PA[2] pin */
02695 #define AFIO_EXTICR1_EXTI2_PB                ((uint16_t)0x0100)            /*!< PB[2] pin */
02696 #define AFIO_EXTICR1_EXTI2_PC                ((uint16_t)0x0200)            /*!< PC[2] pin */
02697 #define AFIO_EXTICR1_EXTI2_PD                ((uint16_t)0x0300)            /*!< PD[2] pin */
02698 #define AFIO_EXTICR1_EXTI2_PE                ((uint16_t)0x0400)            /*!< PE[2] pin */
02699 #define AFIO_EXTICR1_EXTI2_PF                ((uint16_t)0x0500)            /*!< PF[2] pin */
02700 #define AFIO_EXTICR1_EXTI2_PG                ((uint16_t)0x0600)            /*!< PG[2] pin */
02701 
02702 /*!< EXTI3 configuration */
02703 #define AFIO_EXTICR1_EXTI3_PA                ((uint16_t)0x0000)            /*!< PA[3] pin */
02704 #define AFIO_EXTICR1_EXTI3_PB                ((uint16_t)0x1000)            /*!< PB[3] pin */
02705 #define AFIO_EXTICR1_EXTI3_PC                ((uint16_t)0x2000)            /*!< PC[3] pin */
02706 #define AFIO_EXTICR1_EXTI3_PD                ((uint16_t)0x3000)            /*!< PD[3] pin */
02707 #define AFIO_EXTICR1_EXTI3_PE                ((uint16_t)0x4000)            /*!< PE[3] pin */
02708 #define AFIO_EXTICR1_EXTI3_PF                ((uint16_t)0x5000)            /*!< PF[3] pin */
02709 #define AFIO_EXTICR1_EXTI3_PG                ((uint16_t)0x6000)            /*!< PG[3] pin */
02710 
02711 /*****************  Bit definition for AFIO_EXTICR2 register  *****************/
02712 #define AFIO_EXTICR2_EXTI4                   ((uint16_t)0x000F)            /*!< EXTI 4 configuration */
02713 #define AFIO_EXTICR2_EXTI5                   ((uint16_t)0x00F0)            /*!< EXTI 5 configuration */
02714 #define AFIO_EXTICR2_EXTI6                   ((uint16_t)0x0F00)            /*!< EXTI 6 configuration */
02715 #define AFIO_EXTICR2_EXTI7                   ((uint16_t)0xF000)            /*!< EXTI 7 configuration */
02716 
02717 /*!< EXTI4 configuration */
02718 #define AFIO_EXTICR2_EXTI4_PA                ((uint16_t)0x0000)            /*!< PA[4] pin */
02719 #define AFIO_EXTICR2_EXTI4_PB                ((uint16_t)0x0001)            /*!< PB[4] pin */
02720 #define AFIO_EXTICR2_EXTI4_PC                ((uint16_t)0x0002)            /*!< PC[4] pin */
02721 #define AFIO_EXTICR2_EXTI4_PD                ((uint16_t)0x0003)            /*!< PD[4] pin */
02722 #define AFIO_EXTICR2_EXTI4_PE                ((uint16_t)0x0004)            /*!< PE[4] pin */
02723 #define AFIO_EXTICR2_EXTI4_PF                ((uint16_t)0x0005)            /*!< PF[4] pin */
02724 #define AFIO_EXTICR2_EXTI4_PG                ((uint16_t)0x0006)            /*!< PG[4] pin */
02725 
02726 /* EXTI5 configuration */
02727 #define AFIO_EXTICR2_EXTI5_PA                ((uint16_t)0x0000)            /*!< PA[5] pin */
02728 #define AFIO_EXTICR2_EXTI5_PB                ((uint16_t)0x0010)            /*!< PB[5] pin */
02729 #define AFIO_EXTICR2_EXTI5_PC                ((uint16_t)0x0020)            /*!< PC[5] pin */
02730 #define AFIO_EXTICR2_EXTI5_PD                ((uint16_t)0x0030)            /*!< PD[5] pin */
02731 #define AFIO_EXTICR2_EXTI5_PE                ((uint16_t)0x0040)            /*!< PE[5] pin */
02732 #define AFIO_EXTICR2_EXTI5_PF                ((uint16_t)0x0050)            /*!< PF[5] pin */
02733 #define AFIO_EXTICR2_EXTI5_PG                ((uint16_t)0x0060)            /*!< PG[5] pin */
02734 
02735 /*!< EXTI6 configuration */  
02736 #define AFIO_EXTICR2_EXTI6_PA                ((uint16_t)0x0000)            /*!< PA[6] pin */
02737 #define AFIO_EXTICR2_EXTI6_PB                ((uint16_t)0x0100)            /*!< PB[6] pin */
02738 #define AFIO_EXTICR2_EXTI6_PC                ((uint16_t)0x0200)            /*!< PC[6] pin */
02739 #define AFIO_EXTICR2_EXTI6_PD                ((uint16_t)0x0300)            /*!< PD[6] pin */
02740 #define AFIO_EXTICR2_EXTI6_PE                ((uint16_t)0x0400)            /*!< PE[6] pin */
02741 #define AFIO_EXTICR2_EXTI6_PF                ((uint16_t)0x0500)            /*!< PF[6] pin */
02742 #define AFIO_EXTICR2_EXTI6_PG                ((uint16_t)0x0600)            /*!< PG[6] pin */
02743 
02744 /*!< EXTI7 configuration */
02745 #define AFIO_EXTICR2_EXTI7_PA                ((uint16_t)0x0000)            /*!< PA[7] pin */
02746 #define AFIO_EXTICR2_EXTI7_PB                ((uint16_t)0x1000)            /*!< PB[7] pin */
02747 #define AFIO_EXTICR2_EXTI7_PC                ((uint16_t)0x2000)            /*!< PC[7] pin */
02748 #define AFIO_EXTICR2_EXTI7_PD                ((uint16_t)0x3000)            /*!< PD[7] pin */
02749 #define AFIO_EXTICR2_EXTI7_PE                ((uint16_t)0x4000)            /*!< PE[7] pin */
02750 #define AFIO_EXTICR2_EXTI7_PF                ((uint16_t)0x5000)            /*!< PF[7] pin */
02751 #define AFIO_EXTICR2_EXTI7_PG                ((uint16_t)0x6000)            /*!< PG[7] pin */
02752 
02753 /*****************  Bit definition for AFIO_EXTICR3 register  *****************/
02754 #define AFIO_EXTICR3_EXTI8                   ((uint16_t)0x000F)            /*!< EXTI 8 configuration */
02755 #define AFIO_EXTICR3_EXTI9                   ((uint16_t)0x00F0)            /*!< EXTI 9 configuration */
02756 #define AFIO_EXTICR3_EXTI10                  ((uint16_t)0x0F00)            /*!< EXTI 10 configuration */
02757 #define AFIO_EXTICR3_EXTI11                  ((uint16_t)0xF000)            /*!< EXTI 11 configuration */
02758 
02759 /*!< EXTI8 configuration */
02760 #define AFIO_EXTICR3_EXTI8_PA                ((uint16_t)0x0000)            /*!< PA[8] pin */
02761 #define AFIO_EXTICR3_EXTI8_PB                ((uint16_t)0x0001)            /*!< PB[8] pin */
02762 #define AFIO_EXTICR3_EXTI8_PC                ((uint16_t)0x0002)            /*!< PC[8] pin */
02763 #define AFIO_EXTICR3_EXTI8_PD                ((uint16_t)0x0003)            /*!< PD[8] pin */
02764 #define AFIO_EXTICR3_EXTI8_PE                ((uint16_t)0x0004)            /*!< PE[8] pin */
02765 #define AFIO_EXTICR3_EXTI8_PF                ((uint16_t)0x0005)            /*!< PF[8] pin */
02766 #define AFIO_EXTICR3_EXTI8_PG                ((uint16_t)0x0006)            /*!< PG[8] pin */
02767 
02768 /*!< EXTI9 configuration */
02769 #define AFIO_EXTICR3_EXTI9_PA                ((uint16_t)0x0000)            /*!< PA[9] pin */
02770 #define AFIO_EXTICR3_EXTI9_PB                ((uint16_t)0x0010)            /*!< PB[9] pin */
02771 #define AFIO_EXTICR3_EXTI9_PC                ((uint16_t)0x0020)            /*!< PC[9] pin */
02772 #define AFIO_EXTICR3_EXTI9_PD                ((uint16_t)0x0030)            /*!< PD[9] pin */
02773 #define AFIO_EXTICR3_EXTI9_PE                ((uint16_t)0x0040)            /*!< PE[9] pin */
02774 #define AFIO_EXTICR3_EXTI9_PF                ((uint16_t)0x0050)            /*!< PF[9] pin */
02775 #define AFIO_EXTICR3_EXTI9_PG                ((uint16_t)0x0060)            /*!< PG[9] pin */
02776 
02777 /*!< EXTI10 configuration */  
02778 #define AFIO_EXTICR3_EXTI10_PA               ((uint16_t)0x0000)            /*!< PA[10] pin */
02779 #define AFIO_EXTICR3_EXTI10_PB               ((uint16_t)0x0100)            /*!< PB[10] pin */
02780 #define AFIO_EXTICR3_EXTI10_PC               ((uint16_t)0x0200)            /*!< PC[10] pin */
02781 #define AFIO_EXTICR3_EXTI10_PD               ((uint16_t)0x0300)            /*!< PD[10] pin */
02782 #define AFIO_EXTICR3_EXTI10_PE               ((uint16_t)0x0400)            /*!< PE[10] pin */
02783 #define AFIO_EXTICR3_EXTI10_PF               ((uint16_t)0x0500)            /*!< PF[10] pin */
02784 #define AFIO_EXTICR3_EXTI10_PG               ((uint16_t)0x0600)            /*!< PG[10] pin */
02785 
02786 /*!< EXTI11 configuration */
02787 #define AFIO_EXTICR3_EXTI11_PA               ((uint16_t)0x0000)            /*!< PA[11] pin */
02788 #define AFIO_EXTICR3_EXTI11_PB               ((uint16_t)0x1000)            /*!< PB[11] pin */
02789 #define AFIO_EXTICR3_EXTI11_PC               ((uint16_t)0x2000)            /*!< PC[11] pin */
02790 #define AFIO_EXTICR3_EXTI11_PD               ((uint16_t)0x3000)            /*!< PD[11] pin */
02791 #define AFIO_EXTICR3_EXTI11_PE               ((uint16_t)0x4000)            /*!< PE[11] pin */
02792 #define AFIO_EXTICR3_EXTI11_PF               ((uint16_t)0x5000)            /*!< PF[11] pin */
02793 #define AFIO_EXTICR3_EXTI11_PG               ((uint16_t)0x6000)            /*!< PG[11] pin */
02794 
02795 /*****************  Bit definition for AFIO_EXTICR4 register  *****************/
02796 #define AFIO_EXTICR4_EXTI12                  ((uint16_t)0x000F)            /*!< EXTI 12 configuration */
02797 #define AFIO_EXTICR4_EXTI13                  ((uint16_t)0x00F0)            /*!< EXTI 13 configuration */
02798 #define AFIO_EXTICR4_EXTI14                  ((uint16_t)0x0F00)            /*!< EXTI 14 configuration */
02799 #define AFIO_EXTICR4_EXTI15                  ((uint16_t)0xF000)            /*!< EXTI 15 configuration */
02800 
02801 /* EXTI12 configuration */
02802 #define AFIO_EXTICR4_EXTI12_PA               ((uint16_t)0x0000)            /*!< PA[12] pin */
02803 #define AFIO_EXTICR4_EXTI12_PB               ((uint16_t)0x0001)            /*!< PB[12] pin */
02804 #define AFIO_EXTICR4_EXTI12_PC               ((uint16_t)0x0002)            /*!< PC[12] pin */
02805 #define AFIO_EXTICR4_EXTI12_PD               ((uint16_t)0x0003)            /*!< PD[12] pin */
02806 #define AFIO_EXTICR4_EXTI12_PE               ((uint16_t)0x0004)            /*!< PE[12] pin */
02807 #define AFIO_EXTICR4_EXTI12_PF               ((uint16_t)0x0005)            /*!< PF[12] pin */
02808 #define AFIO_EXTICR4_EXTI12_PG               ((uint16_t)0x0006)            /*!< PG[12] pin */
02809 
02810 /* EXTI13 configuration */
02811 #define AFIO_EXTICR4_EXTI13_PA               ((uint16_t)0x0000)            /*!< PA[13] pin */
02812 #define AFIO_EXTICR4_EXTI13_PB               ((uint16_t)0x0010)            /*!< PB[13] pin */
02813 #define AFIO_EXTICR4_EXTI13_PC               ((uint16_t)0x0020)            /*!< PC[13] pin */
02814 #define AFIO_EXTICR4_EXTI13_PD               ((uint16_t)0x0030)            /*!< PD[13] pin */
02815 #define AFIO_EXTICR4_EXTI13_PE               ((uint16_t)0x0040)            /*!< PE[13] pin */
02816 #define AFIO_EXTICR4_EXTI13_PF               ((uint16_t)0x0050)            /*!< PF[13] pin */
02817 #define AFIO_EXTICR4_EXTI13_PG               ((uint16_t)0x0060)            /*!< PG[13] pin */
02818 
02819 /*!< EXTI14 configuration */  
02820 #define AFIO_EXTICR4_EXTI14_PA               ((uint16_t)0x0000)            /*!< PA[14] pin */
02821 #define AFIO_EXTICR4_EXTI14_PB               ((uint16_t)0x0100)            /*!< PB[14] pin */
02822 #define AFIO_EXTICR4_EXTI14_PC               ((uint16_t)0x0200)            /*!< PC[14] pin */
02823 #define AFIO_EXTICR4_EXTI14_PD               ((uint16_t)0x0300)            /*!< PD[14] pin */
02824 #define AFIO_EXTICR4_EXTI14_PE               ((uint16_t)0x0400)            /*!< PE[14] pin */
02825 #define AFIO_EXTICR4_EXTI14_PF               ((uint16_t)0x0500)            /*!< PF[14] pin */
02826 #define AFIO_EXTICR4_EXTI14_PG               ((uint16_t)0x0600)            /*!< PG[14] pin */
02827 
02828 /*!< EXTI15 configuration */
02829 #define AFIO_EXTICR4_EXTI15_PA               ((uint16_t)0x0000)            /*!< PA[15] pin */
02830 #define AFIO_EXTICR4_EXTI15_PB               ((uint16_t)0x1000)            /*!< PB[15] pin */
02831 #define AFIO_EXTICR4_EXTI15_PC               ((uint16_t)0x2000)            /*!< PC[15] pin */
02832 #define AFIO_EXTICR4_EXTI15_PD               ((uint16_t)0x3000)            /*!< PD[15] pin */
02833 #define AFIO_EXTICR4_EXTI15_PE               ((uint16_t)0x4000)            /*!< PE[15] pin */
02834 #define AFIO_EXTICR4_EXTI15_PF               ((uint16_t)0x5000)            /*!< PF[15] pin */
02835 #define AFIO_EXTICR4_EXTI15_PG               ((uint16_t)0x6000)            /*!< PG[15] pin */
02836 
02837 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
02838 /******************  Bit definition for AFIO_MAPR2 register  ******************/
02839 #define AFIO_MAPR2_TIM15_REMAP               ((uint32_t)0x00000001)        /*!< TIM15 remapping */
02840 #define AFIO_MAPR2_TIM16_REMAP               ((uint32_t)0x00000002)        /*!< TIM16 remapping */
02841 #define AFIO_MAPR2_TIM17_REMAP               ((uint32_t)0x00000004)        /*!< TIM17 remapping */
02842 #define AFIO_MAPR2_CEC_REMAP                 ((uint32_t)0x00000008)        /*!< CEC remapping */
02843 #define AFIO_MAPR2_TIM1_DMA_REMAP            ((uint32_t)0x00000010)        /*!< TIM1_DMA remapping */
02844 #endif
02845 
02846 #ifdef STM32F10X_HD_VL
02847 #define AFIO_MAPR2_TIM13_REMAP               ((uint32_t)0x00000100)        /*!< TIM13 remapping */
02848 #define AFIO_MAPR2_TIM14_REMAP               ((uint32_t)0x00000200)        /*!< TIM14 remapping */
02849 #define AFIO_MAPR2_FSMC_NADV_REMAP           ((uint32_t)0x00000400)        /*!< FSMC NADV remapping */
02850 #define AFIO_MAPR2_TIM67_DAC_DMA_REMAP       ((uint32_t)0x00000800)        /*!< TIM6/TIM7 and DAC DMA remapping */
02851 #define AFIO_MAPR2_TIM12_REMAP               ((uint32_t)0x00001000)        /*!< TIM12 remapping */
02852 #define AFIO_MAPR2_MISC_REMAP                ((uint32_t)0x00002000)        /*!< Miscellaneous remapping */
02853 #endif
02854 
02855 #ifdef STM32F10X_XL 
02856 /******************  Bit definition for AFIO_MAPR2 register  ******************/
02857 #define AFIO_MAPR2_TIM9_REMAP                ((uint32_t)0x00000020)        /*!< TIM9 remapping */
02858 #define AFIO_MAPR2_TIM10_REMAP               ((uint32_t)0x00000040)        /*!< TIM10 remapping */
02859 #define AFIO_MAPR2_TIM11_REMAP               ((uint32_t)0x00000080)        /*!< TIM11 remapping */
02860 #define AFIO_MAPR2_TIM13_REMAP               ((uint32_t)0x00000100)        /*!< TIM13 remapping */
02861 #define AFIO_MAPR2_TIM14_REMAP               ((uint32_t)0x00000200)        /*!< TIM14 remapping */
02862 #define AFIO_MAPR2_FSMC_NADV_REMAP           ((uint32_t)0x00000400)        /*!< FSMC NADV remapping */
02863 #endif
02864 
02865 /******************************************************************************/
02866 /*                                                                            */
02867 /*                               SystemTick                                   */
02868 /*                                                                            */
02869 /******************************************************************************/
02870 
02871 /*****************  Bit definition for SysTick_CTRL register  *****************/
02872 #define  SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)        /*!< Counter enable */
02873 #define  SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)        /*!< Counting down to 0 pends the SysTick handler */
02874 #define  SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)        /*!< Clock source */
02875 #define  SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)        /*!< Count Flag */
02876 
02877 /*****************  Bit definition for SysTick_LOAD register  *****************/
02878 #define  SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)        /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
02879 
02880 /*****************  Bit definition for SysTick_VAL register  ******************/
02881 #define  SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)        /*!< Current value at the time the register is accessed */
02882 
02883 /*****************  Bit definition for SysTick_CALIB register  ****************/
02884 #define  SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)        /*!< Reload value to use for 10ms timing */
02885 #define  SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)        /*!< Calibration value is not exactly 10 ms */
02886 #define  SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)        /*!< The reference clock is not provided */
02887 
02888 /******************************************************************************/
02889 /*                                                                            */
02890 /*                  Nested Vectored Interrupt Controller                      */
02891 /*                                                                            */
02892 /******************************************************************************/
02893 
02894 /******************  Bit definition for NVIC_ISER register  *******************/
02895 #define  NVIC_ISER_SETENA                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set enable bits */
02896 #define  NVIC_ISER_SETENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
02897 #define  NVIC_ISER_SETENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
02898 #define  NVIC_ISER_SETENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
02899 #define  NVIC_ISER_SETENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
02900 #define  NVIC_ISER_SETENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
02901 #define  NVIC_ISER_SETENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
02902 #define  NVIC_ISER_SETENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
02903 #define  NVIC_ISER_SETENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
02904 #define  NVIC_ISER_SETENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
02905 #define  NVIC_ISER_SETENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
02906 #define  NVIC_ISER_SETENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
02907 #define  NVIC_ISER_SETENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
02908 #define  NVIC_ISER_SETENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
02909 #define  NVIC_ISER_SETENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
02910 #define  NVIC_ISER_SETENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
02911 #define  NVIC_ISER_SETENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
02912 #define  NVIC_ISER_SETENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
02913 #define  NVIC_ISER_SETENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
02914 #define  NVIC_ISER_SETENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
02915 #define  NVIC_ISER_SETENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
02916 #define  NVIC_ISER_SETENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
02917 #define  NVIC_ISER_SETENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
02918 #define  NVIC_ISER_SETENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
02919 #define  NVIC_ISER_SETENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
02920 #define  NVIC_ISER_SETENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
02921 #define  NVIC_ISER_SETENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
02922 #define  NVIC_ISER_SETENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
02923 #define  NVIC_ISER_SETENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
02924 #define  NVIC_ISER_SETENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
02925 #define  NVIC_ISER_SETENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
02926 #define  NVIC_ISER_SETENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
02927 #define  NVIC_ISER_SETENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
02928 
02929 /******************  Bit definition for NVIC_ICER register  *******************/
02930 #define  NVIC_ICER_CLRENA                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-enable bits */
02931 #define  NVIC_ICER_CLRENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
02932 #define  NVIC_ICER_CLRENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
02933 #define  NVIC_ICER_CLRENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
02934 #define  NVIC_ICER_CLRENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
02935 #define  NVIC_ICER_CLRENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
02936 #define  NVIC_ICER_CLRENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
02937 #define  NVIC_ICER_CLRENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
02938 #define  NVIC_ICER_CLRENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
02939 #define  NVIC_ICER_CLRENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
02940 #define  NVIC_ICER_CLRENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
02941 #define  NVIC_ICER_CLRENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
02942 #define  NVIC_ICER_CLRENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
02943 #define  NVIC_ICER_CLRENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
02944 #define  NVIC_ICER_CLRENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
02945 #define  NVIC_ICER_CLRENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
02946 #define  NVIC_ICER_CLRENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
02947 #define  NVIC_ICER_CLRENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
02948 #define  NVIC_ICER_CLRENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
02949 #define  NVIC_ICER_CLRENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
02950 #define  NVIC_ICER_CLRENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
02951 #define  NVIC_ICER_CLRENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
02952 #define  NVIC_ICER_CLRENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
02953 #define  NVIC_ICER_CLRENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
02954 #define  NVIC_ICER_CLRENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
02955 #define  NVIC_ICER_CLRENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
02956 #define  NVIC_ICER_CLRENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
02957 #define  NVIC_ICER_CLRENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
02958 #define  NVIC_ICER_CLRENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
02959 #define  NVIC_ICER_CLRENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
02960 #define  NVIC_ICER_CLRENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
02961 #define  NVIC_ICER_CLRENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
02962 #define  NVIC_ICER_CLRENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
02963 
02964 /******************  Bit definition for NVIC_ISPR register  *******************/
02965 #define  NVIC_ISPR_SETPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set-pending bits */
02966 #define  NVIC_ISPR_SETPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
02967 #define  NVIC_ISPR_SETPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
02968 #define  NVIC_ISPR_SETPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
02969 #define  NVIC_ISPR_SETPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
02970 #define  NVIC_ISPR_SETPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
02971 #define  NVIC_ISPR_SETPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
02972 #define  NVIC_ISPR_SETPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
02973 #define  NVIC_ISPR_SETPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
02974 #define  NVIC_ISPR_SETPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
02975 #define  NVIC_ISPR_SETPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
02976 #define  NVIC_ISPR_SETPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
02977 #define  NVIC_ISPR_SETPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
02978 #define  NVIC_ISPR_SETPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
02979 #define  NVIC_ISPR_SETPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
02980 #define  NVIC_ISPR_SETPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
02981 #define  NVIC_ISPR_SETPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
02982 #define  NVIC_ISPR_SETPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
02983 #define  NVIC_ISPR_SETPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
02984 #define  NVIC_ISPR_SETPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
02985 #define  NVIC_ISPR_SETPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
02986 #define  NVIC_ISPR_SETPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
02987 #define  NVIC_ISPR_SETPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
02988 #define  NVIC_ISPR_SETPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
02989 #define  NVIC_ISPR_SETPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
02990 #define  NVIC_ISPR_SETPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
02991 #define  NVIC_ISPR_SETPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
02992 #define  NVIC_ISPR_SETPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
02993 #define  NVIC_ISPR_SETPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
02994 #define  NVIC_ISPR_SETPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
02995 #define  NVIC_ISPR_SETPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
02996 #define  NVIC_ISPR_SETPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
02997 #define  NVIC_ISPR_SETPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
02998 
02999 /******************  Bit definition for NVIC_ICPR register  *******************/
03000 #define  NVIC_ICPR_CLRPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-pending bits */
03001 #define  NVIC_ICPR_CLRPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
03002 #define  NVIC_ICPR_CLRPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
03003 #define  NVIC_ICPR_CLRPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
03004 #define  NVIC_ICPR_CLRPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
03005 #define  NVIC_ICPR_CLRPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
03006 #define  NVIC_ICPR_CLRPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
03007 #define  NVIC_ICPR_CLRPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
03008 #define  NVIC_ICPR_CLRPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
03009 #define  NVIC_ICPR_CLRPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
03010 #define  NVIC_ICPR_CLRPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
03011 #define  NVIC_ICPR_CLRPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
03012 #define  NVIC_ICPR_CLRPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
03013 #define  NVIC_ICPR_CLRPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
03014 #define  NVIC_ICPR_CLRPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
03015 #define  NVIC_ICPR_CLRPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
03016 #define  NVIC_ICPR_CLRPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
03017 #define  NVIC_ICPR_CLRPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
03018 #define  NVIC_ICPR_CLRPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
03019 #define  NVIC_ICPR_CLRPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
03020 #define  NVIC_ICPR_CLRPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
03021 #define  NVIC_ICPR_CLRPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
03022 #define  NVIC_ICPR_CLRPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
03023 #define  NVIC_ICPR_CLRPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
03024 #define  NVIC_ICPR_CLRPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
03025 #define  NVIC_ICPR_CLRPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
03026 #define  NVIC_ICPR_CLRPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
03027 #define  NVIC_ICPR_CLRPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
03028 #define  NVIC_ICPR_CLRPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
03029 #define  NVIC_ICPR_CLRPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
03030 #define  NVIC_ICPR_CLRPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
03031 #define  NVIC_ICPR_CLRPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
03032 #define  NVIC_ICPR_CLRPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
03033 
03034 /******************  Bit definition for NVIC_IABR register  *******************/
03035 #define  NVIC_IABR_ACTIVE                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt active flags */
03036 #define  NVIC_IABR_ACTIVE_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
03037 #define  NVIC_IABR_ACTIVE_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
03038 #define  NVIC_IABR_ACTIVE_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
03039 #define  NVIC_IABR_ACTIVE_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
03040 #define  NVIC_IABR_ACTIVE_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
03041 #define  NVIC_IABR_ACTIVE_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
03042 #define  NVIC_IABR_ACTIVE_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
03043 #define  NVIC_IABR_ACTIVE_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
03044 #define  NVIC_IABR_ACTIVE_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
03045 #define  NVIC_IABR_ACTIVE_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
03046 #define  NVIC_IABR_ACTIVE_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
03047 #define  NVIC_IABR_ACTIVE_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
03048 #define  NVIC_IABR_ACTIVE_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
03049 #define  NVIC_IABR_ACTIVE_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
03050 #define  NVIC_IABR_ACTIVE_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
03051 #define  NVIC_IABR_ACTIVE_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
03052 #define  NVIC_IABR_ACTIVE_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
03053 #define  NVIC_IABR_ACTIVE_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
03054 #define  NVIC_IABR_ACTIVE_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
03055 #define  NVIC_IABR_ACTIVE_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
03056 #define  NVIC_IABR_ACTIVE_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
03057 #define  NVIC_IABR_ACTIVE_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
03058 #define  NVIC_IABR_ACTIVE_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
03059 #define  NVIC_IABR_ACTIVE_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
03060 #define  NVIC_IABR_ACTIVE_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
03061 #define  NVIC_IABR_ACTIVE_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
03062 #define  NVIC_IABR_ACTIVE_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
03063 #define  NVIC_IABR_ACTIVE_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
03064 #define  NVIC_IABR_ACTIVE_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
03065 #define  NVIC_IABR_ACTIVE_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
03066 #define  NVIC_IABR_ACTIVE_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
03067 #define  NVIC_IABR_ACTIVE_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
03068 
03069 /******************  Bit definition for NVIC_PRI0 register  *******************/
03070 #define  NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 0 */
03071 #define  NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 1 */
03072 #define  NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 2 */
03073 #define  NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 3 */
03074 
03075 /******************  Bit definition for NVIC_PRI1 register  *******************/
03076 #define  NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 4 */
03077 #define  NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 5 */
03078 #define  NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 6 */
03079 #define  NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 7 */
03080 
03081 /******************  Bit definition for NVIC_PRI2 register  *******************/
03082 #define  NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 8 */
03083 #define  NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 9 */
03084 #define  NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 10 */
03085 #define  NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 11 */
03086 
03087 /******************  Bit definition for NVIC_PRI3 register  *******************/
03088 #define  NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 12 */
03089 #define  NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 13 */
03090 #define  NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 14 */
03091 #define  NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 15 */
03092 
03093 /******************  Bit definition for NVIC_PRI4 register  *******************/
03094 #define  NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 16 */
03095 #define  NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 17 */
03096 #define  NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 18 */
03097 #define  NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 19 */
03098 
03099 /******************  Bit definition for NVIC_PRI5 register  *******************/
03100 #define  NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 20 */
03101 #define  NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 21 */
03102 #define  NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 22 */
03103 #define  NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 23 */
03104 
03105 /******************  Bit definition for NVIC_PRI6 register  *******************/
03106 #define  NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 24 */
03107 #define  NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 25 */
03108 #define  NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 26 */
03109 #define  NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 27 */
03110 
03111 /******************  Bit definition for NVIC_PRI7 register  *******************/
03112 #define  NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 28 */
03113 #define  NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 29 */
03114 #define  NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 30 */
03115 #define  NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 31 */
03116 
03117 /******************  Bit definition for SCB_CPUID register  *******************/
03118 #define  SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)        /*!< Implementation defined revision number */
03119 #define  SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)        /*!< Number of processor within family */
03120 #define  SCB_CPUID_Constant                  ((uint32_t)0x000F0000)        /*!< Reads as 0x0F */
03121 #define  SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)        /*!< Implementation defined variant number */
03122 #define  SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)        /*!< Implementer code. ARM is 0x41 */
03123 
03124 /*******************  Bit definition for SCB_ICSR register  *******************/
03125 #define  SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)        /*!< Active ISR number field */
03126 #define  SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)        /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
03127 #define  SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)        /*!< Pending ISR number field */
03128 #define  SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)        /*!< Interrupt pending flag */
03129 #define  SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)        /*!< It indicates that a pending interrupt becomes active in the next running cycle */
03130 #define  SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)        /*!< Clear pending SysTick bit */
03131 #define  SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)        /*!< Set pending SysTick bit */
03132 #define  SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)        /*!< Clear pending pendSV bit */
03133 #define  SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)        /*!< Set pending pendSV bit */
03134 #define  SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)        /*!< Set pending NMI bit */
03135 
03136 /*******************  Bit definition for SCB_VTOR register  *******************/
03137 #define  SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)        /*!< Vector table base offset field */
03138 #define  SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)        /*!< Table base in code(0) or RAM(1) */
03139 
03140 /*!<*****************  Bit definition for SCB_AIRCR register  *******************/
03141 #define  SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)        /*!< System Reset bit */
03142 #define  SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)        /*!< Clear active vector bit */
03143 #define  SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)        /*!< Requests chip control logic to generate a reset */
03144 
03145 #define  SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)        /*!< PRIGROUP[2:0] bits (Priority group) */
03146 #define  SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)        /*!< Bit 0 */
03147 #define  SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)        /*!< Bit 1 */
03148 #define  SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)        /*!< Bit 2  */
03149 
03150 /* prority group configuration */
03151 #define  SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)        /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
03152 #define  SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)        /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
03153 #define  SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)        /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
03154 #define  SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)        /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
03155 #define  SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)        /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
03156 #define  SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)        /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
03157 #define  SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)        /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
03158 #define  SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)        /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
03159 
03160 #define  SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)        /*!< Data endianness bit */
03161 #define  SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)        /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
03162 
03163 /*******************  Bit definition for SCB_SCR register  ********************/
03164 #define  SCB_SCR_SLEEPONEXIT                 ((uint8_t)0x02)               /*!< Sleep on exit bit */
03165 #define  SCB_SCR_SLEEPDEEP                   ((uint8_t)0x04)               /*!< Sleep deep bit */
03166 #define  SCB_SCR_SEVONPEND                   ((uint8_t)0x10)               /*!< Wake up from WFE */
03167 
03168 /********************  Bit definition for SCB_CCR register  *******************/
03169 #define  SCB_CCR_NONBASETHRDENA              ((uint16_t)0x0001)            /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
03170 #define  SCB_CCR_USERSETMPEND                ((uint16_t)0x0002)            /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
03171 #define  SCB_CCR_UNALIGN_TRP                 ((uint16_t)0x0008)            /*!< Trap for unaligned access */
03172 #define  SCB_CCR_DIV_0_TRP                   ((uint16_t)0x0010)            /*!< Trap on Divide by 0 */
03173 #define  SCB_CCR_BFHFNMIGN                   ((uint16_t)0x0100)            /*!< Handlers running at priority -1 and -2 */
03174 #define  SCB_CCR_STKALIGN                    ((uint16_t)0x0200)            /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
03175 
03176 /*******************  Bit definition for SCB_SHPR register ********************/
03177 #define  SCB_SHPR_PRI_N                      ((uint32_t)0x000000FF)        /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
03178 #define  SCB_SHPR_PRI_N1                     ((uint32_t)0x0000FF00)        /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
03179 #define  SCB_SHPR_PRI_N2                     ((uint32_t)0x00FF0000)        /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
03180 #define  SCB_SHPR_PRI_N3                     ((uint32_t)0xFF000000)        /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
03181 
03182 /******************  Bit definition for SCB_SHCSR register  *******************/
03183 #define  SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)        /*!< MemManage is active */
03184 #define  SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)        /*!< BusFault is active */
03185 #define  SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)        /*!< UsageFault is active */
03186 #define  SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)        /*!< SVCall is active */
03187 #define  SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)        /*!< Monitor is active */
03188 #define  SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)        /*!< PendSV is active */
03189 #define  SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)        /*!< SysTick is active */
03190 #define  SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)        /*!< Usage Fault is pended */
03191 #define  SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)        /*!< MemManage is pended */
03192 #define  SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)        /*!< Bus Fault is pended */
03193 #define  SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)        /*!< SVCall is pended */
03194 #define  SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)        /*!< MemManage enable */
03195 #define  SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)        /*!< Bus Fault enable */
03196 #define  SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)        /*!< UsageFault enable */
03197 
03198 /*******************  Bit definition for SCB_CFSR register  *******************/
03199 /*!< MFSR */
03200 #define  SCB_CFSR_IACCVIOL                   ((uint32_t)0x00000001)        /*!< Instruction access violation */
03201 #define  SCB_CFSR_DACCVIOL                   ((uint32_t)0x00000002)        /*!< Data access violation */
03202 #define  SCB_CFSR_MUNSTKERR                  ((uint32_t)0x00000008)        /*!< Unstacking error */
03203 #define  SCB_CFSR_MSTKERR                    ((uint32_t)0x00000010)        /*!< Stacking error */
03204 #define  SCB_CFSR_MMARVALID                  ((uint32_t)0x00000080)        /*!< Memory Manage Address Register address valid flag */
03205 /*!< BFSR */
03206 #define  SCB_CFSR_IBUSERR                    ((uint32_t)0x00000100)        /*!< Instruction bus error flag */
03207 #define  SCB_CFSR_PRECISERR                  ((uint32_t)0x00000200)        /*!< Precise data bus error */
03208 #define  SCB_CFSR_IMPRECISERR                ((uint32_t)0x00000400)        /*!< Imprecise data bus error */
03209 #define  SCB_CFSR_UNSTKERR                   ((uint32_t)0x00000800)        /*!< Unstacking error */
03210 #define  SCB_CFSR_STKERR                     ((uint32_t)0x00001000)        /*!< Stacking error */
03211 #define  SCB_CFSR_BFARVALID                  ((uint32_t)0x00008000)        /*!< Bus Fault Address Register address valid flag */
03212 /*!< UFSR */
03213 #define  SCB_CFSR_UNDEFINSTR                 ((uint32_t)0x00010000)        /*!< The processor attempt to excecute an undefined instruction */
03214 #define  SCB_CFSR_INVSTATE                   ((uint32_t)0x00020000)        /*!< Invalid combination of EPSR and instruction */
03215 #define  SCB_CFSR_INVPC                      ((uint32_t)0x00040000)        /*!< Attempt to load EXC_RETURN into pc illegally */
03216 #define  SCB_CFSR_NOCP                       ((uint32_t)0x00080000)        /*!< Attempt to use a coprocessor instruction */
03217 #define  SCB_CFSR_UNALIGNED                  ((uint32_t)0x01000000)        /*!< Fault occurs when there is an attempt to make an unaligned memory access */
03218 #define  SCB_CFSR_DIVBYZERO                  ((uint32_t)0x02000000)        /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
03219 
03220 /*******************  Bit definition for SCB_HFSR register  *******************/
03221 #define  SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)        /*!< Fault occures because of vector table read on exception processing */
03222 #define  SCB_HFSR_FORCED                     ((uint32_t)0x40000000)        /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
03223 #define  SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)        /*!< Fault related to debug */
03224 
03225 /*******************  Bit definition for SCB_DFSR register  *******************/
03226 #define  SCB_DFSR_HALTED                     ((uint8_t)0x01)               /*!< Halt request flag */
03227 #define  SCB_DFSR_BKPT                       ((uint8_t)0x02)               /*!< BKPT flag */
03228 #define  SCB_DFSR_DWTTRAP                    ((uint8_t)0x04)               /*!< Data Watchpoint and Trace (DWT) flag */
03229 #define  SCB_DFSR_VCATCH                     ((uint8_t)0x08)               /*!< Vector catch flag */
03230 #define  SCB_DFSR_EXTERNAL                   ((uint8_t)0x10)               /*!< External debug request flag */
03231 
03232 /*******************  Bit definition for SCB_MMFAR register  ******************/
03233 #define  SCB_MMFAR_ADDRESS                   ((uint32_t)0xFFFFFFFF)        /*!< Mem Manage fault address field */
03234 
03235 /*******************  Bit definition for SCB_BFAR register  *******************/
03236 #define  SCB_BFAR_ADDRESS                    ((uint32_t)0xFFFFFFFF)        /*!< Bus fault address field */
03237 
03238 /*******************  Bit definition for SCB_afsr register  *******************/
03239 #define  SCB_AFSR_IMPDEF                     ((uint32_t)0xFFFFFFFF)        /*!< Implementation defined */
03240 
03241 /******************************************************************************/
03242 /*                                                                            */
03243 /*                    External Interrupt/Event Controller                     */
03244 /*                                                                            */
03245 /******************************************************************************/
03246 
03247 /*******************  Bit definition for EXTI_IMR register  *******************/
03248 #define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
03249 #define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
03250 #define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
03251 #define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
03252 #define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
03253 #define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
03254 #define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
03255 #define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
03256 #define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
03257 #define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
03258 #define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
03259 #define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
03260 #define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
03261 #define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
03262 #define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
03263 #define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
03264 #define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
03265 #define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
03266 #define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
03267 #define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
03268 
03269 /*******************  Bit definition for EXTI_EMR register  *******************/
03270 #define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
03271 #define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
03272 #define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
03273 #define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
03274 #define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
03275 #define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
03276 #define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
03277 #define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
03278 #define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
03279 #define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
03280 #define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
03281 #define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
03282 #define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
03283 #define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
03284 #define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
03285 #define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
03286 #define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
03287 #define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
03288 #define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
03289 #define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
03290 
03291 /******************  Bit definition for EXTI_RTSR register  *******************/
03292 #define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
03293 #define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
03294 #define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
03295 #define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
03296 #define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
03297 #define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
03298 #define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
03299 #define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
03300 #define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
03301 #define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
03302 #define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
03303 #define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
03304 #define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
03305 #define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
03306 #define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
03307 #define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
03308 #define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
03309 #define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
03310 #define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
03311 #define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
03312 
03313 /******************  Bit definition for EXTI_FTSR register  *******************/
03314 #define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
03315 #define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
03316 #define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
03317 #define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
03318 #define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
03319 #define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
03320 #define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
03321 #define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
03322 #define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
03323 #define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
03324 #define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
03325 #define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
03326 #define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
03327 #define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
03328 #define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
03329 #define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
03330 #define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
03331 #define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
03332 #define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
03333 #define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
03334 
03335 /******************  Bit definition for EXTI_SWIER register  ******************/
03336 #define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
03337 #define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
03338 #define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
03339 #define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
03340 #define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
03341 #define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
03342 #define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
03343 #define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
03344 #define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
03345 #define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
03346 #define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
03347 #define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
03348 #define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
03349 #define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
03350 #define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
03351 #define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
03352 #define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
03353 #define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
03354 #define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
03355 #define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
03356 
03357 /*******************  Bit definition for EXTI_PR register  ********************/
03358 #define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
03359 #define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
03360 #define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
03361 #define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
03362 #define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
03363 #define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
03364 #define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
03365 #define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
03366 #define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
03367 #define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
03368 #define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
03369 #define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
03370 #define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
03371 #define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
03372 #define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
03373 #define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
03374 #define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
03375 #define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
03376 #define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
03377 #define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
03378 
03379 /******************************************************************************/
03380 /*                                                                            */
03381 /*                             DMA Controller                                 */
03382 /*                                                                            */
03383 /******************************************************************************/
03384 
03385 /*******************  Bit definition for DMA_ISR register  ********************/
03386 #define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag */
03387 #define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag */
03388 #define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag */
03389 #define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag */
03390 #define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag */
03391 #define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag */
03392 #define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag */
03393 #define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag */
03394 #define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag */
03395 #define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag */
03396 #define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag */
03397 #define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag */
03398 #define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag */
03399 #define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag */
03400 #define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag */
03401 #define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag */
03402 #define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag */
03403 #define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag */
03404 #define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag */
03405 #define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag */
03406 #define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */
03407 #define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */
03408 #define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */
03409 #define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */
03410 #define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */
03411 #define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */
03412 #define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */
03413 #define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */
03414 
03415 /*******************  Bit definition for DMA_IFCR register  *******************/
03416 #define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clearr */
03417 #define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear */
03418 #define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear */
03419 #define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear */
03420 #define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear */
03421 #define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear */
03422 #define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear */
03423 #define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear */
03424 #define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear */
03425 #define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear */
03426 #define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear */
03427 #define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear */
03428 #define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear */
03429 #define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear */
03430 #define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear */
03431 #define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear */
03432 #define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear */
03433 #define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear */
03434 #define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear */
03435 #define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear */
03436 #define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */
03437 #define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */
03438 #define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */
03439 #define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */
03440 #define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */
03441 #define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */
03442 #define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */
03443 #define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */
03444 
03445 /*******************  Bit definition for DMA_CCR1 register  *******************/
03446 #define  DMA_CCR1_EN                         ((uint16_t)0x0001)            /*!< Channel enable*/
03447 #define  DMA_CCR1_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
03448 #define  DMA_CCR1_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
03449 #define  DMA_CCR1_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
03450 #define  DMA_CCR1_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
03451 #define  DMA_CCR1_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
03452 #define  DMA_CCR1_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
03453 #define  DMA_CCR1_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
03454 
03455 #define  DMA_CCR1_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
03456 #define  DMA_CCR1_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
03457 #define  DMA_CCR1_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
03458 
03459 #define  DMA_CCR1_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
03460 #define  DMA_CCR1_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
03461 #define  DMA_CCR1_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
03462 
03463 #define  DMA_CCR1_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits(Channel Priority level) */
03464 #define  DMA_CCR1_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
03465 #define  DMA_CCR1_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
03466 
03467 #define  DMA_CCR1_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
03468 
03469 /*******************  Bit definition for DMA_CCR2 register  *******************/
03470 #define  DMA_CCR2_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
03471 #define  DMA_CCR2_TCIE                       ((uint16_t)0x0002)            /*!< ransfer complete interrupt enable */
03472 #define  DMA_CCR2_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
03473 #define  DMA_CCR2_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
03474 #define  DMA_CCR2_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
03475 #define  DMA_CCR2_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
03476 #define  DMA_CCR2_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
03477 #define  DMA_CCR2_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
03478 
03479 #define  DMA_CCR2_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
03480 #define  DMA_CCR2_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
03481 #define  DMA_CCR2_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
03482 
03483 #define  DMA_CCR2_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
03484 #define  DMA_CCR2_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
03485 #define  DMA_CCR2_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
03486 
03487 #define  DMA_CCR2_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
03488 #define  DMA_CCR2_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
03489 #define  DMA_CCR2_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
03490 
03491 #define  DMA_CCR2_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
03492 
03493 /*******************  Bit definition for DMA_CCR3 register  *******************/
03494 #define  DMA_CCR3_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
03495 #define  DMA_CCR3_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
03496 #define  DMA_CCR3_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
03497 #define  DMA_CCR3_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
03498 #define  DMA_CCR3_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
03499 #define  DMA_CCR3_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
03500 #define  DMA_CCR3_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
03501 #define  DMA_CCR3_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
03502 
03503 #define  DMA_CCR3_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
03504 #define  DMA_CCR3_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
03505 #define  DMA_CCR3_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
03506 
03507 #define  DMA_CCR3_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
03508 #define  DMA_CCR3_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
03509 #define  DMA_CCR3_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
03510 
03511 #define  DMA_CCR3_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
03512 #define  DMA_CCR3_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
03513 #define  DMA_CCR3_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
03514 
03515 #define  DMA_CCR3_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
03516 
03517 /*!<******************  Bit definition for DMA_CCR4 register  *******************/
03518 #define  DMA_CCR4_EN                         ((uint16_t)0x0001)            /*!<Channel enable */
03519 #define  DMA_CCR4_TCIE                       ((uint16_t)0x0002)            /*!<Transfer complete interrupt enable */
03520 #define  DMA_CCR4_HTIE                       ((uint16_t)0x0004)            /*!<Half Transfer interrupt enable */
03521 #define  DMA_CCR4_TEIE                       ((uint16_t)0x0008)            /*!<Transfer error interrupt enable */
03522 #define  DMA_CCR4_DIR                        ((uint16_t)0x0010)            /*!<Data transfer direction */
03523 #define  DMA_CCR4_CIRC                       ((uint16_t)0x0020)            /*!<Circular mode */
03524 #define  DMA_CCR4_PINC                       ((uint16_t)0x0040)            /*!<Peripheral increment mode */
03525 #define  DMA_CCR4_MINC                       ((uint16_t)0x0080)            /*!<Memory increment mode */
03526 
03527 #define  DMA_CCR4_PSIZE                      ((uint16_t)0x0300)            /*!<PSIZE[1:0] bits (Peripheral size) */
03528 #define  DMA_CCR4_PSIZE_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
03529 #define  DMA_CCR4_PSIZE_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
03530 
03531 #define  DMA_CCR4_MSIZE                      ((uint16_t)0x0C00)            /*!<MSIZE[1:0] bits (Memory size) */
03532 #define  DMA_CCR4_MSIZE_0                    ((uint16_t)0x0400)            /*!<Bit 0 */
03533 #define  DMA_CCR4_MSIZE_1                    ((uint16_t)0x0800)            /*!<Bit 1 */
03534 
03535 #define  DMA_CCR4_PL                         ((uint16_t)0x3000)            /*!<PL[1:0] bits (Channel Priority level) */
03536 #define  DMA_CCR4_PL_0                       ((uint16_t)0x1000)            /*!<Bit 0 */
03537 #define  DMA_CCR4_PL_1                       ((uint16_t)0x2000)            /*!<Bit 1 */
03538 
03539 #define  DMA_CCR4_MEM2MEM                    ((uint16_t)0x4000)            /*!<Memory to memory mode */
03540 
03541 /******************  Bit definition for DMA_CCR5 register  *******************/
03542 #define  DMA_CCR5_EN                         ((uint16_t)0x0001)            /*!<Channel enable */
03543 #define  DMA_CCR5_TCIE                       ((uint16_t)0x0002)            /*!<Transfer complete interrupt enable */
03544 #define  DMA_CCR5_HTIE                       ((uint16_t)0x0004)            /*!<Half Transfer interrupt enable */
03545 #define  DMA_CCR5_TEIE                       ((uint16_t)0x0008)            /*!<Transfer error interrupt enable */
03546 #define  DMA_CCR5_DIR                        ((uint16_t)0x0010)            /*!<Data transfer direction */
03547 #define  DMA_CCR5_CIRC                       ((uint16_t)0x0020)            /*!<Circular mode */
03548 #define  DMA_CCR5_PINC                       ((uint16_t)0x0040)            /*!<Peripheral increment mode */
03549 #define  DMA_CCR5_MINC                       ((uint16_t)0x0080)            /*!<Memory increment mode */
03550 
03551 #define  DMA_CCR5_PSIZE                      ((uint16_t)0x0300)            /*!<PSIZE[1:0] bits (Peripheral size) */
03552 #define  DMA_CCR5_PSIZE_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
03553 #define  DMA_CCR5_PSIZE_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
03554 
03555 #define  DMA_CCR5_MSIZE                      ((uint16_t)0x0C00)            /*!<MSIZE[1:0] bits (Memory size) */
03556 #define  DMA_CCR5_MSIZE_0                    ((uint16_t)0x0400)            /*!<Bit 0 */
03557 #define  DMA_CCR5_MSIZE_1                    ((uint16_t)0x0800)            /*!<Bit 1 */
03558 
03559 #define  DMA_CCR5_PL                         ((uint16_t)0x3000)            /*!<PL[1:0] bits (Channel Priority level) */
03560 #define  DMA_CCR5_PL_0                       ((uint16_t)0x1000)            /*!<Bit 0 */
03561 #define  DMA_CCR5_PL_1                       ((uint16_t)0x2000)            /*!<Bit 1 */
03562 
03563 #define  DMA_CCR5_MEM2MEM                    ((uint16_t)0x4000)            /*!<Memory to memory mode enable */
03564 
03565 /*******************  Bit definition for DMA_CCR6 register  *******************/
03566 #define  DMA_CCR6_EN                         ((uint16_t)0x0001)            /*!<Channel enable */
03567 #define  DMA_CCR6_TCIE                       ((uint16_t)0x0002)            /*!<Transfer complete interrupt enable */
03568 #define  DMA_CCR6_HTIE                       ((uint16_t)0x0004)            /*!<Half Transfer interrupt enable */
03569 #define  DMA_CCR6_TEIE                       ((uint16_t)0x0008)            /*!<Transfer error interrupt enable */
03570 #define  DMA_CCR6_DIR                        ((uint16_t)0x0010)            /*!<Data transfer direction */
03571 #define  DMA_CCR6_CIRC                       ((uint16_t)0x0020)            /*!<Circular mode */
03572 #define  DMA_CCR6_PINC                       ((uint16_t)0x0040)            /*!<Peripheral increment mode */
03573 #define  DMA_CCR6_MINC                       ((uint16_t)0x0080)            /*!<Memory increment mode */
03574 
03575 #define  DMA_CCR6_PSIZE                      ((uint16_t)0x0300)            /*!<PSIZE[1:0] bits (Peripheral size) */
03576 #define  DMA_CCR6_PSIZE_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
03577 #define  DMA_CCR6_PSIZE_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
03578 
03579 #define  DMA_CCR6_MSIZE                      ((uint16_t)0x0C00)            /*!<MSIZE[1:0] bits (Memory size) */
03580 #define  DMA_CCR6_MSIZE_0                    ((uint16_t)0x0400)            /*!<Bit 0 */
03581 #define  DMA_CCR6_MSIZE_1                    ((uint16_t)0x0800)            /*!<Bit 1 */
03582 
03583 #define  DMA_CCR6_PL                         ((uint16_t)0x3000)            /*!<PL[1:0] bits (Channel Priority level) */
03584 #define  DMA_CCR6_PL_0                       ((uint16_t)0x1000)            /*!<Bit 0 */
03585 #define  DMA_CCR6_PL_1                       ((uint16_t)0x2000)            /*!<Bit 1 */
03586 
03587 #define  DMA_CCR6_MEM2MEM                    ((uint16_t)0x4000)            /*!<Memory to memory mode */
03588 
03589 /*******************  Bit definition for DMA_CCR7 register  *******************/
03590 #define  DMA_CCR7_EN                         ((uint16_t)0x0001)            /*!<Channel enable */
03591 #define  DMA_CCR7_TCIE                       ((uint16_t)0x0002)            /*!<Transfer complete interrupt enable */
03592 #define  DMA_CCR7_HTIE                       ((uint16_t)0x0004)            /*!<Half Transfer interrupt enable */
03593 #define  DMA_CCR7_TEIE                       ((uint16_t)0x0008)            /*!<Transfer error interrupt enable */
03594 #define  DMA_CCR7_DIR                        ((uint16_t)0x0010)            /*!<Data transfer direction */
03595 #define  DMA_CCR7_CIRC                       ((uint16_t)0x0020)            /*!<Circular mode */
03596 #define  DMA_CCR7_PINC                       ((uint16_t)0x0040)            /*!<Peripheral increment mode */
03597 #define  DMA_CCR7_MINC                       ((uint16_t)0x0080)            /*!<Memory increment mode */
03598 
03599 #define  DMA_CCR7_PSIZE            ,         ((uint16_t)0x0300)            /*!<PSIZE[1:0] bits (Peripheral size) */
03600 #define  DMA_CCR7_PSIZE_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
03601 #define  DMA_CCR7_PSIZE_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
03602 
03603 #define  DMA_CCR7_MSIZE                      ((uint16_t)0x0C00)            /*!<MSIZE[1:0] bits (Memory size) */
03604 #define  DMA_CCR7_MSIZE_0                    ((uint16_t)0x0400)            /*!<Bit 0 */
03605 #define  DMA_CCR7_MSIZE_1                    ((uint16_t)0x0800)            /*!<Bit 1 */
03606 
03607 #define  DMA_CCR7_PL                         ((uint16_t)0x3000)            /*!<PL[1:0] bits (Channel Priority level) */
03608 #define  DMA_CCR7_PL_0                       ((uint16_t)0x1000)            /*!<Bit 0 */
03609 #define  DMA_CCR7_PL_1                       ((uint16_t)0x2000)            /*!<Bit 1 */
03610 
03611 #define  DMA_CCR7_MEM2MEM                    ((uint16_t)0x4000)            /*!<Memory to memory mode enable */
03612 
03613 /******************  Bit definition for DMA_CNDTR1 register  ******************/
03614 #define  DMA_CNDTR1_NDT                      ((uint16_t)0xFFFF)            /*!<Number of data to Transfer */
03615 
03616 /******************  Bit definition for DMA_CNDTR2 register  ******************/
03617 #define  DMA_CNDTR2_NDT                      ((uint16_t)0xFFFF)            /*!<Number of data to Transfer */
03618 
03619 /******************  Bit definition for DMA_CNDTR3 register  ******************/
03620 #define  DMA_CNDTR3_NDT                      ((uint16_t)0xFFFF)            /*!<Number of data to Transfer */
03621 
03622 /******************  Bit definition for DMA_CNDTR4 register  ******************/
03623 #define  DMA_CNDTR4_NDT                      ((uint16_t)0xFFFF)            /*!<Number of data to Transfer */
03624 
03625 /******************  Bit definition for DMA_CNDTR5 register  ******************/
03626 #define  DMA_CNDTR5_NDT                      ((uint16_t)0xFFFF)            /*!<Number of data to Transfer */
03627 
03628 /******************  Bit definition for DMA_CNDTR6 register  ******************/
03629 #define  DMA_CNDTR6_NDT                      ((uint16_t)0xFFFF)            /*!<Number of data to Transfer */
03630 
03631 /******************  Bit definition for DMA_CNDTR7 register  ******************/
03632 #define  DMA_CNDTR7_NDT                      ((uint16_t)0xFFFF)            /*!<Number of data to Transfer */
03633 
03634 /******************  Bit definition for DMA_CPAR1 register  *******************/
03635 #define  DMA_CPAR1_PA                        ((uint32_t)0xFFFFFFFF)        /*!<Peripheral Address */
03636 
03637 /******************  Bit definition for DMA_CPAR2 register  *******************/
03638 #define  DMA_CPAR2_PA                        ((uint32_t)0xFFFFFFFF)        /*!<Peripheral Address */
03639 
03640 /******************  Bit definition for DMA_CPAR3 register  *******************/
03641 #define  DMA_CPAR3_PA                        ((uint32_t)0xFFFFFFFF)        /*!<Peripheral Address */
03642 
03643 
03644 /******************  Bit definition for DMA_CPAR4 register  *******************/
03645 #define  DMA_CPAR4_PA                        ((uint32_t)0xFFFFFFFF)        /*!<Peripheral Address */
03646 
03647 /******************  Bit definition for DMA_CPAR5 register  *******************/
03648 #define  DMA_CPAR5_PA                        ((uint32_t)0xFFFFFFFF)        /*!<Peripheral Address */
03649 
03650 /******************  Bit definition for DMA_CPAR6 register  *******************/
03651 #define  DMA_CPAR6_PA                        ((uint32_t)0xFFFFFFFF)        /*!<Peripheral Address */
03652 
03653 
03654 /******************  Bit definition for DMA_CPAR7 register  *******************/
03655 #define  DMA_CPAR7_PA                        ((uint32_t)0xFFFFFFFF)        /*!<Peripheral Address */
03656 
03657 /******************  Bit definition for DMA_CMAR1 register  *******************/
03658 #define  DMA_CMAR1_MA                        ((uint32_t)0xFFFFFFFF)        /*!<Memory Address */
03659 
03660 /******************  Bit definition for DMA_CMAR2 register  *******************/
03661 #define  DMA_CMAR2_MA                        ((uint32_t)0xFFFFFFFF)        /*!<Memory Address */
03662 
03663 /******************  Bit definition for DMA_CMAR3 register  *******************/
03664 #define  DMA_CMAR3_MA                        ((uint32_t)0xFFFFFFFF)        /*!<Memory Address */
03665 
03666 
03667 /******************  Bit definition for DMA_CMAR4 register  *******************/
03668 #define  DMA_CMAR4_MA                        ((uint32_t)0xFFFFFFFF)        /*!<Memory Address */
03669 
03670 /******************  Bit definition for DMA_CMAR5 register  *******************/
03671 #define  DMA_CMAR5_MA                        ((uint32_t)0xFFFFFFFF)        /*!<Memory Address */
03672 
03673 /******************  Bit definition for DMA_CMAR6 register  *******************/
03674 #define  DMA_CMAR6_MA                        ((uint32_t)0xFFFFFFFF)        /*!<Memory Address */
03675 
03676 /******************  Bit definition for DMA_CMAR7 register  *******************/
03677 #define  DMA_CMAR7_MA                        ((uint32_t)0xFFFFFFFF)        /*!<Memory Address */
03678 
03679 /******************************************************************************/
03680 /*                                                                            */
03681 /*                        Analog to Digital Converter                         */
03682 /*                                                                            */
03683 /******************************************************************************/
03684 
03685 /********************  Bit definition for ADC_SR register  ********************/
03686 #define  ADC_SR_AWD                          ((uint8_t)0x01)               /*!<Analog watchdog flag */
03687 #define  ADC_SR_EOC                          ((uint8_t)0x02)               /*!<End of conversion */
03688 #define  ADC_SR_JEOC                         ((uint8_t)0x04)               /*!<Injected channel end of conversion */
03689 #define  ADC_SR_JSTRT                        ((uint8_t)0x08)               /*!<Injected channel Start flag */
03690 #define  ADC_SR_STRT                         ((uint8_t)0x10)               /*!<Regular channel Start flag */
03691 
03692 /*******************  Bit definition for ADC_CR1 register  ********************/
03693 #define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
03694 #define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
03695 #define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
03696 #define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
03697 #define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
03698 #define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
03699 
03700 #define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!<Interrupt enable for EOC */
03701 #define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!<AAnalog Watchdog interrupt enable */
03702 #define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!<Interrupt enable for injected channels */
03703 #define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!<Scan mode */
03704 #define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!<Enable the watchdog on a single channel in scan mode */
03705 #define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!<Automatic injected group conversion */
03706 #define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!<Discontinuous mode on regular channels */
03707 #define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!<Discontinuous mode on injected channels */
03708 
03709 #define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
03710 #define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!<Bit 0 */
03711 #define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!<Bit 1 */
03712 #define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!<Bit 2 */
03713 
03714 #define  ADC_CR1_DUALMOD                     ((uint32_t)0x000F0000)        /*!<DUALMOD[3:0] bits (Dual mode selection) */
03715 #define  ADC_CR1_DUALMOD_0                   ((uint32_t)0x00010000)        /*!<Bit 0 */
03716 #define  ADC_CR1_DUALMOD_1                   ((uint32_t)0x00020000)        /*!<Bit 1 */
03717 #define  ADC_CR1_DUALMOD_2                   ((uint32_t)0x00040000)        /*!<Bit 2 */
03718 #define  ADC_CR1_DUALMOD_3                   ((uint32_t)0x00080000)        /*!<Bit 3 */
03719 
03720 #define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!<Analog watchdog enable on injected channels */
03721 #define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!<Analog watchdog enable on regular channels */
03722 
03723   
03724 /*******************  Bit definition for ADC_CR2 register  ********************/
03725 #define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!<A/D Converter ON / OFF */
03726 #define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!<Continuous Conversion */
03727 #define  ADC_CR2_CAL                         ((uint32_t)0x00000004)        /*!<A/D Calibration */
03728 #define  ADC_CR2_RSTCAL                      ((uint32_t)0x00000008)        /*!<Reset Calibration */
03729 #define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!<Direct Memory access mode */
03730 #define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!<Data Alignment */
03731 
03732 #define  ADC_CR2_JEXTSEL                     ((uint32_t)0x00007000)        /*!<JEXTSEL[2:0] bits (External event select for injected group) */
03733 #define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00001000)        /*!<Bit 0 */
03734 #define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00002000)        /*!<Bit 1 */
03735 #define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00004000)        /*!<Bit 2 */
03736 
03737 #define  ADC_CR2_JEXTTRIG                    ((uint32_t)0x00008000)        /*!<External Trigger Conversion mode for injected channels */
03738 
03739 #define  ADC_CR2_EXTSEL                      ((uint32_t)0x000E0000)        /*!<EXTSEL[2:0] bits (External Event Select for regular group) */
03740 #define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x00020000)        /*!<Bit 0 */
03741 #define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x00040000)        /*!<Bit 1 */
03742 #define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x00080000)        /*!<Bit 2 */
03743 
03744 #define  ADC_CR2_EXTTRIG                     ((uint32_t)0x00100000)        /*!<External Trigger Conversion mode for regular channels */
03745 #define  ADC_CR2_JSWSTART                    ((uint32_t)0x00200000)        /*!<Start Conversion of injected channels */
03746 #define  ADC_CR2_SWSTART                     ((uint32_t)0x00400000)        /*!<Start Conversion of regular channels */
03747 #define  ADC_CR2_TSVREFE                     ((uint32_t)0x00800000)        /*!<Temperature Sensor and VREFINT Enable */
03748 
03749 /******************  Bit definition for ADC_SMPR1 register  *******************/
03750 #define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
03751 #define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
03752 #define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
03753 #define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
03754 
03755 #define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
03756 #define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)        /*!<Bit 0 */
03757 #define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)        /*!<Bit 1 */
03758 #define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)        /*!<Bit 2 */
03759 
03760 #define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
03761 #define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)        /*!<Bit 0 */
03762 #define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)        /*!<Bit 1 */
03763 #define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)        /*!<Bit 2 */
03764 
03765 #define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
03766 #define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)        /*!<Bit 0 */
03767 #define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)        /*!<Bit 1 */
03768 #define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)        /*!<Bit 2 */
03769 
03770 #define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
03771 #define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)        /*!<Bit 0 */
03772 #define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)        /*!<Bit 1 */
03773 #define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)        /*!<Bit 2 */
03774 
03775 #define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
03776 #define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!<Bit 0 */
03777 #define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!<Bit 1 */
03778 #define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!<Bit 2 */
03779 
03780 #define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
03781 #define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!<Bit 0 */
03782 #define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!<Bit 1 */
03783 #define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!<Bit 2 */
03784 
03785 #define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
03786 #define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!<Bit 0 */
03787 #define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!<Bit 1 */
03788 #define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!<Bit 2 */
03789 
03790 /******************  Bit definition for ADC_SMPR2 register  *******************/
03791 #define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
03792 #define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!<Bit 0 */
03793 #define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!<Bit 1 */
03794 #define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!<Bit 2 */
03795 
03796 #define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
03797 #define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!<Bit 0 */
03798 #define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!<Bit 1 */
03799 #define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!<Bit 2 */
03800 
03801 #define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
03802 #define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!<Bit 0 */
03803 #define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!<Bit 1 */
03804 #define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!<Bit 2 */
03805 
03806 #define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
03807 #define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
03808 #define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
03809 #define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
03810 
03811 #define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
03812 #define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
03813 #define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
03814 #define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
03815 
03816 #define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
03817 #define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!<Bit 0 */
03818 #define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!<Bit 1 */
03819 #define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!<Bit 2 */
03820 
03821 #define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
03822 #define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!<Bit 0 */
03823 #define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!<Bit 1 */
03824 #define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!<Bit 2 */
03825 
03826 #define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
03827 #define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!<Bit 0 */
03828 #define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!<Bit 1 */
03829 #define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!<Bit 2 */
03830 
03831 #define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
03832 #define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
03833 #define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
03834 #define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
03835 
03836 #define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
03837 #define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!<Bit 0 */
03838 #define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!<Bit 1 */
03839 #define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!<Bit 2 */
03840 
03841 /******************  Bit definition for ADC_JOFR1 register  *******************/
03842 #define  ADC_JOFR1_JOFFSET1                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 1 */
03843 
03844 /******************  Bit definition for ADC_JOFR2 register  *******************/
03845 #define  ADC_JOFR2_JOFFSET2                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 2 */
03846 
03847 /******************  Bit definition for ADC_JOFR3 register  *******************/
03848 #define  ADC_JOFR3_JOFFSET3                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 3 */
03849 
03850 /******************  Bit definition for ADC_JOFR4 register  *******************/
03851 #define  ADC_JOFR4_JOFFSET4                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 4 */
03852 
03853 /*******************  Bit definition for ADC_HTR register  ********************/
03854 #define  ADC_HTR_HT                          ((uint16_t)0x0FFF)            /*!<Analog watchdog high threshold */
03855 
03856 /*******************  Bit definition for ADC_LTR register  ********************/
03857 #define  ADC_LTR_LT                          ((uint16_t)0x0FFF)            /*!<Analog watchdog low threshold */
03858 
03859 /*******************  Bit definition for ADC_SQR1 register  *******************/
03860 #define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
03861 #define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
03862 #define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
03863 #define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
03864 #define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
03865 #define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
03866 
03867 #define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
03868 #define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
03869 #define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
03870 #define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
03871 #define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
03872 #define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
03873 
03874 #define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
03875 #define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
03876 #define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
03877 #define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
03878 #define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
03879 #define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
03880 
03881 #define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
03882 #define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
03883 #define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
03884 #define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
03885 #define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
03886 #define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
03887 
03888 #define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!<L[3:0] bits (Regular channel sequence length) */
03889 #define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!<Bit 0 */
03890 #define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!<Bit 1 */
03891 #define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!<Bit 2 */
03892 #define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!<Bit 3 */
03893 
03894 /*******************  Bit definition for ADC_SQR2 register  *******************/
03895 #define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
03896 #define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
03897 #define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
03898 #define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
03899 #define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
03900 #define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
03901 
03902 #define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
03903 #define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
03904 #define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
03905 #define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
03906 #define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
03907 #define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
03908 
03909 #define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
03910 #define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
03911 #define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
03912 #define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
03913 #define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
03914 #define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
03915 
03916 #define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
03917 #define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
03918 #define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
03919 #define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
03920 #define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
03921 #define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
03922 
03923 #define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
03924 #define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!<Bit 0 */
03925 #define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!<Bit 1 */
03926 #define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!<Bit 2 */
03927 #define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!<Bit 3 */
03928 #define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!<Bit 4 */
03929 
03930 #define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
03931 #define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!<Bit 0 */
03932 #define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!<Bit 1 */
03933 #define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!<Bit 2 */
03934 #define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!<Bit 3 */
03935 #define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!<Bit 4 */
03936 
03937 /*******************  Bit definition for ADC_SQR3 register  *******************/
03938 #define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
03939 #define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
03940 #define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
03941 #define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
03942 #define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
03943 #define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
03944 
03945 #define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
03946 #define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
03947 #define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
03948 #define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
03949 #define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
03950 #define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
03951 
03952 #define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
03953 #define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
03954 #define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
03955 #define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
03956 #define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
03957 #define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
03958 
03959 #define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
03960 #define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!<Bit 0 */
03961 #define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!<Bit 1 */
03962 #define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!<Bit 2 */
03963 #define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!<Bit 3 */
03964 #define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!<Bit 4 */
03965 
03966 #define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
03967 #define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!<Bit 0 */
03968 #define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!<Bit 1 */
03969 #define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!<Bit 2 */
03970 #define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!<Bit 3 */
03971 #define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!<Bit 4 */
03972 
03973 #define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
03974 #define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!<Bit 0 */
03975 #define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!<Bit 1 */
03976 #define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!<Bit 2 */
03977 #define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!<Bit 3 */
03978 #define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!<Bit 4 */
03979 
03980 /*******************  Bit definition for ADC_JSQR register  *******************/
03981 #define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
03982 #define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
03983 #define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
03984 #define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
03985 #define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
03986 #define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
03987 
03988 #define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
03989 #define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
03990 #define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
03991 #define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
03992 #define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
03993 #define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
03994 
03995 #define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
03996 #define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
03997 #define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
03998 #define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
03999 #define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
04000 #define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
04001 
04002 #define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
04003 #define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
04004 #define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
04005 #define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
04006 #define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
04007 #define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
04008 
04009 #define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!<JL[1:0] bits (Injected Sequence length) */
04010 #define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!<Bit 0 */
04011 #define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!<Bit 1 */
04012 
04013 /*******************  Bit definition for ADC_JDR1 register  *******************/
04014 #define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
04015 
04016 /*******************  Bit definition for ADC_JDR2 register  *******************/
04017 #define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
04018 
04019 /*******************  Bit definition for ADC_JDR3 register  *******************/
04020 #define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
04021 
04022 /*******************  Bit definition for ADC_JDR4 register  *******************/
04023 #define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
04024 
04025 /********************  Bit definition for ADC_DR register  ********************/
04026 #define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!<Regular data */
04027 #define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000)        /*!<ADC2 data */
04028 
04029 /******************************************************************************/
04030 /*                                                                            */
04031 /*                      Digital to Analog Converter                           */
04032 /*                                                                            */
04033 /******************************************************************************/
04034 
04035 /********************  Bit definition for DAC_CR register  ********************/
04036 #define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */
04037 #define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */
04038 #define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */
04039 
04040 #define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
04041 #define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */
04042 #define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */
04043 #define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */
04044 
04045 #define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
04046 #define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!<Bit 0 */
04047 #define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!<Bit 1 */
04048 
04049 #define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
04050 #define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!<Bit 0 */
04051 #define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!<Bit 1 */
04052 #define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!<Bit 2 */
04053 #define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!<Bit 3 */
04054 
04055 #define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */
04056 #define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!<DAC channel2 enable */
04057 #define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!<DAC channel2 output buffer disable */
04058 #define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!<DAC channel2 Trigger enable */
04059 
04060 #define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
04061 #define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!<Bit 0 */
04062 #define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!<Bit 1 */
04063 #define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!<Bit 2 */
04064 
04065 #define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
04066 #define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!<Bit 0 */
04067 #define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!<Bit 1 */
04068 
04069 #define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
04070 #define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!<Bit 0 */
04071 #define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!<Bit 1 */
04072 #define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!<Bit 2 */
04073 #define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!<Bit 3 */
04074 
04075 #define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!<DAC channel2 DMA enabled */
04076 
04077 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
04078 #define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!<DAC channel1 software trigger */
04079 #define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!<DAC channel2 software trigger */
04080 
04081 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
04082 #define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!<DAC channel1 12-bit Right aligned data */
04083 
04084 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
04085 #define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!<DAC channel1 12-bit Left aligned data */
04086 
04087 /******************  Bit definition for DAC_DHR8R1 register  ******************/
04088 #define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!<DAC channel1 8-bit Right aligned data */
04089 
04090 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
04091 #define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!<DAC channel2 12-bit Right aligned data */
04092 
04093 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
04094 #define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!<DAC channel2 12-bit Left aligned data */
04095 
04096 /******************  Bit definition for DAC_DHR8R2 register  ******************/
04097 #define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!<DAC channel2 8-bit Right aligned data */
04098 
04099 /*****************  Bit definition for DAC_DHR12RD register  ******************/
04100 #define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
04101 #define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!<DAC channel2 12-bit Right aligned data */
04102 
04103 /*****************  Bit definition for DAC_DHR12LD register  ******************/
04104 #define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
04105 #define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!<DAC channel2 12-bit Left aligned data */
04106 
04107 /******************  Bit definition for DAC_DHR8RD register  ******************/
04108 #define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!<DAC channel1 8-bit Right aligned data */
04109 #define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!<DAC channel2 8-bit Right aligned data */
04110 
04111 /*******************  Bit definition for DAC_DOR1 register  *******************/
04112 #define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel1 data output */
04113 
04114 /*******************  Bit definition for DAC_DOR2 register  *******************/
04115 #define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel2 data output */
04116 
04117 /********************  Bit definition for DAC_SR register  ********************/
04118 #define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
04119 #define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun flag */
04120 
04121 /******************************************************************************/
04122 /*                                                                            */
04123 /*                                    CEC                                     */
04124 /*                                                                            */
04125 /******************************************************************************/
04126 /********************  Bit definition for CEC_CFGR register  ******************/
04127 #define  CEC_CFGR_PE              ((uint16_t)0x0001)     /*!< Peripheral Enable */
04128 #define  CEC_CFGR_IE              ((uint16_t)0x0002)     /*!< Interrupt Enable */
04129 #define  CEC_CFGR_BTEM            ((uint16_t)0x0004)     /*!< Bit Timing Error Mode */
04130 #define  CEC_CFGR_BPEM            ((uint16_t)0x0008)     /*!< Bit Period Error Mode */
04131 
04132 /********************  Bit definition for CEC_OAR register  ******************/
04133 #define  CEC_OAR_OA               ((uint16_t)0x000F)     /*!< OA[3:0]: Own Address */
04134 #define  CEC_OAR_OA_0             ((uint16_t)0x0001)     /*!< Bit 0 */
04135 #define  CEC_OAR_OA_1             ((uint16_t)0x0002)     /*!< Bit 1 */
04136 #define  CEC_OAR_OA_2             ((uint16_t)0x0004)     /*!< Bit 2 */
04137 #define  CEC_OAR_OA_3             ((uint16_t)0x0008)     /*!< Bit 3 */
04138 
04139 /********************  Bit definition for CEC_PRES register  ******************/
04140 #define  CEC_PRES_PRES            ((uint16_t)0x3FFF)   /*!< Prescaler Counter Value */
04141 
04142 /********************  Bit definition for CEC_ESR register  ******************/
04143 #define  CEC_ESR_BTE              ((uint16_t)0x0001)     /*!< Bit Timing Error */
04144 #define  CEC_ESR_BPE              ((uint16_t)0x0002)     /*!< Bit Period Error */
04145 #define  CEC_ESR_RBTFE            ((uint16_t)0x0004)     /*!< Rx Block Transfer Finished Error */
04146 #define  CEC_ESR_SBE              ((uint16_t)0x0008)     /*!< Start Bit Error */
04147 #define  CEC_ESR_ACKE             ((uint16_t)0x0010)     /*!< Block Acknowledge Error */
04148 #define  CEC_ESR_LINE             ((uint16_t)0x0020)     /*!< Line Error */
04149 #define  CEC_ESR_TBTFE            ((uint16_t)0x0040)     /*!< Tx Block Transfer Finsihed Error */
04150 
04151 /********************  Bit definition for CEC_CSR register  ******************/
04152 #define  CEC_CSR_TSOM             ((uint16_t)0x0001)     /*!< Tx Start Of Message */
04153 #define  CEC_CSR_TEOM             ((uint16_t)0x0002)     /*!< Tx End Of Message */
04154 #define  CEC_CSR_TERR             ((uint16_t)0x0004)     /*!< Tx Error */
04155 #define  CEC_CSR_TBTRF            ((uint16_t)0x0008)     /*!< Tx Byte Transfer Request or Block Transfer Finished */
04156 #define  CEC_CSR_RSOM             ((uint16_t)0x0010)     /*!< Rx Start Of Message */
04157 #define  CEC_CSR_REOM             ((uint16_t)0x0020)     /*!< Rx End Of Message */
04158 #define  CEC_CSR_RERR             ((uint16_t)0x0040)     /*!< Rx Error */
04159 #define  CEC_CSR_RBTF             ((uint16_t)0x0080)     /*!< Rx Block Transfer Finished */
04160 
04161 /********************  Bit definition for CEC_TXD register  ******************/
04162 #define  CEC_TXD_TXD              ((uint16_t)0x00FF)     /*!< Tx Data register */
04163 
04164 /********************  Bit definition for CEC_RXD register  ******************/
04165 #define  CEC_RXD_RXD              ((uint16_t)0x00FF)     /*!< Rx Data register */
04166 
04167 /******************************************************************************/
04168 /*                                                                            */
04169 /*                                    TIM                                     */
04170 /*                                                                            */
04171 /******************************************************************************/
04172 
04173 /*******************  Bit definition for TIM_CR1 register  ********************/
04174 #define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
04175 #define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
04176 #define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
04177 #define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
04178 #define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
04179 
04180 #define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
04181 #define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
04182 #define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
04183 
04184 #define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
04185 
04186 #define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
04187 #define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
04188 #define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
04189 
04190 /*******************  Bit definition for TIM_CR2 register  ********************/
04191 #define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control */
04192 #define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
04193 #define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */
04194 
04195 #define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
04196 #define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
04197 #define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
04198 #define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
04199 
04200 #define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
04201 #define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output) */
04202 #define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
04203 #define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output) */
04204 #define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
04205 #define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output) */
04206 #define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
04207 #define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output) */
04208 
04209 /*******************  Bit definition for TIM_SMCR register  *******************/
04210 #define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */
04211 #define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
04212 #define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
04213 #define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
04214 
04215 #define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */
04216 #define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
04217 #define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
04218 #define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
04219 
04220 #define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */
04221 
04222 #define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
04223 #define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
04224 #define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
04225 #define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
04226 #define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
04227 
04228 #define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
04229 #define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
04230 #define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
04231 
04232 #define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */
04233 #define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
04234 
04235 /*******************  Bit definition for TIM_DIER register  *******************/
04236 #define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
04237 #define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
04238 #define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
04239 #define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
04240 #define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
04241 #define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable */
04242 #define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
04243 #define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable */
04244 #define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
04245 #define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
04246 #define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
04247 #define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
04248 #define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
04249 #define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
04250 #define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
04251 
04252 /********************  Bit definition for TIM_SR register  ********************/
04253 #define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */
04254 #define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */
04255 #define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */
04256 #define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */
04257 #define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */
04258 #define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag */
04259 #define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */
04260 #define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag */
04261 #define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
04262 #define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
04263 #define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
04264 #define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
04265 
04266 /*******************  Bit definition for TIM_EGR register  ********************/
04267 #define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */
04268 #define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */
04269 #define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */
04270 #define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */
04271 #define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */
04272 #define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
04273 #define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */
04274 #define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation */
04275 
04276 /******************  Bit definition for TIM_CCMR1 register  *******************/
04277 #define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
04278 #define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
04279 #define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
04280 
04281 #define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */
04282 #define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */
04283 
04284 #define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
04285 #define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
04286 #define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
04287 #define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
04288 
04289 #define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */
04290 
04291 #define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
04292 #define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
04293 #define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
04294 
04295 #define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */
04296 #define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */
04297 
04298 #define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
04299 #define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
04300 #define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
04301 #define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
04302 
04303 #define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
04304 
04305 /*----------------------------------------------------------------------------*/
04306 
04307 #define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
04308 #define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
04309 #define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
04310 
04311 #define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
04312 #define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
04313 #define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
04314 #define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
04315 #define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
04316 
04317 #define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
04318 #define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
04319 #define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
04320 
04321 #define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
04322 #define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
04323 #define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
04324 #define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
04325 #define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
04326 
04327 /******************  Bit definition for TIM_CCMR2 register  *******************/
04328 #define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
04329 #define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
04330 #define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
04331 
04332 #define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */
04333 #define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */
04334 
04335 #define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
04336 #define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
04337 #define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
04338 #define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
04339 
04340 #define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
04341 
04342 #define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
04343 #define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
04344 #define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
04345 
04346 #define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */
04347 #define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
04348 
04349 #define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
04350 #define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
04351 #define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
04352 #define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
04353 
04354 #define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
04355 
04356 /*----------------------------------------------------------------------------*/
04357 
04358 #define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
04359 #define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
04360 #define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
04361 
04362 #define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
04363 #define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
04364 #define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
04365 #define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
04366 #define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
04367 
04368 #define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
04369 #define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
04370 #define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
04371 
04372 #define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
04373 #define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
04374 #define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
04375 #define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
04376 #define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
04377 
04378 /*******************  Bit definition for TIM_CCER register  *******************/
04379 #define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */
04380 #define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */
04381 #define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable */
04382 #define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
04383 #define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */
04384 #define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */
04385 #define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable */
04386 #define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
04387 #define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */
04388 #define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */
04389 #define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable */
04390 #define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
04391 #define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */
04392 #define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */
04393 #define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
04394 
04395 /*******************  Bit definition for TIM_CNT register  ********************/
04396 #define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */
04397 
04398 /*******************  Bit definition for TIM_PSC register  ********************/
04399 #define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
04400 
04401 /*******************  Bit definition for TIM_ARR register  ********************/
04402 #define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
04403 
04404 /*******************  Bit definition for TIM_RCR register  ********************/
04405 #define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
04406 
04407 /*******************  Bit definition for TIM_CCR1 register  *******************/
04408 #define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
04409 
04410 /*******************  Bit definition for TIM_CCR2 register  *******************/
04411 #define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
04412 
04413 /*******************  Bit definition for TIM_CCR3 register  *******************/
04414 #define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
04415 
04416 /*******************  Bit definition for TIM_CCR4 register  *******************/
04417 #define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
04418 
04419 /*******************  Bit definition for TIM_BDTR register  *******************/
04420 #define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
04421 #define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
04422 #define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
04423 #define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
04424 #define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
04425 #define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
04426 #define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
04427 #define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
04428 #define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */
04429 
04430 #define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
04431 #define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
04432 #define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */
04433 
04434 #define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
04435 #define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode */
04436 #define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable */
04437 #define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity */
04438 #define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable */
04439 #define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable */
04440 
04441 /*******************  Bit definition for TIM_DCR register  ********************/
04442 #define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
04443 #define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
04444 #define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
04445 #define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
04446 #define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
04447 #define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
04448 
04449 #define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
04450 #define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
04451 #define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
04452 #define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
04453 #define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
04454 #define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
04455 
04456 /*******************  Bit definition for TIM_DMAR register  *******************/
04457 #define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
04458 
04459 /******************************************************************************/
04460 /*                                                                            */
04461 /*                             Real-Time Clock                                */
04462 /*                                                                            */
04463 /******************************************************************************/
04464 
04465 /*******************  Bit definition for RTC_CRH register  ********************/
04466 #define  RTC_CRH_SECIE                       ((uint8_t)0x01)               /*!<Second Interrupt Enable */
04467 #define  RTC_CRH_ALRIE                       ((uint8_t)0x02)               /*!<Alarm Interrupt Enable */
04468 #define  RTC_CRH_OWIE                        ((uint8_t)0x04)               /*!<OverfloW Interrupt Enable */
04469 
04470 /*******************  Bit definition for RTC_CRL register  ********************/
04471 #define  RTC_CRL_SECF                        ((uint8_t)0x01)               /*!<Second Flag */
04472 #define  RTC_CRL_ALRF                        ((uint8_t)0x02)               /*!<Alarm Flag */
04473 #define  RTC_CRL_OWF                         ((uint8_t)0x04)               /*!<OverfloW Flag */
04474 #define  RTC_CRL_RSF                         ((uint8_t)0x08)               /*!<Registers Synchronized Flag */
04475 #define  RTC_CRL_CNF                         ((uint8_t)0x10)               /*!<Configuration Flag */
04476 #define  RTC_CRL_RTOFF                       ((uint8_t)0x20)               /*!<RTC operation OFF */
04477 
04478 /*******************  Bit definition for RTC_PRLH register  *******************/
04479 #define  RTC_PRLH_PRL                        ((uint16_t)0x000F)            /*!<RTC Prescaler Reload Value High */
04480 
04481 /*******************  Bit definition for RTC_PRLL register  *******************/
04482 #define  RTC_PRLL_PRL                        ((uint16_t)0xFFFF)            /*!<RTC Prescaler Reload Value Low */
04483 
04484 /*******************  Bit definition for RTC_DIVH register  *******************/
04485 #define  RTC_DIVH_RTC_DIV                    ((uint16_t)0x000F)            /*!<RTC Clock Divider High */
04486 
04487 /*******************  Bit definition for RTC_DIVL register  *******************/
04488 #define  RTC_DIVL_RTC_DIV                    ((uint16_t)0xFFFF)            /*!<RTC Clock Divider Low */
04489 
04490 /*******************  Bit definition for RTC_CNTH register  *******************/
04491 #define  RTC_CNTH_RTC_CNT                    ((uint16_t)0xFFFF)            /*!<RTC Counter High */
04492 
04493 /*******************  Bit definition for RTC_CNTL register  *******************/
04494 #define  RTC_CNTL_RTC_CNT                    ((uint16_t)0xFFFF)            /*!<RTC Counter Low */
04495 
04496 /*******************  Bit definition for RTC_ALRH register  *******************/
04497 #define  RTC_ALRH_RTC_ALR                    ((uint16_t)0xFFFF)            /*!<RTC Alarm High */
04498 
04499 /*******************  Bit definition for RTC_ALRL register  *******************/
04500 #define  RTC_ALRL_RTC_ALR                    ((uint16_t)0xFFFF)            /*!<RTC Alarm Low */
04501 
04502 /******************************************************************************/
04503 /*                                                                            */
04504 /*                           Independent WATCHDOG                             */
04505 /*                                                                            */
04506 /******************************************************************************/
04507 
04508 /*******************  Bit definition for IWDG_KR register  ********************/
04509 #define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!<Key value (write only, read 0000h) */
04510 
04511 /*******************  Bit definition for IWDG_PR register  ********************/
04512 #define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!<PR[2:0] (Prescaler divider) */
04513 #define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!<Bit 0 */
04514 #define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!<Bit 1 */
04515 #define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!<Bit 2 */
04516 
04517 /*******************  Bit definition for IWDG_RLR register  *******************/
04518 #define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!<Watchdog counter reload value */
04519 
04520 /*******************  Bit definition for IWDG_SR register  ********************/
04521 #define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!<Watchdog prescaler value update */
04522 #define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!<Watchdog counter reload value update */
04523 
04524 /******************************************************************************/
04525 /*                                                                            */
04526 /*                            Window WATCHDOG                                 */
04527 /*                                                                            */
04528 /******************************************************************************/
04529 
04530 /*******************  Bit definition for WWDG_CR register  ********************/
04531 #define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
04532 #define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!<Bit 0 */
04533 #define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!<Bit 1 */
04534 #define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!<Bit 2 */
04535 #define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!<Bit 3 */
04536 #define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!<Bit 4 */
04537 #define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!<Bit 5 */
04538 #define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!<Bit 6 */
04539 
04540 #define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!<Activation bit */
04541 
04542 /*******************  Bit definition for WWDG_CFR register  *******************/
04543 #define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!<W[6:0] bits (7-bit window value) */
04544 #define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!<Bit 0 */
04545 #define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!<Bit 1 */
04546 #define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!<Bit 2 */
04547 #define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!<Bit 3 */
04548 #define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!<Bit 4 */
04549 #define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!<Bit 5 */
04550 #define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!<Bit 6 */
04551 
04552 #define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!<WDGTB[1:0] bits (Timer Base) */
04553 #define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!<Bit 0 */
04554 #define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!<Bit 1 */
04555 
04556 #define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!<Early Wakeup Interrupt */
04557 
04558 /*******************  Bit definition for WWDG_SR register  ********************/
04559 #define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!<Early Wakeup Interrupt Flag */
04560 
04561 /******************************************************************************/
04562 /*                                                                            */
04563 /*                       Flexible Static Memory Controller                    */
04564 /*                                                                            */
04565 /******************************************************************************/
04566 
04567 /******************  Bit definition for FSMC_BCR1 register  *******************/
04568 #define  FSMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit */
04569 #define  FSMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit */
04570 
04571 #define  FSMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type) */
04572 #define  FSMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
04573 #define  FSMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
04574 
04575 #define  FSMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
04576 #define  FSMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
04577 #define  FSMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
04578 
04579 #define  FSMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable */
04580 #define  FSMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit */
04581 #define  FSMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit */
04582 #define  FSMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
04583 #define  FSMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration */
04584 #define  FSMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit */
04585 #define  FSMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit */
04586 #define  FSMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable */
04587 #define  FSMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!<Asynchronous wait */
04588 #define  FSMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable */
04589 
04590 /******************  Bit definition for FSMC_BCR2 register  *******************/
04591 #define  FSMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit */
04592 #define  FSMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit */
04593 
04594 #define  FSMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type) */
04595 #define  FSMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
04596 #define  FSMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
04597 
04598 #define  FSMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
04599 #define  FSMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
04600 #define  FSMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
04601 
04602 #define  FSMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable */
04603 #define  FSMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit */
04604 #define  FSMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit */
04605 #define  FSMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
04606 #define  FSMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration */
04607 #define  FSMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit */
04608 #define  FSMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit */
04609 #define  FSMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable */
04610 #define  FSMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!<Asynchronous wait */
04611 #define  FSMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable */
04612 
04613 /******************  Bit definition for FSMC_BCR3 register  *******************/
04614 #define  FSMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit */
04615 #define  FSMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit */
04616 
04617 #define  FSMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type) */
04618 #define  FSMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
04619 #define  FSMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
04620 
04621 #define  FSMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
04622 #define  FSMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
04623 #define  FSMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
04624 
04625 #define  FSMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable */
04626 #define  FSMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit */
04627 #define  FSMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit. */
04628 #define  FSMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
04629 #define  FSMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration */
04630 #define  FSMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit */
04631 #define  FSMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit */
04632 #define  FSMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable */
04633 #define  FSMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!<Asynchronous wait */
04634 #define  FSMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable */
04635 
04636 /******************  Bit definition for FSMC_BCR4 register  *******************/
04637 #define  FSMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit */
04638 #define  FSMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit */
04639 
04640 #define  FSMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type) */
04641 #define  FSMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
04642 #define  FSMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
04643 
04644 #define  FSMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
04645 #define  FSMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
04646 #define  FSMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
04647 
04648 #define  FSMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable */
04649 #define  FSMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit */
04650 #define  FSMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit */
04651 #define  FSMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
04652 #define  FSMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration */
04653 #define  FSMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit */
04654 #define  FSMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit */
04655 #define  FSMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable */
04656 #define  FSMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!<Asynchronous wait */
04657 #define  FSMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable */
04658 
04659 /******************  Bit definition for FSMC_BTR1 register  ******************/
04660 #define  FSMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
04661 #define  FSMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
04662 #define  FSMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
04663 #define  FSMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
04664 #define  FSMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
04665 
04666 #define  FSMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
04667 #define  FSMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
04668 #define  FSMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
04669 #define  FSMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
04670 #define  FSMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
04671 
04672 #define  FSMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
04673 #define  FSMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
04674 #define  FSMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
04675 #define  FSMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
04676 #define  FSMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
04677 
04678 #define  FSMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
04679 #define  FSMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
04680 #define  FSMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
04681 #define  FSMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
04682 #define  FSMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
04683 
04684 #define  FSMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
04685 #define  FSMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
04686 #define  FSMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
04687 #define  FSMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
04688 #define  FSMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
04689 
04690 #define  FSMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
04691 #define  FSMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
04692 #define  FSMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
04693 #define  FSMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
04694 #define  FSMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
04695 
04696 #define  FSMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
04697 #define  FSMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
04698 #define  FSMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
04699 
04700 /******************  Bit definition for FSMC_BTR2 register  *******************/
04701 #define  FSMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
04702 #define  FSMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
04703 #define  FSMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
04704 #define  FSMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
04705 #define  FSMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
04706 
04707 #define  FSMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
04708 #define  FSMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
04709 #define  FSMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
04710 #define  FSMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
04711 #define  FSMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
04712 
04713 #define  FSMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
04714 #define  FSMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
04715 #define  FSMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
04716 #define  FSMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
04717 #define  FSMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
04718 
04719 #define  FSMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
04720 #define  FSMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
04721 #define  FSMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
04722 #define  FSMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
04723 #define  FSMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
04724 
04725 #define  FSMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
04726 #define  FSMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
04727 #define  FSMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
04728 #define  FSMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
04729 #define  FSMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
04730 
04731 #define  FSMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
04732 #define  FSMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
04733 #define  FSMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
04734 #define  FSMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
04735 #define  FSMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
04736 
04737 #define  FSMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
04738 #define  FSMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
04739 #define  FSMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
04740 
04741 /*******************  Bit definition for FSMC_BTR3 register  *******************/
04742 #define  FSMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
04743 #define  FSMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
04744 #define  FSMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
04745 #define  FSMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
04746 #define  FSMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
04747 
04748 #define  FSMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
04749 #define  FSMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
04750 #define  FSMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
04751 #define  FSMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
04752 #define  FSMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
04753 
04754 #define  FSMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
04755 #define  FSMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
04756 #define  FSMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
04757 #define  FSMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
04758 #define  FSMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
04759 
04760 #define  FSMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
04761 #define  FSMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
04762 #define  FSMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
04763 #define  FSMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
04764 #define  FSMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
04765 
04766 #define  FSMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
04767 #define  FSMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
04768 #define  FSMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
04769 #define  FSMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
04770 #define  FSMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
04771 
04772 #define  FSMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
04773 #define  FSMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
04774 #define  FSMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
04775 #define  FSMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
04776 #define  FSMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
04777 
04778 #define  FSMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
04779 #define  FSMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
04780 #define  FSMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
04781 
04782 /******************  Bit definition for FSMC_BTR4 register  *******************/
04783 #define  FSMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
04784 #define  FSMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
04785 #define  FSMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
04786 #define  FSMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
04787 #define  FSMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
04788 
04789 #define  FSMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
04790 #define  FSMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
04791 #define  FSMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
04792 #define  FSMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
04793 #define  FSMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
04794 
04795 #define  FSMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
04796 #define  FSMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
04797 #define  FSMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
04798 #define  FSMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
04799 #define  FSMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
04800 
04801 #define  FSMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
04802 #define  FSMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
04803 #define  FSMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
04804 #define  FSMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
04805 #define  FSMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
04806 
04807 #define  FSMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
04808 #define  FSMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
04809 #define  FSMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
04810 #define  FSMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
04811 #define  FSMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
04812 
04813 #define  FSMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
04814 #define  FSMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
04815 #define  FSMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
04816 #define  FSMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
04817 #define  FSMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
04818 
04819 #define  FSMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
04820 #define  FSMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
04821 #define  FSMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
04822 
04823 /******************  Bit definition for FSMC_BWTR1 register  ******************/
04824 #define  FSMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
04825 #define  FSMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
04826 #define  FSMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
04827 #define  FSMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
04828 #define  FSMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
04829 
04830 #define  FSMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
04831 #define  FSMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
04832 #define  FSMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
04833 #define  FSMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
04834 #define  FSMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
04835 
04836 #define  FSMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
04837 #define  FSMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
04838 #define  FSMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
04839 #define  FSMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
04840 #define  FSMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
04841 
04842 #define  FSMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
04843 #define  FSMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
04844 #define  FSMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
04845 #define  FSMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
04846 #define  FSMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
04847 
04848 #define  FSMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
04849 #define  FSMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
04850 #define  FSMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
04851 #define  FSMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
04852 #define  FSMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
04853 
04854 #define  FSMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
04855 #define  FSMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
04856 #define  FSMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
04857 
04858 /******************  Bit definition for FSMC_BWTR2 register  ******************/
04859 #define  FSMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
04860 #define  FSMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
04861 #define  FSMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
04862 #define  FSMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
04863 #define  FSMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
04864 
04865 #define  FSMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
04866 #define  FSMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
04867 #define  FSMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
04868 #define  FSMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
04869 #define  FSMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
04870 
04871 #define  FSMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
04872 #define  FSMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
04873 #define  FSMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
04874 #define  FSMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
04875 #define  FSMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
04876 
04877 #define  FSMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
04878 #define  FSMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
04879 #define  FSMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1*/
04880 #define  FSMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
04881 #define  FSMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
04882 
04883 #define  FSMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
04884 #define  FSMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
04885 #define  FSMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
04886 #define  FSMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
04887 #define  FSMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
04888 
04889 #define  FSMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
04890 #define  FSMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
04891 #define  FSMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
04892 
04893 /******************  Bit definition for FSMC_BWTR3 register  ******************/
04894 #define  FSMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
04895 #define  FSMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
04896 #define  FSMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
04897 #define  FSMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
04898 #define  FSMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
04899 
04900 #define  FSMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
04901 #define  FSMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
04902 #define  FSMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
04903 #define  FSMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
04904 #define  FSMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
04905 
04906 #define  FSMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
04907 #define  FSMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
04908 #define  FSMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
04909 #define  FSMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
04910 #define  FSMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
04911 
04912 #define  FSMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
04913 #define  FSMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
04914 #define  FSMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
04915 #define  FSMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
04916 #define  FSMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
04917 
04918 #define  FSMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
04919 #define  FSMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
04920 #define  FSMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
04921 #define  FSMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
04922 #define  FSMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
04923 
04924 #define  FSMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
04925 #define  FSMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
04926 #define  FSMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
04927 
04928 /******************  Bit definition for FSMC_BWTR4 register  ******************/
04929 #define  FSMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
04930 #define  FSMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
04931 #define  FSMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
04932 #define  FSMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
04933 #define  FSMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
04934 
04935 #define  FSMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
04936 #define  FSMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
04937 #define  FSMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
04938 #define  FSMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
04939 #define  FSMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
04940 
04941 #define  FSMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
04942 #define  FSMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
04943 #define  FSMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
04944 #define  FSMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
04945 #define  FSMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
04946 
04947 #define  FSMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
04948 #define  FSMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
04949 #define  FSMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
04950 #define  FSMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
04951 #define  FSMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
04952 
04953 #define  FSMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
04954 #define  FSMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
04955 #define  FSMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
04956 #define  FSMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
04957 #define  FSMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
04958 
04959 #define  FSMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
04960 #define  FSMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
04961 #define  FSMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
04962 
04963 /******************  Bit definition for FSMC_PCR2 register  *******************/
04964 #define  FSMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
04965 #define  FSMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
04966 #define  FSMC_PCR2_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
04967 
04968 #define  FSMC_PCR2_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
04969 #define  FSMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
04970 #define  FSMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
04971 
04972 #define  FSMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
04973 
04974 #define  FSMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
04975 #define  FSMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
04976 #define  FSMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
04977 #define  FSMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
04978 #define  FSMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
04979 
04980 #define  FSMC_PCR2_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
04981 #define  FSMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
04982 #define  FSMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
04983 #define  FSMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
04984 #define  FSMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
04985 
04986 #define  FSMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[1:0] bits (ECC page size) */
04987 #define  FSMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
04988 #define  FSMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
04989 #define  FSMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
04990 
04991 /******************  Bit definition for FSMC_PCR3 register  *******************/
04992 #define  FSMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
04993 #define  FSMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
04994 #define  FSMC_PCR3_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
04995 
04996 #define  FSMC_PCR3_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
04997 #define  FSMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
04998 #define  FSMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
04999 
05000 #define  FSMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
05001 
05002 #define  FSMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
05003 #define  FSMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
05004 #define  FSMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
05005 #define  FSMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
05006 #define  FSMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
05007 
05008 #define  FSMC_PCR3_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
05009 #define  FSMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
05010 #define  FSMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
05011 #define  FSMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
05012 #define  FSMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
05013 
05014 #define  FSMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size) */
05015 #define  FSMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
05016 #define  FSMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
05017 #define  FSMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
05018 
05019 /******************  Bit definition for FSMC_PCR4 register  *******************/
05020 #define  FSMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
05021 #define  FSMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
05022 #define  FSMC_PCR4_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
05023 
05024 #define  FSMC_PCR4_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
05025 #define  FSMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
05026 #define  FSMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
05027 
05028 #define  FSMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
05029 
05030 #define  FSMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
05031 #define  FSMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
05032 #define  FSMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
05033 #define  FSMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
05034 #define  FSMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
05035 
05036 #define  FSMC_PCR4_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
05037 #define  FSMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
05038 #define  FSMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
05039 #define  FSMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
05040 #define  FSMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
05041 
05042 #define  FSMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size) */
05043 #define  FSMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
05044 #define  FSMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
05045 #define  FSMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
05046 
05047 /*******************  Bit definition for FSMC_SR2 register  *******************/
05048 #define  FSMC_SR2_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status */
05049 #define  FSMC_SR2_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status */
05050 #define  FSMC_SR2_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status */
05051 #define  FSMC_SR2_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit */
05052 #define  FSMC_SR2_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit */
05053 #define  FSMC_SR2_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
05054 #define  FSMC_SR2_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */
05055 
05056 /*******************  Bit definition for FSMC_SR3 register  *******************/
05057 #define  FSMC_SR3_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status */
05058 #define  FSMC_SR3_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status */
05059 #define  FSMC_SR3_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status */
05060 #define  FSMC_SR3_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit */
05061 #define  FSMC_SR3_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit */
05062 #define  FSMC_SR3_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
05063 #define  FSMC_SR3_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */
05064 
05065 /*******************  Bit definition for FSMC_SR4 register  *******************/
05066 #define  FSMC_SR4_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status */
05067 #define  FSMC_SR4_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status */
05068 #define  FSMC_SR4_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status */
05069 #define  FSMC_SR4_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit */