stm3210e_eval_fsmc_sram.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm3210e_eval_fsmc_sram.c
00004   * @author  MCD Application Team
00005   * @version V4.3.0
00006   * @date    10/15/2010
00007   * @brief   This file provides a set of functions needed to drive the 
00008   *          IS61WV51216BLL SRAM memory mounted on STM3210E-EVAL board.
00009   ******************************************************************************
00010   * @copy
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
00020   */ 
00021 
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm3210e_eval_fsmc_sram.h"
00024 
00025 /** @addtogroup Utilities
00026   * @{
00027   */
00028   
00029 /** @addtogroup STM32_EVAL
00030   * @{
00031   */ 
00032 
00033 /** @addtogroup STM3210E_EVAL
00034   * @{
00035   */
00036   
00037 /** @addtogroup STM3210E_EVAL_FSMC_SRAM
00038   * @brief      This file provides a set of functions needed to drive the 
00039   *             IS61WV51216BLL SRAM memory mounted on STM3210E-EVAL board.
00040   * @{
00041   */ 
00042 
00043 /** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Types
00044   * @{
00045   */ 
00046 /**
00047   * @}
00048   */ 
00049 
00050 
00051 /** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Defines
00052   * @{
00053   */ 
00054 /** 
00055   * @brief  FSMC Bank 1 NOR/SRAM3  
00056   */
00057 #define Bank1_SRAM3_ADDR    ((uint32_t)0x68000000)     
00058 /**
00059   * @}
00060   */ 
00061 
00062 
00063 /** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Macros
00064   * @{
00065   */
00066 /**
00067   * @}
00068   */ 
00069   
00070 
00071 /** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Variables
00072   * @{
00073   */ 
00074 /**
00075   * @}
00076   */ 
00077 
00078 
00079 /** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Function_Prototypes
00080   * @{
00081   */ 
00082 /**
00083   * @}
00084   */ 
00085 
00086 
00087 /** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Functions
00088   * @{
00089   */ 
00090 
00091 /**
00092   * @brief  Configures the FSMC and GPIOs to interface with the SRAM memory.
00093   *         This function must be called before any write/read operation
00094   *         on the SRAM.
00095   * @param  None 
00096   * @retval None
00097   */
00098 void SRAM_Init(void)
00099 {
00100   FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
00101   FSMC_NORSRAMTimingInitTypeDef  p;
00102   GPIO_InitTypeDef GPIO_InitStructure; 
00103   
00104   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE |
00105                          RCC_APB2Periph_GPIOF, ENABLE);
00106   
00107 /*-- GPIO Configuration ------------------------------------------------------*/
00108   /*!< SRAM Data lines configuration */
00109   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
00110                                 GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
00111   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00112   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00113   GPIO_Init(GPIOD, &GPIO_InitStructure); 
00114   
00115   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
00116                                 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | 
00117                                 GPIO_Pin_15;
00118   GPIO_Init(GPIOE, &GPIO_InitStructure);
00119   
00120   /*!< SRAM Address lines configuration */
00121   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | 
00122                                 GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | 
00123                                 GPIO_Pin_14 | GPIO_Pin_15;
00124   GPIO_Init(GPIOF, &GPIO_InitStructure);
00125   
00126   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | 
00127                                 GPIO_Pin_4 | GPIO_Pin_5;
00128   GPIO_Init(GPIOG, &GPIO_InitStructure);
00129   
00130   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13; 
00131   GPIO_Init(GPIOD, &GPIO_InitStructure);
00132    
00133   /*!< NOE and NWE configuration */  
00134   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 |GPIO_Pin_5;
00135   GPIO_Init(GPIOD, &GPIO_InitStructure);
00136   
00137   /*!< NE3 configuration */
00138   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; 
00139   GPIO_Init(GPIOG, &GPIO_InitStructure);
00140   
00141   /*!< NBL0, NBL1 configuration */
00142   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1; 
00143   GPIO_Init(GPIOE, &GPIO_InitStructure); 
00144   
00145 /*-- FSMC Configuration ------------------------------------------------------*/
00146   p.FSMC_AddressSetupTime = 0;
00147   p.FSMC_AddressHoldTime = 0;
00148   p.FSMC_DataSetupTime = 1;
00149   p.FSMC_BusTurnAroundDuration = 0;
00150   p.FSMC_CLKDivision = 0;
00151   p.FSMC_DataLatency = 0;
00152   p.FSMC_AccessMode = FSMC_AccessMode_A;
00153 
00154   FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
00155   FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
00156   FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
00157   FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
00158   FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
00159   FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;  
00160   FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
00161   FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
00162   FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
00163   FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
00164   FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
00165   FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
00166   FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
00167   FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
00168   FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
00169 
00170   FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 
00171 
00172   /*!< Enable FSMC Bank1_SRAM Bank */
00173   FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);  
00174 }
00175 
00176 /**
00177   * @brief  Writes a Half-word buffer to the FSMC SRAM memory. 
00178   * @param  pBuffer : pointer to buffer. 
00179   * @param  WriteAddr : SRAM memory internal address from which the data will be 
00180   *         written.
00181   * @param  NumHalfwordToWrite : number of half-words to write. 
00182   * @retval None
00183   */
00184 void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
00185 {
00186   for(; NumHalfwordToWrite != 0; NumHalfwordToWrite--) /*!< while there is data to write */
00187   {
00188     /*!< Transfer data to the memory */
00189     *(uint16_t *) (Bank1_SRAM3_ADDR + WriteAddr) = *pBuffer++;
00190     
00191     /*!< Increment the address*/  
00192     WriteAddr += 2;
00193   }   
00194 }
00195 
00196 /**
00197   * @brief  Reads a block of data from the FSMC SRAM memory.
00198   * @param  pBuffer : pointer to the buffer that receives the data read from the 
00199   *         SRAM memory.
00200   * @param  ReadAddr : SRAM memory internal address to read from.
00201   * @param  NumHalfwordToRead : number of half-words to read.
00202   * @retval None
00203   */
00204 void SRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
00205 {
00206   for(; NumHalfwordToRead != 0; NumHalfwordToRead--) /*!< while there is data to read */
00207   {
00208     /*!< Read a half-word from the memory */
00209     *pBuffer++ = *(__IO uint16_t*) (Bank1_SRAM3_ADDR + ReadAddr);
00210 
00211     /*!< Increment the address*/  
00212     ReadAddr += 2;
00213   }  
00214 }
00215 
00216 /**
00217   * @}
00218   */
00219 
00220 /**
00221   * @}
00222   */
00223 
00224 /**
00225   * @}
00226   */
00227 
00228 /**
00229   * @}
00230   */
00231 
00232 /**
00233   * @}
00234   */  
00235 
00236 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
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