stm3210e_eval_fsmc_nand.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm3210e_eval_fsmc_nand.c
00004   * @author  MCD Application Team
00005   * @version V4.3.0
00006   * @date    10/15/2010
00007   * @brief   This file provides a set of functions needed to drive the
00008   *          NAND512W3A2 memory mounted on STM3210E-EVAL board.
00009   ******************************************************************************
00010   * @copy
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
00020   */ 
00021 
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm3210e_eval_fsmc_nand.h"
00024 
00025 /** @addtogroup Utilities
00026   * @{
00027   */
00028   
00029 /** @addtogroup STM32_EVAL
00030   * @{
00031   */ 
00032 
00033 /** @addtogroup STM3210E_EVAL
00034   * @{
00035   */
00036   
00037 /** @addtogroup STM3210E_EVAL_FSMC_NAND
00038   * @brief      This file provides a set of functions needed to drive the
00039   *             NAND512W3A2 memory mounted on STM3210E-EVAL board.
00040   * @{
00041   */ 
00042 
00043 /** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Types
00044   * @{
00045   */ 
00046 /**
00047   * @}
00048   */ 
00049 
00050 
00051 /** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Defines
00052   * @{
00053   */ 
00054 /** 
00055   * @brief  FSMC Bank 2 
00056   */
00057 #define FSMC_Bank_NAND     FSMC_Bank2_NAND
00058 #define Bank_NAND_ADDR     Bank2_NAND_ADDR 
00059 #define Bank2_NAND_ADDR    ((uint32_t)0x70000000)     
00060 /**
00061   * @}
00062   */ 
00063 
00064 /** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Macros
00065   * @{
00066   */
00067 #define ROW_ADDRESS (Address.Page + (Address.Block + (Address.Zone * NAND_ZONE_SIZE)) * NAND_BLOCK_SIZE)  
00068 /**
00069   * @}
00070   */ 
00071   
00072 
00073 /** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Variables
00074   * @{
00075   */ 
00076 /**
00077   * @}
00078   */ 
00079 
00080 
00081 /** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Function_Prototypes
00082   * @{
00083   */ 
00084 /**
00085   * @}
00086   */ 
00087 
00088 
00089 /** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Functions
00090   * @{
00091   */ 
00092 
00093 /**
00094   * @brief  Configures the FSMC and GPIOs to interface with the NAND memory.
00095   *         This function must be called before any write/read operation on the 
00096   *         NAND.
00097   * @param  None
00098   * @retval None
00099   */
00100 void NAND_Init(void)
00101 {
00102   GPIO_InitTypeDef GPIO_InitStructure; 
00103   FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
00104   FSMC_NAND_PCCARDTimingInitTypeDef  p;
00105   
00106   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | 
00107                          RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
00108   
00109 /*-- GPIO Configuration ------------------------------------------------------*/
00110 /*!< CLE, ALE, D0->D3, NOE, NWE and NCE2  NAND pin configuration  */
00111   GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_14 | GPIO_Pin_15 |  
00112                                  GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | 
00113                                  GPIO_Pin_7;
00114   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00115   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00116 
00117   GPIO_Init(GPIOD, &GPIO_InitStructure); 
00118 
00119 /*!< D4->D7 NAND pin configuration  */  
00120   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
00121 
00122   GPIO_Init(GPIOE, &GPIO_InitStructure);
00123 
00124 
00125 /*!< NWAIT NAND pin configuration */
00126   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
00127   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00128   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
00129 
00130   GPIO_Init(GPIOD, &GPIO_InitStructure); 
00131 
00132 /*!< INT2 NAND pin configuration */  
00133   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
00134   GPIO_Init(GPIOG, &GPIO_InitStructure);
00135 
00136   /*-- FSMC Configuration ------------------------------------------------------*/
00137   p.FSMC_SetupTime = 0x0;
00138   p.FSMC_WaitSetupTime = 0x2;
00139   p.FSMC_HoldSetupTime = 0x1;
00140   p.FSMC_HiZSetupTime = 0x0;
00141 
00142   FSMC_NANDInitStructure.FSMC_Bank = FSMC_Bank2_NAND;
00143   FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Enable;
00144   FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
00145   FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Enable;
00146   FSMC_NANDInitStructure.FSMC_ECCPageSize = FSMC_ECCPageSize_512Bytes;
00147   FSMC_NANDInitStructure.FSMC_TCLRSetupTime = 0x00;
00148   FSMC_NANDInitStructure.FSMC_TARSetupTime = 0x00;
00149   FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &p;
00150   FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &p;
00151 
00152   FSMC_NANDInit(&FSMC_NANDInitStructure);
00153 
00154   /*!< FSMC NAND Bank Cmd Test */
00155   FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE);
00156 }
00157 
00158 /**
00159   * @brief  Reads NAND memory's ID.
00160   * @param  NAND_ID: pointer to a NAND_IDTypeDef structure which will hold
00161   *         the Manufacturer and Device ID.  
00162   * @retval None
00163   */
00164 void NAND_ReadID(NAND_IDTypeDef* NAND_ID)
00165 {
00166   uint32_t data = 0;
00167 
00168   /*!< Send Command to the command area */
00169   *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = 0x90;
00170   *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
00171 
00172    /*!< Sequence to read ID from NAND flash */
00173    data = *(__IO uint32_t *)(Bank_NAND_ADDR | DATA_AREA);
00174 
00175    NAND_ID->Maker_ID   = ADDR_1st_CYCLE (data);
00176    NAND_ID->Device_ID  = ADDR_2nd_CYCLE (data);
00177    NAND_ID->Third_ID   = ADDR_3rd_CYCLE (data);
00178    NAND_ID->Fourth_ID  = ADDR_4th_CYCLE (data);
00179 }
00180 
00181 /**
00182   * @brief  This routine is for writing one or several 512 Bytes Page size.
00183   * @param  pBuffer: pointer on the Buffer containing data to be written 
00184   * @param  Address: First page address
00185   * @param  NumPageToWrite: Number of page to write  
00186   * @retval New status of the NAND operation. This parameter can be:
00187   *              - NAND_TIMEOUT_ERROR: when the previous operation generate 
00188   *                a Timeout error
00189   *              - NAND_READY: when memory is ready for the next operation 
00190   *                And the new status of the increment address operation. It can be:
00191   *              - NAND_VALID_ADDRESS: When the new address is valid address
00192   *              - NAND_INVALID_ADDRESS: When the new address is invalid address  
00193   */
00194 uint32_t NAND_WriteSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToWrite)
00195 {
00196   uint32_t index = 0x00, numpagewritten = 0x00, addressstatus = NAND_VALID_ADDRESS;
00197   uint32_t status = NAND_READY, size = 0x00;
00198 
00199   while((NumPageToWrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY))
00200   {
00201     /*!< Page write command and address */
00202     *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A;
00203     *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
00204 
00205     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
00206     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
00207     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
00208     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
00209 
00210     /*!< Calculate the size */
00211     size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpagewritten);
00212 
00213     /*!< Write data */
00214     for(; index < size; index++)
00215     {
00216       *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index];
00217     }
00218     
00219     *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
00220 
00221     /*!< Check status for successful operation */
00222     status = NAND_GetStatus();
00223     
00224     if(status == NAND_READY)
00225     {
00226       numpagewritten++;
00227 
00228       NumPageToWrite--;
00229 
00230       /*!< Calculate Next small page Address */
00231       addressstatus = NAND_AddressIncrement(&Address);
00232     }
00233   }
00234   
00235   return (status | addressstatus);
00236 }
00237 
00238 /**
00239   * @brief  This routine is for sequential read from one or several 512 Bytes Page size.
00240   * @param  pBuffer: pointer on the Buffer to fill
00241   * @param  Address: First page address
00242   * @param  NumPageToRead: Number of page to read  
00243   * @retval New status of the NAND operation. This parameter can be:
00244   *              - NAND_TIMEOUT_ERROR: when the previous operation generate 
00245   *                a Timeout error
00246   *              - NAND_READY: when memory is ready for the next operation 
00247   *                And the new status of the increment address operation. It can be:
00248   *              - NAND_VALID_ADDRESS: When the new address is valid address
00249   *              - NAND_INVALID_ADDRESS: When the new address is invalid address
00250   */
00251 uint32_t NAND_ReadSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToRead)
00252 {
00253   uint32_t index = 0x00, numpageread = 0x00, addressstatus = NAND_VALID_ADDRESS;
00254   uint32_t status = NAND_READY, size = 0x00;
00255 
00256   while((NumPageToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS))
00257   {
00258     /*!< Page Read command and page address */
00259     *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A;
00260    
00261     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00; 
00262     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
00263     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
00264     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
00265     
00266     /*!< Calculate the size */
00267     size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpageread);
00268     
00269     /*!< Get Data into Buffer */    
00270     for(; index < size; index++)
00271     {
00272       pBuffer[index]= *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA);
00273     }
00274 
00275     numpageread++;
00276     
00277     NumPageToRead--;
00278 
00279     /*!< Calculate page address */
00280     addressstatus = NAND_AddressIncrement(&Address);
00281   }
00282 
00283   status = NAND_GetStatus();
00284   
00285   return (status | addressstatus);
00286 }
00287 
00288 /**
00289   * @brief  This routine write the spare area information for the specified
00290   *         pages addresses.  
00291   * @param  pBuffer: pointer on the Buffer containing data to be written 
00292   * @param  Address: First page address
00293   * @param  NumSpareAreaTowrite: Number of Spare Area to write
00294   * @retval New status of the NAND operation. This parameter can be:
00295   *              - NAND_TIMEOUT_ERROR: when the previous operation generate 
00296   *                a Timeout error
00297   *              - NAND_READY: when memory is ready for the next operation 
00298   *                And the new status of the increment address operation. It can be:
00299   *              - NAND_VALID_ADDRESS: When the new address is valid address
00300   *              - NAND_INVALID_ADDRESS: When the new address is invalid address
00301   */
00302 uint32_t NAND_WriteSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaTowrite)
00303 {
00304   uint32_t index = 0x00, numsparesreawritten = 0x00, addressstatus = NAND_VALID_ADDRESS;
00305   uint32_t status = NAND_READY, size = 0x00; 
00306 
00307   while((NumSpareAreaTowrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY))
00308   {
00309     /*!< Page write Spare area command and address */
00310     *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C;
00311     *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
00312 
00313     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00; 
00314     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
00315     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
00316     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
00317 
00318     /*!< Calculate the size */ 
00319     size = NAND_SPARE_AREA_SIZE + (NAND_SPARE_AREA_SIZE * numsparesreawritten);
00320 
00321     /*!< Write the data */ 
00322     for(; index < size; index++)
00323     {
00324       *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index];
00325     }
00326     
00327     *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
00328 
00329     /*!< Check status for successful operation */
00330     status = NAND_GetStatus();
00331 
00332     if(status == NAND_READY)
00333     {
00334       numsparesreawritten++;
00335 
00336       NumSpareAreaTowrite--;
00337     
00338       /*!< Calculate Next page Address */
00339       addressstatus = NAND_AddressIncrement(&Address);
00340     }
00341   }
00342   
00343   return (status | addressstatus);
00344 }
00345 
00346 /**
00347   * @brief  This routine read the spare area information from the specified
00348   *         pages addresses.  
00349   * @param  pBuffer: pointer on the Buffer to fill 
00350   * @param  Address: First page address
00351   * @param  NumSpareAreaToRead: Number of Spare Area to read
00352   * @retval New status of the NAND operation. This parameter can be:
00353   *              - NAND_TIMEOUT_ERROR: when the previous operation generate 
00354   *                a Timeout error
00355   *              - NAND_READY: when memory is ready for the next operation 
00356   *                And the new status of the increment address operation. It can be:
00357   *              - NAND_VALID_ADDRESS: When the new address is valid address
00358   *              - NAND_INVALID_ADDRESS: When the new address is invalid address
00359   */
00360 uint32_t NAND_ReadSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaToRead)
00361 {
00362   uint32_t numsparearearead = 0x00, index = 0x00, addressstatus = NAND_VALID_ADDRESS;
00363   uint32_t status = NAND_READY, size = 0x00;
00364 
00365   while((NumSpareAreaToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS))
00366   {     
00367     /*!< Page Read command and page address */
00368     *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C;
00369 
00370     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00; 
00371     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
00372     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
00373     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
00374 
00375     /*!< Data Read */
00376     size = NAND_SPARE_AREA_SIZE +  (NAND_SPARE_AREA_SIZE * numsparearearead);
00377 
00378     /*!< Get Data into Buffer */
00379     for ( ;index < size; index++)
00380     {
00381       pBuffer[index] = *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA);
00382     }
00383     
00384     numsparearearead++;
00385     
00386     NumSpareAreaToRead--;
00387 
00388     /*!< Calculate page address */
00389     addressstatus = NAND_AddressIncrement(&Address);
00390   }
00391 
00392   status = NAND_GetStatus();
00393 
00394   return (status | addressstatus);
00395 }
00396 
00397 /**
00398   * @brief  This routine erase complete block from NAND FLASH
00399   * @param  Address: Any address into block to be erased
00400   * @retval New status of the NAND operation. This parameter can be:
00401   *              - NAND_TIMEOUT_ERROR: when the previous operation generate 
00402   *                a Timeout error
00403   *              - NAND_READY: when memory is ready for the next operation 
00404   */
00405 uint32_t NAND_EraseBlock(NAND_ADDRESS Address)
00406 {
00407   *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE0;
00408 
00409   *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
00410   *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
00411   *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
00412 
00413   *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE1; 
00414 
00415   return (NAND_GetStatus());
00416 }
00417 
00418 /**
00419   * @brief  This routine reset the NAND FLASH.
00420   * @param  None
00421   * @retval NAND_READY
00422   */
00423 uint32_t NAND_Reset(void)
00424 {
00425   *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_RESET;
00426 
00427   return (NAND_READY);
00428 }
00429 
00430 /**
00431   * @brief  Get the NAND operation status.
00432   * @param  None
00433   * @retval New status of the NAND operation. This parameter can be:
00434   *              - NAND_TIMEOUT_ERROR: when the previous operation generate
00435   *                a Timeout error
00436   *              - NAND_READY: when memory is ready for the next operation
00437   */
00438 uint32_t NAND_GetStatus(void)
00439 {
00440   uint32_t timeout = 0x1000000, status = NAND_READY;
00441 
00442   status = NAND_ReadStatus();
00443 
00444   /*!< Wait for a NAND operation to complete or a TIMEOUT to occur */
00445   while ((status != NAND_READY) &&( timeout != 0x00))
00446   {
00447      status = NAND_ReadStatus();
00448      timeout --;
00449   }
00450 
00451   if(timeout == 0x00)
00452   {
00453     status =  NAND_TIMEOUT_ERROR;
00454   }
00455 
00456   /*!< Return the operation status */
00457   return (status);
00458 }
00459   
00460 /**
00461   * @brief  Reads the NAND memory status using the Read status command. 
00462   * @param  None
00463   * @retval The status of the NAND memory. This parameter can be:
00464   *              - NAND_BUSY: when memory is busy
00465   *              - NAND_READY: when memory is ready for the next operation
00466   *              - NAND_ERROR: when the previous operation gererates error
00467   */
00468 uint32_t NAND_ReadStatus(void)
00469 {
00470   uint32_t data = 0x00, status = NAND_BUSY;
00471 
00472   /*!< Read status operation ------------------------------------ */
00473   *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_STATUS;
00474   data = *(__IO uint8_t *)(Bank_NAND_ADDR);
00475 
00476   if((data & NAND_ERROR) == NAND_ERROR)
00477   {
00478     status = NAND_ERROR;
00479   } 
00480   else if((data & NAND_READY) == NAND_READY)
00481   {
00482     status = NAND_READY;
00483   }
00484   else
00485   {
00486     status = NAND_BUSY; 
00487   }
00488   
00489   return (status);
00490 }
00491 
00492 /**
00493   * @brief  Increment the NAND memory address. 
00494   * @param  Address: address to be incremented.
00495   * @retval The new status of the increment address operation. It can be:
00496   *              - NAND_VALID_ADDRESS: When the new address is valid address
00497   *              - NAND_INVALID_ADDRESS: When the new address is invalid address   
00498   */
00499 uint32_t NAND_AddressIncrement(NAND_ADDRESS* Address)
00500 {
00501   uint32_t status = NAND_VALID_ADDRESS;
00502  
00503   Address->Page++;
00504 
00505   if(Address->Page == NAND_BLOCK_SIZE)
00506   {
00507     Address->Page = 0;
00508     Address->Block++;
00509     
00510     if(Address->Block == NAND_ZONE_SIZE)
00511     {
00512       Address->Block = 0;
00513       Address->Zone++;
00514 
00515       if(Address->Zone == NAND_MAX_ZONE)
00516       {
00517         status = NAND_INVALID_ADDRESS;
00518       }
00519     }
00520   } 
00521   
00522   return (status);
00523 }
00524 
00525 /**
00526   * @}
00527   */
00528 
00529 /**
00530   * @}
00531   */
00532 
00533 /**
00534   * @}
00535   */
00536 
00537 /**
00538   * @}
00539   */
00540 
00541 /**
00542   * @}
00543   */  
00544 
00545 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
STM32F10x Standard Peripherals Library: Footer

 

 

 

      For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit  www.st.com/STM32