stm32100e_eval_fsmc_onenand.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32100e_eval_fsmc_onenand.c
00004   * @author  MCD Application Team
00005   * @version V4.3.0
00006   * @date    10/15/2010
00007   * @brief   This file provides a set of functions needed to drive the
00008   *          KFG1216x2A-xxB5 OneNAND memory mounted on STM32100E-EVAL board.
00009   ******************************************************************************
00010   * @copy
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
00020   */ 
00021 
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32100e_eval_fsmc_onenand.h"
00024 
00025 /** @addtogroup Utilities
00026   * @{
00027   */
00028   
00029 /** @addtogroup STM32_EVAL
00030   * @{
00031   */ 
00032 
00033 /** @addtogroup STM32100E_EVAL
00034   * @{
00035   */
00036   
00037 /** @addtogroup STM32100E_EVAL_FSMC_ONENAND
00038   * @brief      This file provides a set of functions needed to drive the
00039   *             KFG1216x2A-xxB5 OneNAND memory mounted on STM32100E-EVAL board.
00040   * @{
00041   */ 
00042 
00043 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Types
00044   * @{
00045   */ 
00046 /**
00047   * @}
00048   */ 
00049 
00050 
00051 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Defines
00052   * @{
00053   */ 
00054 #define Bank1_NOR1_ADDR               ((uint32_t)0x60000000)
00055 #define ONENAND_BOOTPARTITION_ADDR    ((uint32_t)Bank1_NOR1_ADDR)
00056 
00057  
00058 /**
00059   * @}
00060   */ 
00061 
00062 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Macros
00063   * @{
00064   */
00065 #define ADDR_SHIFT(A) (Bank1_NOR1_ADDR + (2 * (A)))
00066 #define OneNAND_WRITE(Address, Data)  (*(__IO uint16_t *)(Address) = (Data))
00067   
00068 /**
00069   * @}
00070   */ 
00071   
00072 
00073 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Variables
00074   * @{
00075   */ 
00076 /**
00077   * @}
00078   */ 
00079 
00080 
00081 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Function_Prototypes
00082   * @{
00083   */ 
00084 /**
00085   * @}
00086   */ 
00087 
00088 
00089 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Functions
00090   * @{
00091   */ 
00092 
00093 /**
00094   * @brief  Configures the FSMC and GPIOs to interface with the OneNAND memory.
00095   *         This function must be called before any write/read operation on the 
00096   *         OneNAND.
00097   * @param  None
00098   * @retval None
00099   */
00100 void OneNAND_Init(void)
00101 {
00102   FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
00103   FSMC_NORSRAMTimingInitTypeDef  p;
00104   GPIO_InitTypeDef GPIO_InitStructure;
00105 
00106 
00107   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE); 
00108   
00109 /*-- GPIO Configuration ------------------------------------------------------*/
00110   /* OneNAND Data lines configuration */
00111   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE |
00112                          RCC_APB2Periph_GPIOF, ENABLE);
00113   
00114 /*-- GPIO Configuration ------------------------------------------------------*/
00115   /*!< OneNAND Data lines configuration */
00116   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
00117                                 GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
00118   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00119   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00120   GPIO_Init(GPIOD, &GPIO_InitStructure); 
00121   
00122   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
00123                                 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | 
00124                                 GPIO_Pin_15;
00125   GPIO_Init(GPIOE, &GPIO_InitStructure);
00126   
00127   /*!< OneNAND Address lines configuration */
00128   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | 
00129                                 GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | 
00130                                 GPIO_Pin_14 | GPIO_Pin_15;
00131   GPIO_Init(GPIOF, &GPIO_InitStructure);
00132   
00133   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | 
00134                                 GPIO_Pin_4 | GPIO_Pin_5;
00135   GPIO_Init(GPIOG, &GPIO_InitStructure);
00136      
00137   /*!< CLK, NOE and NWE configuration */  
00138   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 |GPIO_Pin_5;
00139   GPIO_Init(GPIOD, &GPIO_InitStructure);
00140   
00141   /*!< NE1 configuration */
00142   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; 
00143   GPIO_Init(GPIOD, &GPIO_InitStructure);
00144 
00145   /*!< NL configuration */
00146   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; 
00147   GPIO_Init(GPIOB, &GPIO_InitStructure);
00148   
00149   /*!< NWAIT configuration */
00150   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; 
00151   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;  
00152   GPIO_Init(GPIOD, &GPIO_InitStructure);
00153     
00154   /*-- FSMC Configuration ----------------------------------------------------*/
00155   p.FSMC_AddressSetupTime = 0x01;
00156   p.FSMC_AddressHoldTime = 0x00;
00157   p.FSMC_DataSetupTime = 0x04;
00158   p.FSMC_BusTurnAroundDuration = 0x01;
00159   p.FSMC_CLKDivision = 0x1;
00160   p.FSMC_DataLatency = 0x00;
00161   p.FSMC_AccessMode = FSMC_AccessMode_B;
00162 
00163   FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM1;
00164   FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
00165   FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR;
00166   FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
00167   FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Enable;
00168   FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;      
00169   FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
00170   FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
00171   FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
00172   FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
00173   FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
00174   FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
00175   FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
00176   FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
00177   FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
00178 
00179   FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
00180   FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE);
00181 }
00182 
00183 /**
00184   * @brief  Reads OneNAND memory's Manufacturer and Device Code.
00185   * @param  OneNAND_ID: pointer to a OneNAND_IDTypeDef structure which will hold
00186   *         the Manufacturer and Device Code.  
00187   * @retval None
00188   */
00189 void OneNAND_ReadID(OneNAND_IDTypeDef* OneNAND_ID)
00190 {
00191   /* Read ID command */
00192   OneNAND_WRITE(Bank1_NOR1_ADDR + OneNAND_REG_COMMAND, OneNAND_CMD_READ_ID);
00193 
00194   /* Read ID data */
00195   OneNAND_ID->Manufacturer_ID = *(__IO uint16_t *)(Bank1_NOR1_ADDR + OneNAND_REG_MANUFACTERID);
00196   OneNAND_ID->Device_ID = *(__IO uint16_t *)(Bank1_NOR1_ADDR + OneNAND_REG_DEVICEID);
00197 }
00198 
00199 /**
00200   * @brief  Reads the OneNAND memory status. 
00201   * @param  None
00202   * @retval OneNAND Status
00203   */
00204 uint16_t OneNAND_ReadStatus(void)
00205 {
00206 __IO uint16_t status = 0x0;
00207 
00208   /* Read Status */
00209   return (status = *(__IO uint16_t *)(Bank1_NOR1_ADDR + OneNAND_REG_INTERRUPT));
00210 }
00211 
00212 /**
00213   * @brief  Reads the OneNAND Controller status 
00214   * @param  None
00215   * @retval OneNAND Controller Status
00216   */
00217 uint16_t OneNAND_ReadControllerStatus(void)
00218 {
00219 __IO uint16_t status = 0x0;
00220 
00221   /* Read Controller Status */
00222   return (status = *(__IO uint16_t *)(Bank1_NOR1_ADDR + OneNAND_REG_CONTROLSTATUS));
00223 }
00224 
00225 /**
00226   * @brief  Erases the specified OneNAND memory block.
00227   * @param  None
00228   * @retval The returned value can be: OneNAND_SUCCESS, OneNAND_ERROR
00229 *           or OneNAND_TIMEOUT
00230   */
00231 uint16_t OneNAND_EraseBlock(uint32_t BlockAddr)
00232 {
00233   uint16_t status = 0;
00234 
00235   /* Erase operation*/
00236   *(__IO uint16_t *)(Bank1_NOR1_ADDR + 0xF100*2) = BlockAddr;
00237   *(__IO uint16_t *)(Bank1_NOR1_ADDR + 0xF241*2) = 0x0000;
00238   *(__IO uint16_t *)(Bank1_NOR1_ADDR + 0xF220*2) = 0x0094; 
00239 
00240   status = *(__IO uint16_t *)(Bank1_NOR1_ADDR + 0xF241*2);
00241 
00242   while((status & 0x8000) != 0x8000)
00243   {
00244     status = *(__IO uint16_t *)(Bank1_NOR1_ADDR + 0xF241*2);
00245   }
00246  
00247   return (status);
00248 }
00249 
00250 /**
00251   * @brief  Resets the OneNAND memory
00252   * @param  None
00253   * @retval None
00254   */
00255 void OneNAND_Reset(void)
00256 {
00257   OneNAND_WRITE(ONENAND_BOOTPARTITION_ADDR + OneNAND_REG_COMMAND, OneNAND_CMD_RESET);
00258 }
00259 
00260 /**
00261   * @brief  Unlocks the OneNAND memory
00262   * @param  None
00263   * @retval None
00264   */
00265 uint16_t OneNAND_Unlock(void)
00266 {
00267   uint16_t  status = 0;
00268 
00269   /* Unlock sequence */
00270   *(__IO uint16_t *)(Bank1_NOR1_ADDR + 0xF100*2) = 0x0001;
00271   *(__IO uint16_t *)(Bank1_NOR1_ADDR + 0xF241*2) = 0x0000;
00272   *(__IO uint16_t *)(Bank1_NOR1_ADDR + 0xF220*2) = 0x0023;
00273 
00274   status = *(__IO uint16_t *)(Bank1_NOR1_ADDR + 0xF241*2);
00275 
00276   while((status & 0x8000) != 0x8000)
00277   {
00278     status = *(__IO uint16_t *)(Bank1_NOR1_ADDR + 0xF241*2);
00279   }
00280   return (status);
00281 }
00282 /**
00283   * @brief  Writes a Half-word buffer to the OneNAND memory. 
00284   * @param  pBuffer : pointer to buffer. 
00285   * @param  WriteAddr : OneNAND memory internal address from which the data will be 
00286   *         written.
00287   * @param  NumHalfwordToWrite : number of half-words to write. 
00288   * @retval None
00289   */
00290 uint16_t OneNAND_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
00291 {
00292   uint32_t datacounter = 0;
00293   uint16_t status = 0;
00294 
00295   for(datacounter = 0; datacounter < NumHalfwordToWrite; datacounter++)
00296   {
00297     *(__IO uint16_t *)((Bank1_NOR1_ADDR + WriteAddr) + (2*datacounter)) = pBuffer[datacounter];
00298   } 
00299  /* write operation */ 
00300   *(__IO uint16_t *)(Bank1_NOR1_ADDR + (0xF100*2)) = 0x0001;
00301   *(__IO uint16_t *)(Bank1_NOR1_ADDR + (0xF107*2)) = 0x0801;
00302   *(__IO uint16_t *)(Bank1_NOR1_ADDR + (0xF241*2)) = 0x0000;
00303   *(__IO uint16_t *)(Bank1_NOR1_ADDR + (0xF220*2)) = 0x0080; 
00304 
00305   status = *(__IO uint16_t *)(Bank1_NOR1_ADDR + (0xF241*2));
00306 
00307   while((status & 0x8000) != 0x8000)
00308   {
00309     status = *(__IO uint16_t *)(Bank1_NOR1_ADDR + (0xF241*2));
00310   }
00311 
00312   /* Load operation */
00313   *(__IO uint16_t *)(Bank1_NOR1_ADDR + (0xF100*2)) = 0x0000;
00314   *(__IO uint16_t *)(Bank1_NOR1_ADDR + (0xF107*2)) = 0x0000;
00315   *(__IO uint16_t *)(Bank1_NOR1_ADDR + (0xF200*2)) = 0x0000;
00316   *(__IO uint16_t *)(Bank1_NOR1_ADDR + (0xF101*2)) = 0x0000;
00317   *(__IO uint16_t *)(Bank1_NOR1_ADDR + (0xF241*2)) = 0x0000;
00318   *(__IO uint16_t *)(Bank1_NOR1_ADDR + (0xF220*2)) = 0x0000; 
00319 
00320   status = *(__IO uint16_t *)(Bank1_NOR1_ADDR + (0xF241*2));
00321 
00322   while((status & 0x8000) != 0x8000)
00323   {
00324     status = *(__IO uint16_t *)(0x60000000 + (0xF241*2));
00325   }
00326   return (status);
00327 }
00328 
00329 /**
00330   * @brief  Reads a block of data from the OneNAND memory.
00331   * @param  pBuffer : pointer to the buffer that receives the data read from the 
00332   *         OneNAND memory.
00333   * @param  ReadAddr : OneNAND memory internal address to read from.
00334   * @param  NumHalfwordToRead : number of half-words to read.
00335   * @retval None
00336   */
00337 void OneNAND_AsynchronousRead(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
00338 {
00339   uint16_t datatmp = 0x0;
00340   datatmp = *(__IO uint16_t *)(Bank1_NOR1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION); 
00341   /* Set the asynchronous read mode */
00342   OneNAND_WRITE(Bank1_NOR1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION, ( datatmp& 0x7FFF));
00343 
00344   /* Read data */
00345   for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /* while there is data to read */
00346   {
00347     /* Read a Halfword from the memory */
00348     *pBuffer++ = *(__IO uint16_t *)((Bank1_NOR1_ADDR + ReadAddr));
00349     ReadAddr = ReadAddr + 2; 
00350   }  
00351 }
00352 
00353 /**
00354   * @brief  Reads a block of data from the OneNAND memory.
00355   * @param  pBuffer : pointer to the buffer that receives the data read from the 
00356   *         OneNAND memory.
00357   * @param  ReadAddr : OneNAND memory internal address to read from.
00358   * @param  NumHalfwordToRead : number of half-words to read.
00359   * @retval None
00360   */
00361 void OneNAND_SynchronousRead(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
00362 {
00363   uint16_t datatmp = 0x0;
00364   datatmp = *(__IO uint16_t *)(Bank1_NOR1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION); 
00365   /* Set the asynchronous read mode */
00366   OneNAND_WRITE(Bank1_NOR1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION, (datatmp|0x8000));
00367 
00368   /* Read data */
00369   for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /* while there is data to read */
00370   {
00371     /* Read a Halfword from the memory */
00372     *pBuffer++ = *(__IO uint16_t *)((Bank1_NOR1_ADDR + ReadAddr));
00373     ReadAddr = ReadAddr + 2; 
00374   }  
00375 }
00376 /**
00377   * @}
00378   */
00379 
00380 /**
00381   * @}
00382   */
00383 
00384 /**
00385   * @}
00386   */
00387 
00388 /**
00389   * @}
00390   */
00391 
00392 /**
00393   * @}
00394   */  
00395 
00396 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
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