STM3210E_EVAL_FSMC_SRAM_Exported_Functions
[STM3210E_EVAL_FSMC_SRAM]

Functions

void SRAM_Init (void)
 Configures the FSMC and GPIOs to interface with the SRAM memory.
void SRAM_ReadBuffer (uint16_t *pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
 Reads a block of data from the FSMC SRAM memory.
void SRAM_WriteBuffer (uint16_t *pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
 Writes a Half-word buffer to the FSMC SRAM memory.

Function Documentation

void SRAM_Init ( void   ) 

Configures the FSMC and GPIOs to interface with the SRAM memory.

This function must be called before any write/read operation on the SRAM.

Parameters:
None 
Return values:
None 

< SRAM Data lines configuration

< SRAM Address lines configuration

< NOE and NWE configuration

< NE3 configuration

< NBL0, NBL1 configuration

< Enable FSMC Bank1_SRAM Bank

< SRAM Data lines configuration

< SRAM Address lines configuration

< NOE and NWE configuration

< NE3 configuration

< NBL0, NBL1 configuration

< Enable FSMC Bank1_SRAM Bank

Definition at line 98 of file stm32100e_eval_fsmc_sram.c.

References ENABLE, FSMC_NORSRAMTimingInitTypeDef::FSMC_AccessMode, FSMC_AccessMode_A, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressHoldTime, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_AsynchronousWait, FSMC_AsynchronousWait_Disable, FSMC_NORSRAMInitTypeDef::FSMC_Bank, FSMC_Bank1_NORSRAM3, FSMC_NORSRAMInitTypeDef::FSMC_BurstAccessMode, FSMC_BurstAccessMode_Disable, FSMC_NORSRAMTimingInitTypeDef::FSMC_BusTurnAroundDuration, FSMC_NORSRAMTimingInitTypeDef::FSMC_CLKDivision, FSMC_NORSRAMInitTypeDef::FSMC_DataAddressMux, FSMC_DataAddressMux_Disable, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataLatency, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_ExtendedMode, FSMC_ExtendedMode_Disable, FSMC_NORSRAMInitTypeDef::FSMC_MemoryDataWidth, FSMC_MemoryDataWidth_16b, FSMC_NORSRAMInitTypeDef::FSMC_MemoryType, FSMC_MemoryType_SRAM, FSMC_NORSRAMCmd(), FSMC_NORSRAMInit(), FSMC_NORSRAMInitTypeDef::FSMC_ReadWriteTimingStruct, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignal, FSMC_WaitSignal_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalActive, FSMC_WaitSignalActive_BeforeWaitState, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalPolarity, FSMC_WaitSignalPolarity_Low, FSMC_NORSRAMInitTypeDef::FSMC_WrapMode, FSMC_WrapMode_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WriteBurst, FSMC_WriteBurst_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WriteOperation, FSMC_WriteOperation_Enable, FSMC_NORSRAMInitTypeDef::FSMC_WriteTimingStruct, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_0, GPIO_Pin_1, GPIO_Pin_10, GPIO_Pin_11, GPIO_Pin_12, GPIO_Pin_13, GPIO_Pin_14, GPIO_Pin_15, GPIO_Pin_2, GPIO_Pin_3, GPIO_Pin_4, GPIO_Pin_5, GPIO_Pin_7, GPIO_Pin_8, GPIO_Pin_9, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, GPIOD, GPIOE, GPIOF, GPIOG, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, and RCC_APB2PeriphClockCmd().

Referenced by main().

void SRAM_ReadBuffer ( uint16_t *  pBuffer,
uint32_t  ReadAddr,
uint32_t  NumHalfwordToRead 
)

Reads a block of data from the FSMC SRAM memory.

Parameters:
pBuffer : pointer to the buffer that receives the data read from the SRAM memory.
ReadAddr : SRAM memory internal address to read from.
NumHalfwordToRead : number of half-words to read.
Return values:
None 

< while there is data to read

< Read a half-word from the memory

< Increment the address

< while there is data to read

< Read a half-word from the memory

< Increment the address

Definition at line 204 of file stm32100e_eval_fsmc_sram.c.

References Bank1_SRAM3_ADDR.

Referenced by main().

void SRAM_WriteBuffer ( uint16_t *  pBuffer,
uint32_t  WriteAddr,
uint32_t  NumHalfwordToWrite 
)

Writes a Half-word buffer to the FSMC SRAM memory.

Parameters:
pBuffer : pointer to buffer.
WriteAddr : SRAM memory internal address from which the data will be written.
NumHalfwordToWrite : number of half-words to write.
Return values:
None 

< while there is data to write

< Transfer data to the memory

< Increment the address

< while there is data to write

< Transfer data to the memory

< Increment the address

Definition at line 184 of file stm32100e_eval_fsmc_sram.c.

References Bank1_SRAM3_ADDR.

Referenced by main().

STM32F10x Standard Peripherals Library: Footer

 

 

 

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