RCC_Private_Functions
[RCC]

Functions

void RCC_ADCCLKConfig (uint32_t RCC_PCLK2)
 Configures the ADC clock (ADCCLK).
void RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue)
 Adjusts the Internal High Speed oscillator (HSI) calibration value.
void RCC_AHBPeriphClockCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
 Enables or disables the AHB peripheral clock.
void RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
 Enables or disables the Low Speed APB (APB1) peripheral clock.
void RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
 Forces or releases Low Speed APB (APB1) peripheral reset.
void RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
 Enables or disables the High Speed APB (APB2) peripheral clock.
void RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
 Forces or releases High Speed APB (APB2) peripheral reset.
void RCC_BackupResetCmd (FunctionalState NewState)
 Forces or releases the Backup domain reset.
void RCC_ClearFlag (void)
 Clears the RCC reset flags.
void RCC_ClearITPendingBit (uint8_t RCC_IT)
 Clears the RCCís interrupt pending bits.
void RCC_ClockSecuritySystemCmd (FunctionalState NewState)
 Enables or disables the Clock Security System.
void RCC_DeInit (void)
 Resets the RCC clock configuration to the default reset state.
void RCC_GetClocksFreq (RCC_ClocksTypeDef *RCC_Clocks)
 Returns the frequencies of different on chip clocks.
FlagStatus RCC_GetFlagStatus (uint8_t RCC_FLAG)
 Checks whether the specified RCC flag is set or not.
ITStatus RCC_GetITStatus (uint8_t RCC_IT)
 Checks whether the specified RCC interrupt has occurred or not.
uint8_t RCC_GetSYSCLKSource (void)
 Returns the clock source used as system clock.
void RCC_HCLKConfig (uint32_t RCC_SYSCLK)
 Configures the AHB clock (HCLK).
void RCC_HSEConfig (uint32_t RCC_HSE)
 Configures the External High Speed oscillator (HSE).
void RCC_HSICmd (FunctionalState NewState)
 Enables or disables the Internal High Speed oscillator (HSI).
void RCC_ITConfig (uint8_t RCC_IT, FunctionalState NewState)
 Enables or disables the specified RCC interrupts.
void RCC_LSEConfig (uint8_t RCC_LSE)
 Configures the External Low Speed oscillator (LSE).
void RCC_LSICmd (FunctionalState NewState)
 Enables or disables the Internal Low Speed oscillator (LSI).
void RCC_MCOConfig (uint8_t RCC_MCO)
 Selects the clock source to output on MCO pin.
void RCC_PCLK1Config (uint32_t RCC_HCLK)
 Configures the Low Speed APB clock (PCLK1).
void RCC_PCLK2Config (uint32_t RCC_HCLK)
 Configures the High Speed APB clock (PCLK2).
void RCC_PLLCmd (FunctionalState NewState)
 Enables or disables the PLL.
void RCC_PLLConfig (uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
 Configures the PLL clock source and multiplication factor.
void RCC_RTCCLKCmd (FunctionalState NewState)
 Enables or disables the RTC clock.
void RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource)
 Configures the RTC clock (RTCCLK).
void RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource)
 Configures the system clock (SYSCLK).
void RCC_USBCLKConfig (uint32_t RCC_USBCLKSource)
 Configures the USB clock (USBCLK).
ErrorStatus RCC_WaitForHSEStartUp (void)
 Waits for HSE start-up.

Function Documentation

void RCC_ADCCLKConfig ( uint32_t  RCC_PCLK2  ) 

Configures the ADC clock (ADCCLK).

Parameters:
RCC_PCLK2,: defines the ADC clock divider. This clock is derived from the APB2 clock (PCLK2). This parameter can be one of the following values:

  • RCC_PCLK2_Div2: ADC clock = PCLK2/2
  • RCC_PCLK2_Div4: ADC clock = PCLK2/4
  • RCC_PCLK2_Div6: ADC clock = PCLK2/6
  • RCC_PCLK2_Div8: ADC clock = PCLK2/8
Return values:
None 

Definition at line 765 of file stm32f10x_rcc.c.

References assert_param, CFGR_ADCPRE_Reset_Mask, IS_RCC_ADCCLK, and RCC.

Referenced by RCC_Configuration().

void RCC_AdjustHSICalibrationValue ( uint8_t  HSICalibrationValue  ) 

Adjusts the Internal High Speed oscillator (HSI) calibration value.

Parameters:
HSICalibrationValue,: specifies the calibration trimming value. This parameter must be a number between 0 and 0x1F.
Return values:
None 

Definition at line 333 of file stm32f10x_rcc.c.

References assert_param, CR_HSITRIM_Mask, IS_RCC_CALIBRATION_VALUE, and RCC.

void RCC_AHBPeriphClockCmd ( uint32_t  RCC_AHBPeriph,
FunctionalState  NewState 
)

Enables or disables the AHB peripheral clock.

Parameters:
RCC_AHBPeriph,: specifies the AHB peripheral to gates its clock.

For STM32_Connectivity_line_devices, this parameter can be any combination of the following values:

  • RCC_AHBPeriph_DMA1
  • RCC_AHBPeriph_DMA2
  • RCC_AHBPeriph_SRAM
  • RCC_AHBPeriph_FLITF
  • RCC_AHBPeriph_CRC
  • RCC_AHBPeriph_OTG_FS
  • RCC_AHBPeriph_ETH_MAC
  • RCC_AHBPeriph_ETH_MAC_Tx
  • RCC_AHBPeriph_ETH_MAC_Rx

For other_STM32_devices, this parameter can be any combination of the following values:

  • RCC_AHBPeriph_DMA1
  • RCC_AHBPeriph_DMA2
  • RCC_AHBPeriph_SRAM
  • RCC_AHBPeriph_FLITF
  • RCC_AHBPeriph_CRC
  • RCC_AHBPeriph_FSMC
  • RCC_AHBPeriph_SDIO
Note:
SRAM and FLITF clock can be disabled only during sleep mode.
Parameters:
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None 

Definition at line 1063 of file stm32f10x_rcc.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_AHB_PERIPH, and RCC.

Referenced by IOE_DMA_Config(), LCD_CtrlLinesConfig(), LM75_DMA_Config(), main(), OneNAND_Init(), RCC_Configuration(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), and sEE_LowLevel_Init().

void RCC_APB1PeriphClockCmd ( uint32_t  RCC_APB1Periph,
FunctionalState  NewState 
)

Enables or disables the Low Speed APB (APB1) peripheral clock.

Parameters:
RCC_APB1Periph,: specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:

  • RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None 

Definition at line 1125 of file stm32f10x_rcc.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB1_PERIPH, and RCC.

Referenced by CAN_Config(), HDMI_CEC_Init(), IOE_GPIO_Config(), LCD_DeInit(), LCD_SPIConfig(), LM75_LowLevel_DeInit(), LM75_LowLevel_Init(), main(), RCC_Configuration(), RTC_Configuration(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), sEE_LowLevel_DeInit(), sEE_LowLevel_Init(), and STM_EVAL_COMInit().

void RCC_APB1PeriphResetCmd ( uint32_t  RCC_APB1Periph,
FunctionalState  NewState 
)

Forces or releases Low Speed APB (APB1) peripheral reset.

Parameters:
RCC_APB1Periph,: specifies the APB1 peripheral to reset. This parameter can be any combination of the following values:

  • RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None 

Definition at line 1215 of file stm32f10x_rcc.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB1_PERIPH, and RCC.

Referenced by CAN_DeInit(), CEC_DeInit(), DAC_DeInit(), I2C_DeInit(), IOE_GPIO_Config(), PWR_DeInit(), SPI_I2S_DeInit(), TIM_DeInit(), USART_DeInit(), and WWDG_DeInit().

void RCC_APB2PeriphClockCmd ( uint32_t  RCC_APB2Periph,
FunctionalState  NewState 
)

Enables or disables the High Speed APB (APB2) peripheral clock.

Parameters:
RCC_APB2Periph,: specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:

  • RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None 

Definition at line 1094 of file stm32f10x_rcc.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB2_PERIPH, and RCC.

Referenced by CAN_Config(), GPIO_Configuration(), HDMI_CEC_Init(), IOE_EXTI_Config(), IOE_GPIO_Config(), LCD_CtrlLinesConfig(), LCD_SPIConfig(), LM75_LowLevel_Init(), main(), NAND_Init(), NOR_Init(), OneNAND_Init(), RCC_Configuration(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), sEE_LowLevel_Init(), sFLASH_LowLevel_DeInit(), sFLASH_LowLevel_Init(), SRAM_Init(), STM_EVAL_COMInit(), STM_EVAL_LEDInit(), and STM_EVAL_PBInit().

void RCC_APB2PeriphResetCmd ( uint32_t  RCC_APB2Periph,
FunctionalState  NewState 
)

Forces or releases High Speed APB (APB2) peripheral reset.

Parameters:
RCC_APB2Periph,: specifies the APB2 peripheral to reset. This parameter can be any combination of the following values:

  • RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11
NewState,: new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values:
None 

Definition at line 1184 of file stm32f10x_rcc.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB2_PERIPH, and RCC.

Referenced by ADC_DeInit(), GPIO_AFIODeInit(), GPIO_DeInit(), SPI_I2S_DeInit(), TIM_DeInit(), and USART_DeInit().

void RCC_BackupResetCmd ( FunctionalState  NewState  ) 

Forces or releases the Backup domain reset.

Parameters:
NewState,: new state of the Backup domain reset. This parameter can be: ENABLE or DISABLE.
Return values:
None 

Definition at line 1236 of file stm32f10x_rcc.c.

References assert_param, BDCR_BDRST_BB, and IS_FUNCTIONAL_STATE.

Referenced by BKP_DeInit().

void RCC_ClearFlag ( void   ) 

Clears the RCC reset flags.

Note:
The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
Parameters:
None 
Return values:
None 

Definition at line 1370 of file stm32f10x_rcc.c.

References CSR_RMVF_Set, and RCC.

Referenced by main().

void RCC_ClearITPendingBit ( uint8_t  RCC_IT  ) 

Clears the RCCís interrupt pending bits.

Parameters:
RCC_IT,: specifies the interrupt pending bit to clear.

For STM32_Connectivity_line_devices, this parameter can be any combination of the following values:

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_PLL2RDY: PLL2 ready interrupt
  • RCC_IT_PLL3RDY: PLL3 ready interrupt
  • RCC_IT_CSS: Clock Security System interrupt

For other_STM32_devices, this parameter can be any combination of the following values:

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_CSS: Clock Security System interrupt
    Return values:
    None 

Definition at line 1447 of file stm32f10x_rcc.c.

References assert_param, CIR_BYTE3_ADDRESS, and IS_RCC_CLEAR_IT.

Referenced by NMI_Handler(), and RCC_IRQHandler().

void RCC_ClockSecuritySystemCmd ( FunctionalState  NewState  ) 

Enables or disables the Clock Security System.

Parameters:
NewState,: new state of the Clock Security System.. This parameter can be: ENABLE or DISABLE.
Return values:
None 

Definition at line 1249 of file stm32f10x_rcc.c.

References assert_param, CR_CSSON_BB, and IS_FUNCTIONAL_STATE.

Referenced by main().

void RCC_DeInit ( void   ) 

Resets the RCC clock configuration to the default reset state.

Parameters:
None 
Return values:
None 

Definition at line 216 of file stm32f10x_rcc.c.

References RCC.

Referenced by RCC_Configuration(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SetSysClockToHSE().

void RCC_GetClocksFreq ( RCC_ClocksTypeDef RCC_Clocks  ) 

Returns the frequencies of different on chip clocks.

Parameters:
RCC_Clocks,: pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies.
Note:
The result of this function could be not correct when using fractional value for HSE crystal.
Return values:
None 

Definition at line 907 of file stm32f10x_rcc.c.

References RCC_ClocksTypeDef::ADCCLK_Frequency, ADCPrescTable, APBAHBPrescTable, CFGR_ADCPRE_Set_Mask, CFGR_HPRE_Set_Mask, CFGR_PLLMull_Mask, CFGR_PLLSRC_Mask, CFGR_PLLXTPRE_Mask, CFGR_PPRE1_Set_Mask, CFGR_PPRE2_Set_Mask, CFGR_SWS_Mask, RCC_ClocksTypeDef::HCLK_Frequency, HSE_VALUE, HSI_VALUE, RCC_ClocksTypeDef::PCLK1_Frequency, RCC_ClocksTypeDef::PCLK2_Frequency, RCC, RESET, and RCC_ClocksTypeDef::SYSCLK_Frequency.

Referenced by I2C_Init(), I2S_Init(), main(), and USART_Init().

FlagStatus RCC_GetFlagStatus ( uint8_t  RCC_FLAG  ) 

Checks whether the specified RCC flag is set or not.

Parameters:
RCC_FLAG,: specifies the flag to check.

For STM32_Connectivity_line_devices, this parameter can be one of the following values:

  • RCC_FLAG_HSIRDY: HSI oscillator clock ready
  • RCC_FLAG_HSERDY: HSE oscillator clock ready
  • RCC_FLAG_PLLRDY: PLL clock ready
  • RCC_FLAG_PLL2RDY: PLL2 clock ready
  • RCC_FLAG_PLL3RDY: PLL3 clock ready
  • RCC_FLAG_LSERDY: LSE oscillator clock ready
  • RCC_FLAG_LSIRDY: LSI oscillator clock ready
  • RCC_FLAG_PINRST: Pin reset
  • RCC_FLAG_PORRST: POR/PDR reset
  • RCC_FLAG_SFTRST: Software reset
  • RCC_FLAG_IWDGRST: Independent Watchdog reset
  • RCC_FLAG_WWDGRST: Window Watchdog reset
  • RCC_FLAG_LPWRRST: Low Power reset

For other_STM32_devices, this parameter can be one of the following values:

  • RCC_FLAG_HSIRDY: HSI oscillator clock ready
  • RCC_FLAG_HSERDY: HSE oscillator clock ready
  • RCC_FLAG_PLLRDY: PLL clock ready
  • RCC_FLAG_LSERDY: LSE oscillator clock ready
  • RCC_FLAG_LSIRDY: LSI oscillator clock ready
  • RCC_FLAG_PINRST: Pin reset
  • RCC_FLAG_PORRST: POR/PDR reset
  • RCC_FLAG_SFTRST: Software reset
  • RCC_FLAG_IWDGRST: Independent Watchdog reset
  • RCC_FLAG_WWDGRST: Window Watchdog reset
  • RCC_FLAG_LPWRRST: Low Power reset
Return values:
The new state of RCC_FLAG (SET or RESET).

Definition at line 1325 of file stm32f10x_rcc.c.

References assert_param, FLAG_Mask, IS_RCC_FLAG, RCC, RESET, and SET.

Referenced by HDMI_CEC_CommandCallBack(), main(), RCC_Configuration(), RCC_IRQHandler(), RCC_WaitForHSEStartUp(), RTC_Configuration(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SYSCLKConfig_STOP().

ITStatus RCC_GetITStatus ( uint8_t  RCC_IT  ) 

Checks whether the specified RCC interrupt has occurred or not.

Parameters:
RCC_IT,: specifies the RCC interrupt source to check.

For STM32_Connectivity_line_devices, this parameter can be one of the following values:

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_PLL2RDY: PLL2 ready interrupt
  • RCC_IT_PLL3RDY: PLL3 ready interrupt
  • RCC_IT_CSS: Clock Security System interrupt

For other_STM32_devices, this parameter can be one of the following values:

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_CSS: Clock Security System interrupt
Return values:
The new state of RCC_IT (SET or RESET).

Definition at line 1401 of file stm32f10x_rcc.c.

References assert_param, IS_RCC_GET_IT, RCC, RESET, and SET.

Referenced by NMI_Handler(), and RCC_IRQHandler().

uint8_t RCC_GetSYSCLKSource ( void   ) 

Returns the clock source used as system clock.

Parameters:
None 
Return values:
The clock source used as system clock. The returned value can be one of the following:

  • 0x00: HSI used as system clock
  • 0x04: HSE used as system clock
  • 0x08: PLL used as system clock

Definition at line 586 of file stm32f10x_rcc.c.

References CFGR_SWS_Mask, and RCC.

Referenced by HDMI_CEC_CommandCallBack(), RCC_Configuration(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), SetSysClockToHSE(), and SYSCLKConfig_STOP().

void RCC_HCLKConfig ( uint32_t  RCC_SYSCLK  ) 

Configures the AHB clock (HCLK).

Parameters:
RCC_SYSCLK,: defines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values:

  • RCC_SYSCLK_Div1: AHB clock = SYSCLK
  • RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
  • RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
  • RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
  • RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
  • RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
  • RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
  • RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
  • RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
Return values:
None 

Definition at line 607 of file stm32f10x_rcc.c.

References assert_param, CFGR_HPRE_Reset_Mask, IS_RCC_HCLK, and RCC.

Referenced by RCC_Configuration(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SetSysClockToHSE().

void RCC_HSEConfig ( uint32_t  RCC_HSE  ) 

Configures the External High Speed oscillator (HSE).

Note:
HSE can not be stopped if it is used directly or through the PLL as system clock.
Parameters:
RCC_HSE,: specifies the new state of the HSE. This parameter can be one of the following values:

  • RCC_HSE_OFF: HSE oscillator OFF
  • RCC_HSE_ON: HSE oscillator ON
  • RCC_HSE_Bypass: HSE oscillator bypassed with external clock
Return values:
None 

Definition at line 269 of file stm32f10x_rcc.c.

References assert_param, CR_HSEBYP_Reset, CR_HSEBYP_Set, CR_HSEON_Reset, CR_HSEON_Set, IS_RCC_HSE, RCC, RCC_HSE_Bypass, and RCC_HSE_ON.

Referenced by NMI_Handler(), RCC_Configuration(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), SetSysClockToHSE(), and SYSCLKConfig_STOP().

void RCC_HSICmd ( FunctionalState  NewState  ) 

Enables or disables the Internal High Speed oscillator (HSI).

Note:
HSI can not be stopped if it is used directly or through the PLL as system clock.
Parameters:
NewState,: new state of the HSI. This parameter can be: ENABLE or DISABLE.
Return values:
None 

Definition at line 353 of file stm32f10x_rcc.c.

References assert_param, CR_HSION_BB, and IS_FUNCTIONAL_STATE.

void RCC_ITConfig ( uint8_t  RCC_IT,
FunctionalState  NewState 
)

Enables or disables the specified RCC interrupts.

Parameters:
RCC_IT,: specifies the RCC interrupt sources to be enabled or disabled.

For STM32_Connectivity_line_devices, this parameter can be any combination of the following values

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_PLL2RDY: PLL2 ready interrupt
  • RCC_IT_PLL3RDY: PLL3 ready interrupt

For other_STM32_devices, this parameter can be any combination of the following values

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
Parameters:
NewState,: new state of the specified RCC interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None 

Definition at line 699 of file stm32f10x_rcc.c.

References assert_param, CIR_BYTE2_ADDRESS, DISABLE, IS_FUNCTIONAL_STATE, and IS_RCC_IT.

Referenced by NMI_Handler().

void RCC_LSEConfig ( uint8_t  RCC_LSE  ) 

Configures the External Low Speed oscillator (LSE).

Parameters:
RCC_LSE,: specifies the new state of the LSE. This parameter can be one of the following values:

  • RCC_LSE_OFF: LSE oscillator OFF
  • RCC_LSE_ON: LSE oscillator ON
  • RCC_LSE_Bypass: LSE oscillator bypassed with external clock
Return values:
None 

Definition at line 828 of file stm32f10x_rcc.c.

References assert_param, BDCR_ADDRESS, IS_RCC_LSE, RCC_LSE_Bypass, RCC_LSE_OFF, and RCC_LSE_ON.

Referenced by RTC_Configuration().

void RCC_LSICmd ( FunctionalState  NewState  ) 

Enables or disables the Internal Low Speed oscillator (LSI).

Note:
LSI can not be disabled if the IWDG is running.
Parameters:
NewState,: new state of the LSI. This parameter can be: ENABLE or DISABLE.
Return values:
None 

Definition at line 861 of file stm32f10x_rcc.c.

References assert_param, CSR_LSION_BB, and IS_FUNCTIONAL_STATE.

Referenced by RTC_Configuration().

void RCC_MCOConfig ( uint8_t  RCC_MCO  ) 

Selects the clock source to output on MCO pin.

Parameters:
RCC_MCO,: specifies the clock source to output.

For STM32_Connectivity_line_devices, this parameter can be one of the following values:

  • RCC_MCO_NoClock: No clock selected
  • RCC_MCO_SYSCLK: System clock selected
  • RCC_MCO_HSI: HSI oscillator clock selected
  • RCC_MCO_HSE: HSE oscillator clock selected
  • RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
  • RCC_MCO_PLL2CLK: PLL2 clock selected
  • RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected
  • RCC_MCO_XT1: External 3-25 MHz oscillator clock selected
  • RCC_MCO_PLL3CLK: PLL3 clock selected

For other_STM32_devices, this parameter can be one of the following values:

  • RCC_MCO_NoClock: No clock selected
  • RCC_MCO_SYSCLK: System clock selected
  • RCC_MCO_HSI: HSI oscillator clock selected
  • RCC_MCO_HSE: HSE oscillator clock selected
  • RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
Return values:
None 

Definition at line 1281 of file stm32f10x_rcc.c.

References assert_param, CFGR_BYTE4_ADDRESS, and IS_RCC_MCO.

Referenced by main().

void RCC_PCLK1Config ( uint32_t  RCC_HCLK  ) 

Configures the Low Speed APB clock (PCLK1).

Parameters:
RCC_HCLK,: defines the APB1 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:

  • RCC_HCLK_Div1: APB1 clock = HCLK
  • RCC_HCLK_Div2: APB1 clock = HCLK/2
  • RCC_HCLK_Div4: APB1 clock = HCLK/4
  • RCC_HCLK_Div8: APB1 clock = HCLK/8
  • RCC_HCLK_Div16: APB1 clock = HCLK/16
Return values:
None 

Definition at line 633 of file stm32f10x_rcc.c.

References assert_param, CFGR_PPRE1_Reset_Mask, IS_RCC_PCLK, and RCC.

Referenced by RCC_Configuration(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SetSysClockToHSE().

void RCC_PCLK2Config ( uint32_t  RCC_HCLK  ) 

Configures the High Speed APB clock (PCLK2).

Parameters:
RCC_HCLK,: defines the APB2 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:

  • RCC_HCLK_Div1: APB2 clock = HCLK
  • RCC_HCLK_Div2: APB2 clock = HCLK/2
  • RCC_HCLK_Div4: APB2 clock = HCLK/4
  • RCC_HCLK_Div8: APB2 clock = HCLK/8
  • RCC_HCLK_Div16: APB2 clock = HCLK/16
Return values:
None 

Definition at line 659 of file stm32f10x_rcc.c.

References assert_param, CFGR_PPRE2_Reset_Mask, IS_RCC_PCLK, and RCC.

Referenced by RCC_Configuration(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SetSysClockToHSE().

void RCC_PLLCmd ( FunctionalState  NewState  ) 

Enables or disables the PLL.

Note:
The PLL can not be disabled if it is used as system clock.
Parameters:
NewState,: new state of the PLL. This parameter can be: ENABLE or DISABLE.
Return values:
None 

Definition at line 400 of file stm32f10x_rcc.c.

References assert_param, CR_PLLON_BB, and IS_FUNCTIONAL_STATE.

Referenced by HDMI_CEC_CommandCallBack(), RCC_Configuration(), RCC_IRQHandler(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SYSCLKConfig_STOP().

void RCC_PLLConfig ( uint32_t  RCC_PLLSource,
uint32_t  RCC_PLLMul 
)

Configures the PLL clock source and multiplication factor.

Note:
This function must be used only when the PLL is disabled.
Parameters:
RCC_PLLSource,: specifies the PLL entry clock source. For STM32_Connectivity_line_devices or STM32_Value_line_devices, this parameter can be one of the following values:

  • RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
  • RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry For other_STM32_devices, this parameter can be one of the following values:
  • RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
  • RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry
  • RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry
RCC_PLLMul,: specifies the PLL multiplication factor. For STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5} For other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16]
Return values:
None 

Definition at line 377 of file stm32f10x_rcc.c.

References assert_param, CFGR_PLL_Mask, IS_RCC_PLL_MUL, IS_RCC_PLL_SOURCE, and RCC.

Referenced by HDMI_CEC_CommandCallBack(), RCC_Configuration(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), and SetSysClockTo72().

void RCC_RTCCLKCmd ( FunctionalState  NewState  ) 

Enables or disables the RTC clock.

Note:
This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.
Parameters:
NewState,: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
Return values:
None 

Definition at line 892 of file stm32f10x_rcc.c.

References assert_param, BDCR_RTCEN_BB, and IS_FUNCTIONAL_STATE.

Referenced by RTC_Configuration().

void RCC_RTCCLKConfig ( uint32_t  RCC_RTCCLKSource  ) 

Configures the RTC clock (RTCCLK).

Note:
Once the RTC clock is selected it canít be changed unless the Backup domain is reset.
Parameters:
RCC_RTCCLKSource,: specifies the RTC clock source. This parameter can be one of the following values:

  • RCC_RTCCLKSource_LSE: LSE selected as RTC clock
  • RCC_RTCCLKSource_LSI: LSI selected as RTC clock
  • RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock
Return values:
None 

Definition at line 878 of file stm32f10x_rcc.c.

References assert_param, IS_RCC_RTCCLK_SOURCE, and RCC.

Referenced by RTC_Configuration().

void RCC_SYSCLKConfig ( uint32_t  RCC_SYSCLKSource  ) 

Configures the system clock (SYSCLK).

Parameters:
RCC_SYSCLKSource,: specifies the clock source used as system clock. This parameter can be one of the following values:

  • RCC_SYSCLKSource_HSI: HSI selected as system clock
  • RCC_SYSCLKSource_HSE: HSE selected as system clock
  • RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
Return values:
None 

Definition at line 563 of file stm32f10x_rcc.c.

References assert_param, CFGR_SW_Mask, IS_RCC_SYSCLK_SOURCE, and RCC.

Referenced by HDMI_CEC_CommandCallBack(), RCC_Configuration(), RCC_IRQHandler(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), SetSysClockToHSE(), and SYSCLKConfig_STOP().

void RCC_USBCLKConfig ( uint32_t  RCC_USBCLKSource  ) 

Configures the USB clock (USBCLK).

Parameters:
RCC_USBCLKSource,: specifies the USB clock source. This clock is derived from the PLL output. This parameter can be one of the following values:

  • RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB clock source
  • RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
Return values:
None 

Definition at line 727 of file stm32f10x_rcc.c.

References assert_param, CFGR_USBPRE_BB, and IS_RCC_USBCLK_SOURCE.

ErrorStatus RCC_WaitForHSEStartUp ( void   ) 

Waits for HSE start-up.

Parameters:
None 
Return values:
An ErrorStatus enumuration value:

  • SUCCESS: HSE oscillator is stable and ready to use
  • ERROR: HSE oscillator not yet ready

Definition at line 303 of file stm32f10x_rcc.c.

References ERROR, HSE_STARTUP_TIMEOUT, RCC_FLAG_HSERDY, RCC_GetFlagStatus(), RESET, status, and SUCCESS.

Referenced by RCC_Configuration(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), SetSysClockToHSE(), and SYSCLKConfig_STOP().

STM32F10x Standard Peripherals Library: Footer

 

 

 

      For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit  www.st.com/STM32