STM32F10x_StdPeriph_Examples/TIM/DMA/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/DMA/main.c 
00004   * @author  MCD Application Team
00005   * @version V3.4.0
00006   * @date    10/15/2010
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @copy
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
00019   */ 
00020 
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32f10x.h"
00023 
00024 /** @addtogroup STM32F10x_StdPeriph_Examples
00025   * @{
00026   */
00027 
00028 /** @addtogroup TIM_DMA
00029   * @{
00030   */ 
00031 
00032 /* Private typedef -----------------------------------------------------------*/
00033 /* Private define ------------------------------------------------------------*/
00034 #define TIM1_CCR3_Address    0x40012C3C
00035 
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
00039 TIM_OCInitTypeDef  TIM_OCInitStructure;
00040 uint16_t SRC_Buffer[3] = {0, 0, 0};
00041 uint16_t TimerPeriod = 0;
00042 
00043 /* Private function prototypes -----------------------------------------------*/
00044 void RCC_Configuration(void);
00045 void GPIO_Configuration(void);
00046 void DMA_Configuration(void);
00047 
00048 /* Private functions ---------------------------------------------------------*/
00049 
00050 /**
00051   * @brief   Main program
00052   * @param  None
00053   * @retval None
00054   */
00055 int main(void)
00056 {
00057   /*!< At this stage the microcontroller clock setting is already configured, 
00058        this is done through SystemInit() function which is called from startup
00059        file (startup_stm32f10x_xx.s) before to branch to application main.
00060        To reconfigure the default setting of SystemInit() function, refer to
00061        system_stm32f10x.c file
00062      */     
00063        
00064   /* System Clocks Configuration */
00065   RCC_Configuration();
00066 
00067   /* GPIO Configuration */
00068   GPIO_Configuration();
00069 
00070   /* DMA Configuration */
00071   DMA_Configuration();
00072 
00073   /* TIM1 DMA Transfer example -------------------------------------------------
00074   TIM1CLK = SystemCoreClock, Prescaler = 0, TIM1 counter clock = SystemCoreClock
00075   SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
00076   and Connectivity line devices and to 24 MHz for Low-Density Value line and
00077   Medium-Density Value line devices.
00078 
00079   The objective is to configure TIM1 channel 3 to generate complementary PWM
00080   signal with a frequency equal to 17.57 KHz:
00081      - TIM1_Period = (SystemCoreClock / 17570) - 1
00082   and a variable duty cycle that is changed by the DMA after a specific number of
00083   Update DMA request.
00084 
00085   The number of this repetitive requests is defined by the TIM1 Repetion counter,
00086   each 3 Update Requests, the TIM1 Channel 3 Duty Cycle changes to the next new 
00087   value defined by the SRC_Buffer . 
00088   -----------------------------------------------------------------------------*/
00089   /* Compute the value to be set in ARR regiter to generate signal frequency at 17.57 Khz */
00090   TimerPeriod = (SystemCoreClock / 17570 ) - 1;
00091   /* Compute CCR1 value to generate a duty cycle at 50% */
00092   SRC_Buffer[0] = (uint16_t) (((uint32_t) 5 * (TimerPeriod - 1)) / 10);
00093   /* Compute CCR1 value to generate a duty cycle at 37.5% */
00094   SRC_Buffer[1] = (uint16_t) (((uint32_t) 375 * (TimerPeriod - 1)) / 1000);
00095   /* Compute CCR1 value to generate a duty cycle at 25% */
00096   SRC_Buffer[2] = (uint16_t) (((uint32_t) 25 * (TimerPeriod - 1)) / 100);
00097 
00098   /* TIM1 Peripheral Configuration --------------------------------------------*/
00099   /* Time Base configuration */
00100   TIM_TimeBaseStructure.TIM_Prescaler = 0;
00101   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00102   TIM_TimeBaseStructure.TIM_Period = TimerPeriod;
00103   TIM_TimeBaseStructure.TIM_ClockDivision = 0;
00104   TIM_TimeBaseStructure.TIM_RepetitionCounter = 2;
00105 
00106   TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
00107 
00108   /* Channel 3 Configuration in PWM mode */
00109   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
00110   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00111   TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
00112   TIM_OCInitStructure.TIM_Pulse = SRC_Buffer[0];
00113   TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
00114   TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_Low;
00115   TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
00116   TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;
00117 
00118   TIM_OC3Init(TIM1, &TIM_OCInitStructure);
00119 
00120   /* TIM1 Update DMA Request enable */
00121   TIM_DMACmd(TIM1, TIM_DMA_Update, ENABLE);
00122 
00123   /* TIM1 counter enable */
00124   TIM_Cmd(TIM1, ENABLE);
00125 
00126   /* Main Output Enable */
00127   TIM_CtrlPWMOutputs(TIM1, ENABLE);
00128 
00129   while (1)
00130   {}
00131 }
00132 
00133 /**
00134   * @brief  Configures the different system clocks.
00135   * @param  None
00136   * @retval None
00137   */
00138 void RCC_Configuration(void)
00139 {
00140   /* TIM1, GPIOA and GPIOB clock enable */
00141   RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA |
00142                          RCC_APB2Periph_GPIOB, ENABLE);
00143   /* DMA clock enable */
00144   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
00145 }
00146 
00147 /**
00148   * @brief  Configure the TIM1 Pins.
00149   * @param  None
00150   * @retval None
00151   */
00152 void GPIO_Configuration(void)
00153 {
00154   GPIO_InitTypeDef GPIO_InitStructure;
00155 
00156   /* GPIOA Configuration: Channel 3 as alternate function push-pull */
00157   GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_10;
00158   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00159   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00160   GPIO_Init(GPIOA, &GPIO_InitStructure);
00161 
00162   /* GPIOB Configuration: Channel 3N as alternate function push-pull */
00163   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
00164   GPIO_Init(GPIOB, &GPIO_InitStructure);
00165 }
00166 
00167 /**
00168   * @brief  Configures the DMA.
00169   * @param  None
00170   * @retval None
00171   */
00172 void DMA_Configuration(void)
00173 {
00174   DMA_InitTypeDef DMA_InitStructure;
00175 
00176   /* DMA1 Channel5 Config */
00177   DMA_DeInit(DMA1_Channel5);
00178 
00179   DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)TIM1_CCR3_Address;
00180   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SRC_Buffer;
00181   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
00182   DMA_InitStructure.DMA_BufferSize = 3;
00183   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00184   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
00185   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
00186   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
00187   DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
00188   DMA_InitStructure.DMA_Priority = DMA_Priority_High;
00189   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
00190 
00191   DMA_Init(DMA1_Channel5, &DMA_InitStructure);
00192 
00193   /* DMA1 Channel5 enable */
00194   DMA_Cmd(DMA1_Channel5, ENABLE);
00195 }
00196 
00197 #ifdef  USE_FULL_ASSERT
00198 
00199 /**
00200   * @brief  Reports the name of the source file and the source line number
00201   *         where the assert_param error has occurred.
00202   * @param  file: pointer to the source file name
00203   * @param  line: assert_param error line source number
00204   * @retval None
00205   */
00206 void assert_failed(uint8_t* file, uint32_t line)
00207 {
00208   /* User can add his own implementation to report the file name and line number,
00209      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00210 
00211   while (1)
00212   {}
00213 }
00214 #endif
00215 
00216 /**
00217   * @}
00218   */ 
00219 
00220 /**
00221   * @}
00222   */ 
00223 
00224 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
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