STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    CortexM3/Mode_Privilege/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.4.0
00006   * @date    10/15/2010
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   ******************************************************************************  
00009   *
00010   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00011   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00012   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00013   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00014   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00015   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00016   *
00017   * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
00018   ******************************************************************************
00019   */
00020 
00021 /** @addtogroup CMSIS
00022   * @{
00023   */
00024 
00025 /** @addtogroup stm32f10x_system
00026   * @{
00027   */  
00028   
00029 /** @addtogroup STM32F10x_System_Private_Includes
00030   * @{
00031   */
00032 
00033 #include "stm32f10x.h"
00034 
00035 /**
00036   * @}
00037   */
00038 
00039 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00040   * @{
00041   */
00042 
00043 /**
00044   * @}
00045   */
00046 
00047 /** @addtogroup STM32F10x_System_Private_Defines
00048   * @{
00049   */
00050 
00051 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00052    frequency (after reset the HSI is used as SYSCLK source)
00053    
00054    IMPORTANT NOTE:
00055    ============== 
00056    1. After each device reset the HSI is used as System clock source.
00057 
00058    2. Please make sure that the selected System clock doesn't exceed your device's
00059       maximum frequency.
00060       
00061    3. If none of the define below is enabled, the HSI is used as System clock
00062     source.
00063 
00064    4. The System clock configuration functions provided within this file assume that:
00065         - For Low, Medium and High density Value line devices an external 8MHz 
00066           crystal is used to drive the System clock.
00067         - For Low, Medium and High density devices an external 8MHz crystal is
00068           used to drive the System clock.
00069         - For Connectivity line devices an external 25MHz crystal is used to drive
00070           the System clock.
00071      If you are using different crystal you have to adapt those functions accordingly.
00072     */
00073     
00074 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00075 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00076  #define SYSCLK_FREQ_24MHz  24000000
00077 #else
00078 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00079 /* #define SYSCLK_FREQ_24MHz  24000000 */ 
00080 /* #define SYSCLK_FREQ_36MHz  36000000 */
00081 /* #define SYSCLK_FREQ_48MHz  48000000 */
00082 /* #define SYSCLK_FREQ_56MHz  56000000 */
00083 #define SYSCLK_FREQ_72MHz  72000000
00084 #endif
00085 
00086 /*!< Uncomment the following line if you need to use external SRAM mounted
00087      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
00088      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
00089 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00090 /* #define DATA_IN_ExtSRAM */
00091 #endif
00092 
00093 /*!< Uncomment the following line if you need to relocate your vector Table in
00094      Internal SRAM. */ 
00095 /* #define VECT_TAB_SRAM */
00096 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
00097                                   This value must be a multiple of 0x100. */
00098 
00099 
00100 /**
00101   * @}
00102   */
00103 
00104 /** @addtogroup STM32F10x_System_Private_Macros
00105   * @{
00106   */
00107 
00108 /**
00109   * @}
00110   */
00111 
00112 /** @addtogroup STM32F10x_System_Private_Variables
00113   * @{
00114   */
00115 
00116 /*******************************************************************************
00117 *  Clock Definitions
00118 *******************************************************************************/
00119 #ifdef SYSCLK_FREQ_HSE
00120   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00121 #elif defined SYSCLK_FREQ_24MHz
00122   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00123 #elif defined SYSCLK_FREQ_36MHz
00124   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00125 #elif defined SYSCLK_FREQ_48MHz
00126   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00127 #elif defined SYSCLK_FREQ_56MHz
00128   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00129 #elif defined SYSCLK_FREQ_72MHz
00130   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00131 #else /*!< HSI Selected as System Clock source */
00132   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00133 #endif
00134 
00135 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00136 /**
00137   * @}
00138   */
00139 
00140 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00141   * @{
00142   */
00143 
00144 static void SetSysClock(void);
00145 
00146 #ifdef SYSCLK_FREQ_HSE
00147   static void SetSysClockToHSE(void);
00148 #elif defined SYSCLK_FREQ_24MHz
00149   static void SetSysClockTo24(void);
00150 #elif defined SYSCLK_FREQ_36MHz
00151   static void SetSysClockTo36(void);
00152 #elif defined SYSCLK_FREQ_48MHz
00153   static void SetSysClockTo48(void);
00154 #elif defined SYSCLK_FREQ_56MHz
00155   static void SetSysClockTo56(void);  
00156 #elif defined SYSCLK_FREQ_72MHz
00157   static void SetSysClockTo72(void);
00158 #endif
00159 
00160 #ifdef DATA_IN_ExtSRAM
00161   static void SystemInit_ExtMemCtl(void); 
00162 #endif /* DATA_IN_ExtSRAM */
00163 
00164 /**
00165   * @}
00166   */
00167 
00168 /** @addtogroup STM32F10x_System_Private_Functions
00169   * @{
00170   */
00171 
00172 /**
00173   * @brief  Setup the microcontroller system
00174   *         Initialize the Embedded Flash Interface, the PLL and update the 
00175   *         SystemCoreClock variable.
00176   * @note   This function should be used only after reset.
00177   * @param  None
00178   * @retval None
00179   */
00180 void SystemInit (void)
00181 {
00182   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00183   /* Set HSION bit */
00184   RCC->CR |= (uint32_t)0x00000001;
00185 
00186   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00187 #ifndef STM32F10X_CL
00188   RCC->CFGR &= (uint32_t)0xF8FF0000;
00189 #else
00190   RCC->CFGR &= (uint32_t)0xF0FF0000;
00191 #endif /* STM32F10X_CL */   
00192   
00193   /* Reset HSEON, CSSON and PLLON bits */
00194   RCC->CR &= (uint32_t)0xFEF6FFFF;
00195 
00196   /* Reset HSEBYP bit */
00197   RCC->CR &= (uint32_t)0xFFFBFFFF;
00198 
00199   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00200   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00201 
00202 #ifdef STM32F10X_CL
00203   /* Reset PLL2ON and PLL3ON bits */
00204   RCC->CR &= (uint32_t)0xEBFFFFFF;
00205 
00206   /* Disable all interrupts and clear pending bits  */
00207   RCC->CIR = 0x00FF0000;
00208 
00209   /* Reset CFGR2 register */
00210   RCC->CFGR2 = 0x00000000;
00211 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00212   /* Disable all interrupts and clear pending bits  */
00213   RCC->CIR = 0x009F0000;
00214 
00215   /* Reset CFGR2 register */
00216   RCC->CFGR2 = 0x00000000;      
00217 #else
00218   /* Disable all interrupts and clear pending bits  */
00219   RCC->CIR = 0x009F0000;
00220 #endif /* STM32F10X_CL */
00221     
00222 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00223   #ifdef DATA_IN_ExtSRAM
00224     SystemInit_ExtMemCtl(); 
00225   #endif /* DATA_IN_ExtSRAM */
00226 #endif 
00227 
00228   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00229   /* Configure the Flash Latency cycles and enable prefetch buffer */
00230   SetSysClock();
00231 
00232 #ifdef VECT_TAB_SRAM
00233   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00234 #else
00235   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00236 #endif 
00237 }
00238 
00239 /**
00240   * @brief  Update SystemCoreClock according to Clock Register Values
00241   * @note   None
00242   * @param  None
00243   * @retval None
00244   */
00245 void SystemCoreClockUpdate (void)
00246 {
00247   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00248 
00249 #ifdef  STM32F10X_CL
00250   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00251 #endif /* STM32F10X_CL */
00252 
00253 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00254   uint32_t prediv1factor = 0;
00255 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00256     
00257   /* Get SYSCLK source -------------------------------------------------------*/
00258   tmp = RCC->CFGR & RCC_CFGR_SWS;
00259   
00260   switch (tmp)
00261   {
00262     case 0x00:  /* HSI used as system clock */
00263       SystemCoreClock = HSI_VALUE;
00264       break;
00265     case 0x04:  /* HSE used as system clock */
00266       SystemCoreClock = HSE_VALUE;
00267       break;
00268     case 0x08:  /* PLL used as system clock */
00269 
00270       /* Get PLL clock source and multiplication factor ----------------------*/
00271       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00272       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00273       
00274 #ifndef STM32F10X_CL      
00275       pllmull = ( pllmull >> 18) + 2;
00276       
00277       if (pllsource == 0x00)
00278       {
00279         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00280         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00281       }
00282       else
00283       {
00284  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00285        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00286        /* HSE oscillator clock selected as PREDIV1 clock entry */
00287        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
00288  #else
00289         /* HSE selected as PLL clock entry */
00290         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00291         {/* HSE oscillator clock divided by 2 */
00292           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00293         }
00294         else
00295         {
00296           SystemCoreClock = HSE_VALUE * pllmull;
00297         }
00298  #endif
00299       }
00300 #else
00301       pllmull = pllmull >> 18;
00302       
00303       if (pllmull != 0x0D)
00304       {
00305          pllmull += 2;
00306       }
00307       else
00308       { /* PLL multiplication factor = PLL input clock * 6.5 */
00309         pllmull = 13 / 2; 
00310       }
00311             
00312       if (pllsource == 0x00)
00313       {
00314         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00315         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00316       }
00317       else
00318       {/* PREDIV1 selected as PLL clock entry */
00319         
00320         /* Get PREDIV1 clock source and division factor */
00321         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00322         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00323         
00324         if (prediv1source == 0)
00325         { 
00326           /* HSE oscillator clock selected as PREDIV1 clock entry */
00327           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
00328         }
00329         else
00330         {/* PLL2 clock selected as PREDIV1 clock entry */
00331           
00332           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00333           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00334           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
00335           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
00336         }
00337       }
00338 #endif /* STM32F10X_CL */ 
00339       break;
00340 
00341     default:
00342       SystemCoreClock = HSI_VALUE;
00343       break;
00344   }
00345   
00346   /* Compute HCLK clock frequency ----------------*/
00347   /* Get HCLK prescaler */
00348   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00349   /* HCLK clock frequency */
00350   SystemCoreClock >>= tmp;  
00351 }
00352 
00353 /**
00354   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00355   * @param  None
00356   * @retval None
00357   */
00358 static void SetSysClock(void)
00359 {
00360 #ifdef SYSCLK_FREQ_HSE
00361   SetSysClockToHSE();
00362 #elif defined SYSCLK_FREQ_24MHz
00363   SetSysClockTo24();
00364 #elif defined SYSCLK_FREQ_36MHz
00365   SetSysClockTo36();
00366 #elif defined SYSCLK_FREQ_48MHz
00367   SetSysClockTo48();
00368 #elif defined SYSCLK_FREQ_56MHz
00369   SetSysClockTo56();  
00370 #elif defined SYSCLK_FREQ_72MHz
00371   SetSysClockTo72();
00372 #endif
00373  
00374  /* If none of the define above is enabled, the HSI is used as System clock
00375     source (default after reset) */ 
00376 }
00377 
00378 /**
00379   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
00380   *          before jump to __main
00381   * @param  None
00382   * @retval None
00383   */ 
00384 #ifdef DATA_IN_ExtSRAM
00385 /**
00386   * @brief  Setup the external memory controller. 
00387   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00388   *           This function configures the external SRAM mounted on STM3210E-EVAL
00389   *         board (STM32 High density devices). This SRAM will be used as program
00390   *         data memory (including heap and stack).
00391   * @param  None
00392   * @retval None
00393   */ 
00394 void SystemInit_ExtMemCtl(void) 
00395 {
00396 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
00397   required, then adjust the Register Addresses */
00398 
00399   /* Enable FSMC clock */
00400   RCC->AHBENR = 0x00000114;
00401   
00402   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
00403   RCC->APB2ENR = 0x000001E0;
00404   
00405 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00406 /*----------------  SRAM Address lines configuration -------------------------*/
00407 /*----------------  NOE and NWE configuration --------------------------------*/  
00408 /*----------------  NE3 configuration ----------------------------------------*/
00409 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00410   
00411   GPIOD->CRL = 0x44BB44BB;  
00412   GPIOD->CRH = 0xBBBBBBBB;
00413 
00414   GPIOE->CRL = 0xB44444BB;  
00415   GPIOE->CRH = 0xBBBBBBBB;
00416 
00417   GPIOF->CRL = 0x44BBBBBB;  
00418   GPIOF->CRH = 0xBBBB4444;
00419 
00420   GPIOG->CRL = 0x44BBBBBB;  
00421   GPIOG->CRH = 0x44444B44;
00422    
00423 /*----------------  FSMC Configuration ---------------------------------------*/  
00424 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00425   
00426   FSMC_Bank1->BTCR[4] = 0x00001011;
00427   FSMC_Bank1->BTCR[5] = 0x00000200;
00428 }
00429 #endif /* DATA_IN_ExtSRAM */
00430 
00431 #ifdef SYSCLK_FREQ_HSE
00432 /**
00433   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00434   *          and PCLK1 prescalers.
00435   * @note   This function should be used only after reset.
00436   * @param  None
00437   * @retval None
00438   */
00439 static void SetSysClockToHSE(void)
00440 {
00441   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00442   
00443   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
00444   /* Enable HSE */    
00445   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00446  
00447   /* Wait till HSE is ready and if Time out is reached exit */
00448   do
00449   {
00450     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00451     StartUpCounter++;  
00452   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00453 
00454   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00455   {
00456     HSEStatus = (uint32_t)0x01;
00457   }
00458   else
00459   {
00460     HSEStatus = (uint32_t)0x00;
00461   }  
00462 
00463   if (HSEStatus == (uint32_t)0x01)
00464   {
00465 
00466 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00467     /* Enable Prefetch Buffer */
00468     FLASH->ACR |= FLASH_ACR_PRFTBE;
00469 
00470     /* Flash 0 wait state */
00471     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00472 
00473 #ifndef STM32F10X_CL
00474     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00475 #else
00476     if (HSE_VALUE <= 24000000)
00477         {
00478       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00479         }
00480         else
00481         {
00482       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00483         }
00484 #endif /* STM32F10X_CL */
00485 #endif
00486  
00487     /* HCLK = SYSCLK */
00488     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00489       
00490     /* PCLK2 = HCLK */
00491     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00492     
00493     /* PCLK1 = HCLK */
00494     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00495     
00496     /* Select HSE as system clock source */
00497     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00498     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
00499 
00500     /* Wait till HSE is used as system clock source */
00501     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00502     {
00503     }
00504   }
00505   else
00506   { /* If HSE fails to start-up, the application will have wrong clock 
00507          configuration. User can add here some code to deal with this error */
00508   }  
00509 }
00510 #elif defined SYSCLK_FREQ_24MHz
00511 /**
00512   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
00513   *          and PCLK1 prescalers.
00514   * @note   This function should be used only after reset.
00515   * @param  None
00516   * @retval None
00517   */
00518 static void SetSysClockTo24(void)
00519 {
00520   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00521   
00522   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
00523   /* Enable HSE */    
00524   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00525  
00526   /* Wait till HSE is ready and if Time out is reached exit */
00527   do
00528   {
00529     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00530     StartUpCounter++;  
00531   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00532 
00533   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00534   {
00535     HSEStatus = (uint32_t)0x01;
00536   }
00537   else
00538   {
00539     HSEStatus = (uint32_t)0x00;
00540   }  
00541 
00542   if (HSEStatus == (uint32_t)0x01)
00543   {
00544 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
00545     /* Enable Prefetch Buffer */
00546     FLASH->ACR |= FLASH_ACR_PRFTBE;
00547 
00548     /* Flash 0 wait state */
00549     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00550     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
00551 #endif
00552  
00553     /* HCLK = SYSCLK */
00554     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00555       
00556     /* PCLK2 = HCLK */
00557     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00558     
00559     /* PCLK1 = HCLK */
00560     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00561     
00562 #ifdef STM32F10X_CL
00563     /* Configure PLLs ------------------------------------------------------*/
00564     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
00565     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00566     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
00567                             RCC_CFGR_PLLMULL6); 
00568 
00569     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00570     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
00571     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00572                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00573     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00574                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00575   
00576     /* Enable PLL2 */
00577     RCC->CR |= RCC_CR_PLL2ON;
00578     /* Wait till PLL2 is ready */
00579     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00580     {
00581     }   
00582 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00583     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00584     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00585     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00586 #else    
00587     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00588     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00589     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00590 #endif /* STM32F10X_CL */
00591 
00592     /* Enable PLL */
00593     RCC->CR |= RCC_CR_PLLON;
00594 
00595     /* Wait till PLL is ready */
00596     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00597     {
00598     }
00599 
00600     /* Select PLL as system clock source */
00601     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00602     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
00603 
00604     /* Wait till PLL is used as system clock source */
00605     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00606     {
00607     }
00608   }
00609   else
00610   { /* If HSE fails to start-up, the application will have wrong clock 
00611          configuration. User can add here some code to deal with this error */
00612   } 
00613 }
00614 #elif defined SYSCLK_FREQ_36MHz
00615 /**
00616   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
00617   *          and PCLK1 prescalers. 
00618   * @note   This function should be used only after reset.
00619   * @param  None
00620   * @retval None
00621   */
00622 static void SetSysClockTo36(void)
00623 {
00624   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00625   
00626   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
00627   /* Enable HSE */    
00628   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00629  
00630   /* Wait till HSE is ready and if Time out is reached exit */
00631   do
00632   {
00633     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00634     StartUpCounter++;  
00635   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00636 
00637   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00638   {
00639     HSEStatus = (uint32_t)0x01;
00640   }
00641   else
00642   {
00643     HSEStatus = (uint32_t)0x00;
00644   }  
00645 
00646   if (HSEStatus == (uint32_t)0x01)
00647   {
00648     /* Enable Prefetch Buffer */
00649     FLASH->ACR |= FLASH_ACR_PRFTBE;
00650 
00651     /* Flash 1 wait state */
00652     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00653     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
00654  
00655     /* HCLK = SYSCLK */
00656     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00657       
00658     /* PCLK2 = HCLK */
00659     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00660     
00661     /* PCLK1 = HCLK */
00662     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00663     
00664 #ifdef STM32F10X_CL
00665     /* Configure PLLs ------------------------------------------------------*/
00666     
00667     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
00668     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00669     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
00670                             RCC_CFGR_PLLMULL9); 
00671 
00672         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00673     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00674         
00675     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00676                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00677     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00678                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00679   
00680     /* Enable PLL2 */
00681     RCC->CR |= RCC_CR_PLL2ON;
00682     /* Wait till PLL2 is ready */
00683     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00684     {
00685     }
00686     
00687 #else    
00688     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00689     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00690     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00691 #endif /* STM32F10X_CL */
00692 
00693     /* Enable PLL */
00694     RCC->CR |= RCC_CR_PLLON;
00695 
00696     /* Wait till PLL is ready */
00697     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00698     {
00699     }
00700 
00701     /* Select PLL as system clock source */
00702     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00703     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
00704 
00705     /* Wait till PLL is used as system clock source */
00706     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00707     {
00708     }
00709   }
00710   else
00711   { /* If HSE fails to start-up, the application will have wrong clock 
00712          configuration. User can add here some code to deal with this error */
00713   } 
00714 }
00715 #elif defined SYSCLK_FREQ_48MHz
00716 /**
00717   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
00718   *          and PCLK1 prescalers. 
00719   * @note   This function should be used only after reset.
00720   * @param  None
00721   * @retval None
00722   */
00723 static void SetSysClockTo48(void)
00724 {
00725   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00726   
00727   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
00728   /* Enable HSE */    
00729   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00730  
00731   /* Wait till HSE is ready and if Time out is reached exit */
00732   do
00733   {
00734     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00735     StartUpCounter++;  
00736   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00737 
00738   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00739   {
00740     HSEStatus = (uint32_t)0x01;
00741   }
00742   else
00743   {
00744     HSEStatus = (uint32_t)0x00;
00745   }  
00746 
00747   if (HSEStatus == (uint32_t)0x01)
00748   {
00749     /* Enable Prefetch Buffer */
00750     FLASH->ACR |= FLASH_ACR_PRFTBE;
00751 
00752     /* Flash 1 wait state */
00753     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00754     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
00755  
00756     /* HCLK = SYSCLK */
00757     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00758       
00759     /* PCLK2 = HCLK */
00760     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00761     
00762     /* PCLK1 = HCLK */
00763     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00764     
00765 #ifdef STM32F10X_CL
00766     /* Configure PLLs ------------------------------------------------------*/
00767     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00768     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00769         
00770     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00771                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00772     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00773                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00774   
00775     /* Enable PLL2 */
00776     RCC->CR |= RCC_CR_PLL2ON;
00777     /* Wait till PLL2 is ready */
00778     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00779     {
00780     }
00781     
00782    
00783     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
00784     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00785     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
00786                             RCC_CFGR_PLLMULL6); 
00787 #else    
00788     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00789     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00790     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00791 #endif /* STM32F10X_CL */
00792 
00793     /* Enable PLL */
00794     RCC->CR |= RCC_CR_PLLON;
00795 
00796     /* Wait till PLL is ready */
00797     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00798     {
00799     }
00800 
00801     /* Select PLL as system clock source */
00802     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00803     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
00804 
00805     /* Wait till PLL is used as system clock source */
00806     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00807     {
00808     }
00809   }
00810   else
00811   { /* If HSE fails to start-up, the application will have wrong clock 
00812          configuration. User can add here some code to deal with this error */
00813   } 
00814 }
00815 
00816 #elif defined SYSCLK_FREQ_56MHz
00817 /**
00818   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
00819   *          and PCLK1 prescalers. 
00820   * @note   This function should be used only after reset.
00821   * @param  None
00822   * @retval None
00823   */
00824 static void SetSysClockTo56(void)
00825 {
00826   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00827   
00828   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
00829   /* Enable HSE */    
00830   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00831  
00832   /* Wait till HSE is ready and if Time out is reached exit */
00833   do
00834   {
00835     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00836     StartUpCounter++;  
00837   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00838 
00839   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00840   {
00841     HSEStatus = (uint32_t)0x01;
00842   }
00843   else
00844   {
00845     HSEStatus = (uint32_t)0x00;
00846   }  
00847 
00848   if (HSEStatus == (uint32_t)0x01)
00849   {
00850     /* Enable Prefetch Buffer */
00851     FLASH->ACR |= FLASH_ACR_PRFTBE;
00852 
00853     /* Flash 2 wait state */
00854     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00855     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
00856  
00857     /* HCLK = SYSCLK */
00858     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00859       
00860     /* PCLK2 = HCLK */
00861     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00862     
00863     /* PCLK1 = HCLK */
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00865 
00866 #ifdef STM32F10X_CL
00867     /* Configure PLLs ------------------------------------------------------*/
00868     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00869     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00870         
00871     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00872                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00873     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00874                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00875   
00876     /* Enable PLL2 */
00877     RCC->CR |= RCC_CR_PLL2ON;
00878     /* Wait till PLL2 is ready */
00879     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00880     {
00881     }
00882     
00883    
00884     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
00885     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00886     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
00887                             RCC_CFGR_PLLMULL7); 
00888 #else     
00889     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00890     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00891     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00892 
00893 #endif /* STM32F10X_CL */
00894 
00895     /* Enable PLL */
00896     RCC->CR |= RCC_CR_PLLON;
00897 
00898     /* Wait till PLL is ready */
00899     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00900     {
00901     }
00902 
00903     /* Select PLL as system clock source */
00904     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00905     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
00906 
00907     /* Wait till PLL is used as system clock source */
00908     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00909     {
00910     }
00911   }
00912   else
00913   { /* If HSE fails to start-up, the application will have wrong clock 
00914          configuration. User can add here some code to deal with this error */
00915   } 
00916 }
00917 
00918 #elif defined SYSCLK_FREQ_72MHz
00919 /**
00920   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
00921   *          and PCLK1 prescalers. 
00922   * @note   This function should be used only after reset.
00923   * @param  None
00924   * @retval None
00925   */
00926 static void SetSysClockTo72(void)
00927 {
00928   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00929   
00930   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
00931   /* Enable HSE */    
00932   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00933  
00934   /* Wait till HSE is ready and if Time out is reached exit */
00935   do
00936   {
00937     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00938     StartUpCounter++;  
00939   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00940 
00941   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00942   {
00943     HSEStatus = (uint32_t)0x01;
00944   }
00945   else
00946   {
00947     HSEStatus = (uint32_t)0x00;
00948   }  
00949 
00950   if (HSEStatus == (uint32_t)0x01)
00951   {
00952     /* Enable Prefetch Buffer */
00953     FLASH->ACR |= FLASH_ACR_PRFTBE;
00954 
00955     /* Flash 2 wait state */
00956     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00957     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
00958 
00959  
00960     /* HCLK = SYSCLK */
00961     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00962       
00963     /* PCLK2 = HCLK */
00964     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00965     
00966     /* PCLK1 = HCLK */
00967     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00968 
00969 #ifdef STM32F10X_CL
00970     /* Configure PLLs ------------------------------------------------------*/
00971     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00972     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00973         
00974     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00975                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00976     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00977                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00978   
00979     /* Enable PLL2 */
00980     RCC->CR |= RCC_CR_PLL2ON;
00981     /* Wait till PLL2 is ready */
00982     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00983     {
00984     }
00985     
00986    
00987     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
00988     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00989     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
00990                             RCC_CFGR_PLLMULL9); 
00991 #else    
00992     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
00993     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
00994                                         RCC_CFGR_PLLMULL));
00995     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
00996 #endif /* STM32F10X_CL */
00997 
00998     /* Enable PLL */
00999     RCC->CR |= RCC_CR_PLLON;
01000 
01001     /* Wait till PLL is ready */
01002     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01003     {
01004     }
01005     
01006     /* Select PLL as system clock source */
01007     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01008     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
01009 
01010     /* Wait till PLL is used as system clock source */
01011     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01012     {
01013     }
01014   }
01015   else
01016   { /* If HSE fails to start-up, the application will have wrong clock 
01017          configuration. User can add here some code to deal with this error */
01018   }
01019 }
01020 #endif
01021 
01022 /**
01023   * @}
01024   */
01025 
01026 /**
01027   * @}
01028   */
01029   
01030 /**
01031   * @}
01032   */    
01033 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
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